JP2003188713A - Superconducting single magnetic flux quantum circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily control synchronism between a body of a superconducting single magnetic flux quantum circuit and a latch type driver in the superconducting single magnetic flux quantum circuit having the latch type driver as a driver for data output. <P>SOLUTION: A data transfer circuit for simultaneously transferring data D1-D4 outputted sequentially from a body 9 of the superconducting single magnetic flux quantum circuit to latch type drivers 12-1 to 12-4 is composed of a demultiplexer 10, RS flip-flops 11-1 to 11-4, an SFQ pulse multiplexing circuit 13, a clock generating source 14 and a clock generating circuit 15. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting single magnetic flux quantum circuit having a latch type driver as a driver for outputting data.

[0002]

2. Description of the Related Art Superconducting single-flux-quantum circuits using Josephson devices have the characteristics of ultra-high speed and low energy, and are expected as constituent elements of future high-speed information processing systems. Since the signal amplitude of the single magnetic flux quantum circuit is as small as about 1 mV, it is necessary to amplify the voltage with a superconducting driver in order to transfer data to room temperature equipment such as existing semiconductor equipment.

Conventionally, SQUID has been used as a superconducting driver.
A non-latch type driver using an amplifier and a latch type driver in which a latch type Josephson junction is connected in series and parallel have been proposed. Latch type drivers are suitable for high-speed interfaces because they have a high output amplitude with a small number of junctions.

FIG. 5 is a circuit diagram showing an example of a conventional superconducting single magnetic flux quantum circuit using a non-latch type driver.
In FIG. 5, 1 is a superconducting single-flux-quantum circuit main body, 2 is a demultiplexer that divides data consisting of SFQ pulses sequentially output from the superconducting single-flux-quantum circuit main body 1 into four paths, 3-1 to 3-3. -4 is a non-latch type driver that amplifies the data output from the demultiplexer 2 and transfers it to the room temperature equipment.

FIG. 6 is a circuit diagram showing an example of a conventional superconducting single-flux quantum circuit using a latch type driver. Figure 6
Among them, 4 is a demultiplexer for superconducting single-flux-quantum circuit main body, 5 is a demultiplexer for distributing data consisting of SFQ pulses sequentially output from the superconducting single-flux-quantum circuit main body 4 into four paths, Is a latch type driver that amplifies the data output from the demultiplexer 5 and transfers it to room temperature equipment, 7 is a clock generation source, 8 is a superconducting single magnetic flux quantum circuit that multiplies the clock supplied from the clock generation source 7. It is a clock multiplication circuit that is supplied to the main body 4 and the demultiplexer 5.

[0006]

Since the superconducting single-flux-quantum circuit shown in FIG. 5 is provided with the non-latch type drivers 3-1 to 3-4 that operate with a DC bias as the data output driver, the superconducting single-flux quantum circuit is not provided. It is not necessary to perform synchronization control between the single magnetic flux quantum circuit body 1 and the non-latch type drivers 3-1 to 3-4.

However, since the superconducting single-flux quantum circuit shown in FIG. 6 is provided with latch type drivers 6-1 to 6-4 which operate with an AC bias as a driver for outputting data, the superconducting single-flux quantum circuit. It is necessary to perform synchronization control between the quantum circuit body 4 and the latch-type drivers 6-1 to 6-4.

Even a superconducting single-flux-quantum circuit having a latch type driver as a data output driver, if it is a small-scale circuit, for example, as shown in FIG.
It is easy to supply one clock from outside and distribute it. However, when it comes to large-scale superconducting single-flux quantum circuits, due to problems such as clock skew,
It becomes difficult to operate the whole with one global clock.

Therefore, in recent years, a method has been developed in which a superconducting single-flux quantum circuit is divided into several blocks and different clocks are used in each block. In this case, the clocks of the main body of the superconducting single magnetic flux quantum circuit and the latch type driver are independent clocks having different clock generation sources. Therefore, it is necessary to perform synchronization control between the two, but conventionally, no concrete method of synchronization control has been proposed.

In view of the above point, the present invention is a superconducting single-flux quantum circuit having a latch type driver as a data output driver, which is provided between the superconducting single-flux quantum circuit body and the latch type driver. An object of the present invention is to provide a superconducting single-flux-quantum circuit in which synchronization control can be easily performed and data from the main body of the superconducting single-flux-quantum circuit can be easily output to the outside.

[0011]

SUMMARY OF THE INVENTION The present invention has a superconducting single-flux quantum circuit body and a latch type driver group for data output having a clock source different from that of the superconducting single-flux quantum circuit body. A superconducting single-flux-quantum circuit, which stores a plurality of data sequentially output from the superconducting single-flux-quantum circuit body, and stores a plurality of stored data when a clock is supplied to the latch type driver group. It has a data transfer circuit that transfers data to the latch type driver group at the same time.

According to the present invention, a plurality of data that are sequentially output from the superconducting single-flux-quantum-circuit main body are stored, and when the clock is supplied to the latch type driver group, the stored plurality of data are stored. Since it has a data transfer circuit that transfers data to the latch type driver group at the same time, the synchronous control between the superconducting single magnetic flux quantum circuit body and the latch type driver can be easily performed.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a first embodiment and a second embodiment of the present invention will be described with reference to FIGS.

(First Embodiment ... FIGS. 1 and 2) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, 9 is a superconducting single-flux-quantum-circuit main body, 10 is a demultiplexer which distributes the data D1 to D4 consisting of SFQ pulses sequentially output from the superconducting single-flux-quantum circuit main body 9 into four paths. The demultiplexer 10 is configured to output the data D4 and the data / D4 obtained by inverting the data D4 at the same time.

11-1 to 11-4 are demultiplexers 1
RS flip-flops 12-1 to 12-1 in which data D1 to D4 sequentially output from 0 are sequentially given to the set terminal S
Reference numeral 2-4 is a latch-type driver that amplifies the data D1 to D4 output from the RS flip-flops 11-1 to 11-4 and transfers the amplified data D1 to D4 to an external device such as a room temperature device.

Reference numeral 13 denotes S for merging the data D4 and / D4.
This is an FQ pulse merging circuit, and this SFQ pulse merging circuit 13 outputs data D4, / D4 from the demultiplexer 10.
When is not output, "0" is output and the data D4, /
When D4 is output, either data D4 or / D4 is "1", and therefore "1" is output.

Reference numeral 14 is a clock generation source, and 15 is a SFQ which receives a clock CK output from the clock generation source 14.
A clock generation circuit that generates a clock composed of pulses, 16 is an SFQ pulse generation circuit that generates an SFQ pulse in response to the rising edge of the clock CK output from the clock generation source 14, and 17 is an SFQ pulse merging at the set terminal S. Connect to the output terminal of circuit 13 and reset terminal R
RS connected to the output terminal of the SFQ pulse generation circuit 16
The flip-flop, 18 is a latch type driver.

In the first embodiment of the present invention, the demultiplexer 10, the RS flip-flops 11-1 to 11-4, the SFQ pulse merging circuit 13, the clock generation source 14 and the clock generation circuit 15 are combined to form a single superconducting magnetic flux. Quantum circuit body 9
A data transfer circuit for simultaneously transferring the data D1 to D4 sequentially output to the latch type drivers 12-1 to 12-4 is configured. Further, the superconducting single-flux quantum circuit body 9 and the demultiplexer 10 include a clock generation source 14
A clock source is prepared separately from the above.

The clock output from the RS flip-flop 17 is the RS flip-flops 11-1 to 11-1.
1 to 4 are supplied to the reset terminal R, and further to the demultiplexer 10 as a transmission request signal SEND requesting transmission of the data D1 to D4, and data D1 to D1 from the latch type drivers 12-1 to 12-4. The data output signal DOUT indicating that D4 is output is given to the latch type driver 18.

FIG. 2 is a waveform diagram showing an operation example of the first embodiment of the present invention. First, in the first step, when the transmission request signal SEND is given from the clock generation circuit 15 to the demultiplexer 10, the demultiplexer 10 outputs SFQ.
The data D1 to D4 consisting of pulses are output in this order, and these four data D1 to D4 are written in this order to the RS flip-flops 11-1 to 11-4.

Further, the data D from the demultiplexer 10
When 4 is output, the data / D4 is also output at the same time. As a result, the data D4 is written in the RS flip-flop 11-4, and at the same time, the SFQ pulse is fed from the SFQ pulse merging circuit 13 to the set terminal S of the RS flip-flop 17. Is given, the RS flip-flop 17 stores "1". That is, the RS flip-flops 11-1 to 11-1
When all the data D1 to D4 are written in 1-4, R
The S flip-flop 17 will store "1".

Next, as the second stage, the clock generation source 1
4 outputs the clock CK, and in response to the rising edge of the clock CK, the SFQ pulse generation circuit 16 outputs SF
When a Q pulse is generated and this SFQ pulse is applied to the reset terminal R of the RS flip-flop 17, the RS flip-flop 17 is reset, and at the same time, an SFQ pulse is output from the RS flip-flop 17, and this SFQ pulse is output.
The pulse is applied to the reset terminals R of the RS flip-flops 11-1 to 11-4.

As a result, the RS flip-flop 11-1
The data D1 to D4 stored in 11 to 11-4 are simultaneously transferred to the latch type drivers 12-1 to 12-4.
At this time, the clock CK is supplied to the latch-type drivers 12-1 to 12-4 as an AC bias current, so that the latch-type drivers 12-1 to 12-4 have the data D.
1 to D4 will be amplified and output to the room temperature equipment.

The SFQ pulse output from the RS flip-flop 17 is supplied to the latch type driver 18 as the data output signal DOUT and to the demultiplexer 10 as the transmission request signal SEND.
As a result, the latch type driver 18 outputs the data output signal D
Amplify and output OUT, and latch type drivers 12-1 to 12-1
12-4 indicates that the data D1 to D4 output from the demultiplexer 10-4 are valid, and the demultiplexer 10 sends the next data D1.
~ D4 will be output.

Here, if the data D4 and / D4 are not output from the demultiplexer 10, that is,
Data D1 is stored in the RS flip-flops 11-1 to 11-4.
If a SFQ pulse is applied from the SFQ pulse generation circuit 16 to the reset terminal R of the RS flip-flop 17 before all of D4 to D4 have been written, no clock is output from the RS flip-flop 17, so the RS flip-flop 11- 1 to 11-4 wait for the next clock without changing the state. At this time, the latch type drivers 12-1 to 12-4 and 18 output "0",
If the output of the latch type driver 18 is "0", the problem does not occur if it is arranged so that the outputs of the drivers 12-1 to 12-4 are ignored.

As described above, according to the first embodiment of the present invention, the latch type drivers 12-1 to 12-4 use the clock generation source 14, and the superconducting single-flux quantum circuit body 9 is different. Although configured to use a clock source, a demultiplexer 10 and an RS flip-flop 11
Data D1 to D4 sequentially output from the superconducting single magnetic flux quantum circuit body 9 by the -1 to 11 to 4, the SFQ pulse merging circuit 13, the clock generation source 14, and the clock generation circuit 15.
Of the superconducting single magnetic flux quantum circuit main body 9 and the latch type drivers 12-1 to 12-4, because a data transfer circuit for simultaneously transferring the data to the latch type drivers 12-1 to 12-4 is configured.
It is possible to easily perform a synchronous control between the data and the data D1 to D4 sequentially output from the superconducting single magnetic flux quantum circuit body 9 to the room temperature equipment.

(Second Embodiment ... FIGS. 3 and 4) FIG. 3 is a circuit diagram showing a second embodiment of the present invention. Second of the present invention
In the embodiment, the latch type drivers 12-1 to 12-12
-4, 18, RS flip-flops 19-1 to 19-1
19-4 and 20 are provided, and the RS flip-flop 11 is provided.
The outputs of -1 to 11-4 are RS flip-flops 19-1.
19-4 is supplied to the set terminals S of the RS flip-flops 20 and the output of the RS flip-flop 17 is supplied to the set terminals S of the RS flip-flops 20 as the data output signal DOUT.

Further, SFQ pulse generation circuits 21-1 to 21-4, 22 for generating SFQ pulses in response to the rising edge of the clock CK output from the clock generation source 14.
Are provided, and these SFQ pulse generation circuits 21-1 and 21-2 are provided.
The SFQ pulses output from 1-4 and 22 are applied to the reset terminals R of the RS flip-flops 19-1 to 19-4 and 20.
Is configured to supply.

Further, instead of the clock generating circuit 15 shown in FIG. 1, a clock generating circuit 24 having a delay circuit 23 interposed between the SFQ pulse generating circuit 16 and the RS flip-flop 17 is provided. Others are the same as those of the first embodiment of the present invention shown in FIG.

In the second embodiment of the present invention, the demultiplexer 10 and the RS flip-flops 11-1 to 11-4,
19-1 to 19-4, SFQ pulse merging circuit 13, clock generation source 14, and SFQ pulse generation circuits 21-1 to 21
-4 and the clock generation circuit 24 constitute a data transfer circuit for simultaneously transferring the data D1 to D4 sequentially output from the superconducting single magnetic flux quantum circuit body 9 to the latch type drivers 12-1 to 12-4. There is.

FIG. 4 is a waveform diagram showing an operation example of the second embodiment of the present invention. First, as the first step, when the transmission request signal SEND is supplied from the clock generation circuit 24 to the demultiplexer 10, the demultiplexer 10 outputs SFQ.
The data D1 to D4 consisting of pulses are output in this order, and these four data D1 to D4 are written in this order to the RS flip-flops 11-1 to 11-4.

Next, as the second stage, the clock generation source 1
4 outputs the clock CK, and in response to the rising timing of this clock CK, the SFQ pulse generation circuit 16 generates an SFQ pulse, and this SFQ pulse is R
When applied to the reset terminal R of the S flip-flop 17, the RS flip-flop 17 is reset, and at the same time, an SFQ pulse is output from the RS flip-flop 17, and this SFQ pulse is transmitted to the RS flip-flop 11-1.
To 11-4 reset terminals R.

As a result, the RS flip-flop 11-1
The data D1 to D4 stored in 11 to 11-4 are simultaneously transferred to and stored in the RS flip-flops 19-1 to 19-4. The SFQ pulse output from the RS flip-flop 17 is R as the data output signal DOUT.
While being sent to and stored in the S flip-flop 20,
The transmission request signal SEND becomes the request for the next data to the demultiplexer 10.

Here, if the data D4 and / D4 are not output from the demultiplexer 10, that is,
Data D1 is stored in the RS flip-flops 11-1 to 11-4.
If a SFQ pulse is applied from the SFQ pulse generation circuit 16 to the reset terminal R of the RS flip-flop 17 before all of D4 to D4 have been written, no clock is output from the RS flip-flop 17, so the RS flip-flop 11- 1 to 11-4 wait for the next clock without changing the state.

In the third step, when the clock CK is output from the clock generation source 14, the SFQ pulse generation circuit 2
Each of 1-1 to 21-4 and 22 outputs an SFQ pulse in response to the rising edge of the clock CK, and these SFQ pulses are RS flip-flops 19-1 to 19-4 and 20.
Is applied to the reset terminal R of.

As a result, the RS flip-flop 19-1
Data 19 to 19-4 are simultaneously transferred to the latch type drivers 12-1 to 12-4 and R
The data output signal DOUT is supplied from the S flip-flop 20 to the latch type driver 18. At this time, since the clock CK is supplied as an AC bias current to the latch type drivers 12-1 to 12-4 and 18, the latch type drivers 12-1 to 12-4 amplify the data D1 to D4. The latch type driver 18 outputs the data output signal DOUT to the room temperature equipment.

As described above, according to the second embodiment of the present invention, the latch type drivers 12-1 to 12-4 use the clock generation source 14, and the superconducting single magnetic flux quantum circuit body 9 is different. Although configured to use a clock source, a demultiplexer 10 and an RS flip-flop 11
-1 to 11 to 4 and 19-1 to 19-4, the SFQ pulse merging circuit 13, the clock generation source 14, the SFQ pulse generation circuits 21-1 to 21-4, and the clock generation circuit 24, the superconducting single magnetic flux. The data D1 to D4 sequentially output from the quantum circuit main body 9 are simultaneously latched drivers 12-1 to 12-
Since it constitutes a data transfer circuit for transferring data to a superconducting single flux quantum circuit main body 9 and a latch type driver 12-1.
It is possible to easily perform the synchronous control with the above-mentioned devices 12 to 4 and to easily output the data D1 to D4 output from the superconducting single magnetic flux quantum circuit body 9 to the room temperature equipment.

Here, in the first embodiment of the present invention, when the clock CK has a high speed of, for example, about 10 GHz, the width of the clock CK becomes short and the latch type drivers 12-1 to 12-4 receive the clock CK. Is supplied, the data D1 to D4 stored in the RS flip-flops 11-1 to 11-4 are transferred to the latch type driver 12-
1 to 12-4 cannot be transferred and the clock CK is not supplied to the latch type drivers 12-1 to 12-4, the RS flip-flops 11-1 to 11-
Then, the data D1 to D4 stored in No. 4 are transferred to the latch type drivers 12-1 to 12-4.

On the other hand, according to the second embodiment of the present invention, RS flip-flops 19-1 to 19-4 are added and the clock CK is supplied to the latch type drivers 12-1 to 12-4. Sometimes RS flip-flop 19
-1 to 19-4 to Latch type drivers 12-1 to 12-
Since the data D1 to D4 are supplied to 4 simultaneously, even if the clock CK has a high speed of, for example, about 10 GHz, this can be dealt with.

[0040]

As described above, according to the present invention, a plurality of data sequentially output from the superconducting single magnetic flux quantum circuit main body are stored and stored when the clock is supplied to the latch type driver group. Since it has a data transfer circuit that simultaneously transfers multiple data to the latch type driver group, the superconducting single-flux quantum circuit main body and the latch type driver can be easily synchronized and controlled. The data from the main body of the single magnetic flux quantum circuit can be easily output to the outside.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operation example of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a waveform diagram showing an operation example of the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional superconducting single-flux quantum circuit using a non-latch type driver.

FIG. 6 is a circuit diagram showing an example of a conventional superconducting single-flux quantum circuit using a latch type driver.

[Explanation of symbols] (Figure 1, Figure 3) 11-1 to 11-4 ... RS flip-flop 12-1 to 12-4 ... Latch type driver 13 ... SFQ pulse merging circuit 16 ... SFQ pulse generation circuit 17 ... RS flip-flop 18 ... Latch type driver 19-1 to 19-4, 20 ... RS flip-flop 21-1 to 21-4, 22 ... SFQ pulse generation circuit

Claims (5)

[Claims] 1. A superconducting single-flux-quantum circuit having a superconducting single-flux-quantum circuit body and a latch-type driver group for data output, which has a clock source different from that of the superconducting-single-flux quantum circuit body. And storing a plurality of data sequentially output from the superconducting single-flux-quantum circuit main body, and storing the plurality of data at the same time when the clock is supplied to the latch-type driver group. Superconducting single-flux-quantum circuit having a data transfer circuit for transferring to a type driver group. 2. The demultiplexer, wherein the data transfer circuit distributes the data sequentially output from the main body of the superconducting single magnetic flux quantum circuit to a plurality of paths, and the plurality of data output from the demultiplexer temporarily. A control for controlling the memory circuit group to be stored and the memory circuit group so that the data stored in the memory circuit group is simultaneously transferred to the latch type driver group when a clock is supplied to the memory type driver group. The superconducting single-flux quantum circuit of claim 1, wherein the circuit comprises a circuit. 3. The storage circuit group includes an RS flip-flop whose set terminal is supplied with data, and the control circuit generates an SFQ pulse in response to a rising edge of a clock supplied to the latch type driver group. A pulse generation circuit and a reset terminal are connected to an output terminal of the SFQ pulse generation circuit, an output terminal is connected to a reset terminal of an RS flip-flop forming the storage circuit group, and all RS flip-flops forming the storage circuit group are connected. The superconducting single-flux-quantum circuit according to claim 2, further comprising an RS flip-flop that is set when data is written to the superconducting single-flux quantum circuit. 4. The demultiplexer, wherein the data transfer circuit distributes the data sequentially output from the superconducting single magnetic flux quantum circuit main body to a plurality of paths, and the plurality of data output from the demultiplexer temporarily. First to remember
Memory circuit group, a second memory circuit group for temporarily storing data output from the first memory circuit group, and a plurality of data stored in the first memory circuit group at the same time as the second memory circuit group. To be stored in the memory circuit group for storage, and when the clock is supplied to the latch type driver group, the data stored in the second memory circuit group is simultaneously transferred to the driver of the driver group. The superconducting single-flux-quantum circuit according to claim 1, further comprising a control circuit for controlling the first and second memory circuit groups. 5. The first and second memory circuit groups each include an RS flip-flop whose data is supplied to a set terminal, and the control circuit responds to a rising edge of a clock supplied to the latch type driver group. A first SFQ pulse generating circuit for generating an SFQ pulse, a delay circuit for delaying the SFQ pulse output by the SFQ pulse generating circuit, a reset terminal is connected to an output terminal of the delay circuit, and an output terminal is connected to the first terminal. A clock generation circuit having RS flip-flops connected to the reset terminals of the RS flip-flops forming the storage circuit group and set when data is written to all the RS flip-flops forming the first storage circuit group; A clock is provided corresponding to each of the RS flip-flops forming the second memory circuit group and is supplied to the latch type driver group. It has an SFQ pulse generation circuit group which generates an SFQ pulse in response to the rising of the lock and supplies the SFQ pulse to the reset terminal of the RS flip-flop forming the second memory circuit group. The superconducting single-flux quantum circuit according to claim 4.