JP2003188653A - Electronic components for radio communication and semiconductor integrated circuit for communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias circuit capable of realizing a high frequency power amplifier circuit with less change in gain irrespective of variation in temperature, i.e., low temperature-dependent gain. <P>SOLUTION: Electronic components for radio communication includes a high frequency power amplifier circuit (210) amplifying and outputting input high frequency signals by power amplifying elements (211 to 213) comprising FETs, and a bias circuit (220) feeding a bias voltage applied to a gate of the power amplifying elements to make the elements operate in a linear region. The bias circuit is configured so as to generate a bias voltage compensating temperature-dependent properties of the gain and drain current of the power amplifying element. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency power amplifier circuit for amplifying and outputting an input high frequency signal by a power amplifier element composed of a field effect transistor, and a radio communication device such as a mobile phone incorporating the high frequency power amplifier circuit. The present invention relates to a technique effectively applied to, and particularly to a temperature compensation technique using a bias circuit that generates a gate bias voltage that causes a power amplification FET included in a high frequency power amplification circuit to operate in a linear region.

[0002]

2. Description of the Related Art A MOSF is provided at a transmission side output stage of a wireless communication device (mobile communication device) such as an automobile telephone and a mobile telephone.
ET (Metal Oxide Semiconductor Field-Effect-Trans
istor) or a GaAs-MESFET or other semiconductor amplifying device (power amplifying FET) is connected in cascade to form a multistage high frequency power amplifying circuit. Currently, GSM (Global System) is used as a communication method for wireless communication devices such as mobile phones.
for Mobile Communication) and CDMA (Code Div)
There are multiple methods such as ision Multiple Access).
With mobile phones that have adopted these methods, the output (transmission power) is changed to adapt to the surrounding environment by the power level instruction signal from the base station according to the usage environment, and the call is performed to communicate with other mobile phones. The system is configured to prevent interference. Specifically, an APC that outputs a voltage according to a power level instruction signal from the base station
(Automatic Power Control) Power amplification FE so that the output voltage Vapc of the circuit provides the output power required for the call.
The gate bias voltage of T is controlled so that a predetermined bias current (also referred to as an idling current) is supplied.

FIG. 8 shows an example of a gate bias circuit for a power amplification FET in a conventional CDMA system. PA1 and PA2 are high frequency power amplification amplifiers including power amplification FETs. In the circuit of FIG. 8, a MOSFET having a gate and a drain coupled in series with a power amplification FET
Q0 and Q0 'are provided to connect the APC circuit to the MOSFET Q
0, Q0 'is supplied with a constant current Icont via resistors R3, R3', and the bias currents of the amplifiers PA1, PA2 are generated by Q0, Q0 ', and the constant current Icont supplied from the APC circuit is the temperature. By configuring the APC circuit so as to be constant regardless of the temperature variation, the gain of the high frequency power amplification amplifier is constant regardless of temperature fluctuation (for example, Japanese Patent Laid-Open No. 2000-151310).

[0004]

However, when the inventors of the present invention have made a detailed examination of the bias method in the high frequency power amplifier circuit used in the CDMA wireless communication system, the output current from the APC circuit is irrespective of the temperature. It has been found that the gain of the high frequency power amplifier circuit changes considerably even if it is constant. In particular,
As shown by the broken line B in FIG. 5, the temperature is from -20 ° C to 85 ° C.
It was found that the gain dropped from 26.5 dB to 23.5 dB by about 3 dB when changed to. Therefore, as a result of analyzing the phenomenon, the inventors of the present invention have found that the threshold voltage of the power amplification FET has a negative temperature characteristic. Therefore, as shown in FIG. Current characteristic curve (hereinafter simply referred to as voltage-current characteristic) C
And the voltage-current characteristic curve D at low temperature are different. In the CDMA high-frequency power amplifier circuit, the power amplifier FET operates linearly in a region lower than the point Q corresponding to the intersection of the voltage-current characteristic curve C at high temperature and the voltage-current characteristic curve D at low temperature. To be done. Then, in such a region, it became clear that the temperature dependence of the on-resistance remarkably affects the gain, so that the gain decreases as the temperature rises. Note that in the GSM method or the like for performing GMSK modulation, the power amplification FET is operated in a region higher than the point Q, that is, a region (saturation region) in which the drain current decreases as the temperature increases. In addition, in the GSM system and the like, a system in which the power amplifier FET is biased so as to operate at the point Q has been proposed.

An object of the present invention is to provide a high frequency power amplifier circuit for operating a power amplifier FET in a linear region,
Even if the temperature fluctuates, the gain does not change so much.
It is an object of the present invention to provide a semiconductor integrated circuit for wireless communication having a bias circuit given to the above and an electronic component (high frequency power module) for wireless communication including such a semiconductor integrated circuit. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0006]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, a high-frequency power amplifier circuit that amplifies and outputs an input high-frequency signal by a power amplifier element including a field effect transistor, and a bias that is applied to the gate of the power amplifier element to operate the transistor in a linear region. In a wireless communication electronic component including a bias circuit, the bias circuit is configured to generate a bias voltage that compensates for the temperature dependence of the drain current of the power amplification element. According to the means described above, when the temperature changes and the gate-source voltage-drain current characteristic of the power amplification element changes, a bias that compensates for the change is applied to the power amplification element to change the bias current. Therefore, the temperature dependence of the gain of the high frequency power amplifier circuit is reduced. Specifically, the bias circuit includes a MOSFET that is current-mirror connected to the power amplification element,
A bias current is supplied to the power amplification element so as to compensate the temperature dependence of its gain and drain current.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of a high frequency power amplifier circuit and its bias circuit which constitute a CDMA communication system to which the present invention is applied. In FIG. 1, 210 is a high frequency power amplification circuit including a power amplification FET, 220 is a power amplification F of the high frequency power amplification circuit 210.
A bias circuit 230 generates a bias voltage applied to the gate of the ET, and an operation voltage generator 230 generates operation voltages Vdd1 and Vdd2 applied to the drain of the power amplification FET. Although not particularly limited, the high frequency power amplifier circuit 210 of this embodiment has three power amplifier FETs 21.
1, 212, 213, of which the latter FET 21
2, 213 are provided in parallel, and the drain terminals of the first-stage FET 211 are connected to the gate terminals of the second-stage FETs 212, 213, so that they are configured as a two-stage amplifier circuit as a whole.
Further, the high frequency power amplifier circuit 210 includes the first stage FET 211.
To the gate terminal of the high frequency signal Pin via the capacitive element C2.
Is input, the drain terminals of the parallel FETs 212 and 213 in the subsequent stage are connected to the output terminal Pout via the capacitive element C9, and the DC component of the high frequency input signal Pin is cut and the AC component is amplified and output. The output level at this time is controlled by the gate bias voltages Vg1 and Vg2 from the bias circuit 220. Accordingly
The bias circuit 220 also generates a bias voltage Vg1 applied to the gate of the power amplification FET 211 and a second bias circuit 222 generates a bias voltage Vg2 applied to the gates of the power amplification FETs 212 and 213. It consists of and. Since the first and second bias circuits 221 and 222 have the same configuration, the configuration of one circuit 221 will be described below.

The bias circuit 221 is a power amplification FE.
A resistor R1 is provided between the gate terminal of T211 and the ground point of the circuit.
MOSFET Q0 which is connected via 2 and constitutes a current mirror circuit with the power amplification FET 211,
SFET Q0 gate terminal and bias voltage terminal Vbias
A resistor R3 and a MOSFET Q connected in series between
4, a MOSFET Q1 connected between the gate terminal of the MOSFET Q4 and the ground point, and a series connection between the current input terminal to which the constant current Icont supplied from the automatic power control circuit is input and the ground point. Connected resistors R1 and R2
And MOSFETs Q2 and Q3. The MOSFETs Q0, Q1 and Q2 are so-called diode-connected with their gates and drains coupled to each other. Further, the voltage of the connection node n2 between the resistors R1 and R2 is applied to the gate terminal of the MOSFET Q1. The resistor R12 has a function of preventing the high frequency input signal Pin from leaking to the bias circuit 221 side. The resistor R3 is a resistor for adjusting the drain current flowing through the power amplification FET 211 according to the application system. In this embodiment, a highly accurate discrete component is used and is connected as an external resistor. MOSFE
The bias voltage Vbias applied to the voltage terminal connected to the drain terminal of the TQ4 may be a constant voltage, and may be a battery voltage such as 3.5V.

In FIG. 1, symbols MS1 to MS4 are microstrip lines that act as inductance elements for matching impedances between the respective stages of the high frequency power amplifier circuit 210, and MS5 is FETs 212 and 213.
, MS7 and MS7 are microstrip lines for matching impedance between the output voltage Pout and the output terminal Pout. Although not particularly limited, in the present embodiment, among the elements constituting the high frequency power amplifier circuit 210, the power amplifier FETs 211 to 213,
MOSFETs Q0 and Q that form a current mirror with this
0 ′ and the resistors R12 and R13 are formed as a semiconductor integrated circuit IC1 on one semiconductor chip. Where M
The OSFETs Q0 and Q0 ′ are the power amplification FETs 211 to 211.
213 has the same conductivity type (n-channel type) and has the same structure so that it has the same temperature characteristic (threshold voltage Vth has a negative temperature characteristic, that is, ΔVth / ΔT = negative). To be done. Further, among the elements constituting the bias circuit 220, the elements other than the MOSFETs Q0, Q0 'and the resistors R12, R13 are formed as a semiconductor integrated circuit IC2 on another semiconductor chip. Bias circuit 2
The resistors R1 and R2 that form 20 have a positive temperature characteristic, and the MOSFETs Q0 to Q3 are n-channel type and their threshold voltage has a negative temperature characteristic.

These semiconductor integrated circuits IC1,
IC2 and resistors R3 and R as discrete components
Elements such as 3 ′ and capacitors C1 to C9 are mounted on a common ceramic substrate to constitute one electronic component for wireless communication. The microstrip lines MS1 to M
S7 is formed of a conductive layer pattern of copper or the like formed on the ceramic substrate so as to have a desired inductance value. In this specification, a power amplifier element or a semiconductor integrated circuit including the power amplifier element, a semiconductor integrated circuit including a bias circuit, a resistor element, a capacitor element, or the like mounted on a ceramic substrate is referred to as a high-frequency power module.

Next, the operation of the bias circuit 220 will be described in detail with reference to FIG. 2 is the first of FIG.
The bias circuit 221 is shown by changing the positions of the elements and has the same circuit configuration. In FIG. 2, the bias current flowing through the power amplification FET 211 is Ib and the resistance R is
1, the current flowing through R2 is Ig, the current flowing through the MOSFET Q1 is Iq1, and the current flowing through the resistor R3 is Id.
Further, it is assumed that the input current Icont is constant even if the temperature changes. The current Iq3 flowing through Q1 and the current I flowing through the resistor R3
Since d is the input current Icont branched, Iq1
+ Id = Icont = constant.

First, qualitatively explaining the circuit of FIG.
As described above, the MOSFETs Q1, Q2, and Q3 have temperature characteristics in which the threshold voltages are negative, respectively. Therefore, when the temperature rises, the threshold voltages of the Q1, Q2, and Q3 respectively decrease, and a large amount of current flows. To do. On the other hand, the resistors R1 to R1
Although R3 has a positive temperature characteristic, the gate terminal of the MOSFET Q1 is connected to the connection node n2 between the resistors R1 and R2, and the gate voltage of Q1 is determined by the ratio of the resistors R1 and R2. MOSF even if the resistance changes
The gate voltage of ET Q1 remains almost constant, that is, the drain current Iq1 of Q1 is not affected by the temperature dependence of the resistors R1 and R2. Here, the current path and Q of MOSFET Q1
Comparing the current paths of Q2 and Q3, since Q2 and Q3 are stacked in two stages, the amount of change in the threshold voltage is twice the amount of change in the threshold voltage of Q1. Therefore, when the temperature rises, the current Ig flowing through the resistors R1 and R2 is allowed to flow more than the current Iq1 flowing through Q1. As a result, the current Id flowing through the resistors R1 and R2 increases and the node n1
Voltage Vn1 becomes high, and the drain current of the MOSFET Q4, that is, the current Id of the resistor R3 increases. Here, since the MOSFET Q4 has a negative threshold temperature characteristic, it tries to flow a large amount of drain current when the temperature rises, but the resistor R3 in series with Q4 has a positive temperature characteristic and has a current Id of Since they act in a decreasing direction, they cancel each other out. Therefore, the increase in the current Id depends on the increase in the gate voltage of the MOSFET Q4. Then, since this current Id directly flows to the MOSFET Q0, the drain current of Q0 increases.

On the other hand, MOSFET Q0 and power amplification EF
Since the current mirror connection with T211 is made, when the current Id is increased, the current Ib flowing between the drain and the source of the EFT211 is also increased. However,
In the CDMA system, the power amplification EFT211 operates in a region below the Q point, that is, in a region where the current-gain characteristic shows a negative temperature characteristic when the drain current is constant. Therefore, when the temperature rises, the gain of the power amplification EFT211 decreases. However, as the drain current Id of Q0 increases, the drain current Ib of the power amplification EFT211 also increases and acts to increase the gain, so that the decrease in the gain is prevented. The resistance R12 between the MOSFET Q0 and the power amplification FET 211 has a positive temperature characteristic, but since no current flows through R12, the temperature characteristic has no effect on the current Ib.

Next, the operation of the circuit shown in FIG. 2 will be described using equations. The resistance value of the resistor R1 is r1, the resistance value of the resistor R2 is r2, and the gate-source voltage of the MOSFET Q1 is V
Assuming that the gate-source voltage of the MOSFETs Q2 and Q3 is Vgs2, the current Ig flowing through the resistor R2 is represented by the following equation Ig = (Vgs1-2Vgs2) / r2 (1). When the potential of the node n2 is Vn2, Vn2 is expressed by the following equation Vn2 = Ig (r1 + r2) + 2Vgs2 (2). Substituting equation (1) into equation (2), Vn2 = (Vgs1-2Vgs2) (r1 + r2) / r2 + 2Vgs2 = (1 + r1 / r2) (Vgs1-2Vgs2) + 2Vgs2 = (1 + r1 / r2) Vgs1-2 (r1 / r2 ) Vgs2 (3). On the other hand, if the gate-source voltage of the MOSFET Q0 is Vgs0, the gate-source voltage of the MOSFET Q4 is Vgs4, and the resistance value of the resistor R3 is r3, the current Id flowing through the resistor R3 is given by the following equation Id = (Vn2- Vgs4-Vgs0) / r3 (4) Substituting equation (3) into equation (4) yields Id = {(1 + r1 / r2) Vgs1-2 (r1 / r2) Vgs2-Vgs4-Vgs0} .r3 (5).

Here, the general formula of MOSFET I = β (V
gs-Vth) 2/2 modified formula Vgs = √ (2I / β) +
The following expression obtained by differentiating Vth with temperature T, ΔVgs / ΔT = √ (1 / 2βI) ΔI / ΔT + ΔVth /
Since ΔI / ΔT≈0 at ΔT, it can be expressed as ΔVgs / ΔT≈ΔVth / ΔT (6). In addition, MOSFETs Q1, Q2, Q3
Since Q4 is formed on the same chip, the threshold voltage Vth is the same. Therefore, when the threshold voltage of the MOSFET Q0 is set to VTH and the equation (5) is differentiated and the equation (6) is substituted, the following equation ΔId / ΔT = {-(r1 / r2) ΔVth / ΔT-ΔV
TH / ΔT} / r3 is obtained. Here, the resistors R1, R2, R3 have positive temperature characteristics, that is, r1 = positive, r2 = positive, r3 = positive, and M
Both OSFETs have negative temperature characteristics, that is, ΔVth / ΔT =
Under the condition of negative and ΔVTH / ΔT = negative, the above expression is (−positive / negative−negative) / positive, and thus ΔId / ΔT is “positive”. That is, in the circuit of FIG. 2, it can be seen that the current Id can be given a positive temperature characteristic. Therefore, the bias current Ib of the power amplification FET 211 also has a positive temperature characteristic.

In the above description, the MOSFET Q1
Although the change in the current flowing through Q1 due to the temperature characteristic of is not particularly described, the characteristic change of the MOSFET Q1 is woven as the gate-source voltage Vgs1 of the equation (1), so that it is not necessary to establish another equation. It is well demonstrated in the above description that the bias current Ib has a positive temperature characteristic.

Further, since the variation in the element due to the variation in the manufacturing of the semiconductor integrated circuit is larger than that in the MOSFET, in the bias circuit 220 of the embodiment, the variation in the characteristic of the circuit due to the variation in the manufacturing is the variation in the resistance. However, the resistance R3 is an external resistance and has no variation, that is, r3 = constant. Further, from the equation (5) representing the current Id of Q2,
It can be seen that Id is a function of the ratio r1 / r2 of the resistors R1 and R2. Therefore, the bias circuit 22 of the embodiment
With 0, a stable current Id that does not depend on manufacturing variations can flow. In addition, in equation (5), MOSFET Q
Since there is no term for the bias voltage Vbias applied to the drain terminal of No. 4, it can be seen that there is no problem even if a power supply voltage such as a battery whose voltage may change is used as the bias voltage Vbias.

The results obtained by simulating the operation of the bias circuit of the above embodiment and the high frequency power amplifier circuit using the same are shown in FIGS. Of these, FIG. 4 shows the relationship between the input current Icont of the bias circuit and the bias current Ib of the high frequency power amplifier circuit, and FIG. 5 shows the relationship between the temperature and the gain of the high frequency power amplifier circuit. In Fig. 4, ♦ indicates the temperature is -20 ° C and □ indicates the temperature is 2
At 5 ° C., the symbol ▴ plots the relationship between the input current Icont and the bias current Ib when the temperature is 85 ° C. It can be seen from FIG. 4 that if the input current Icont is constant, the bias current Ib increases as the temperature increases. The slope of each curve in FIG. 4 can be appropriately determined by the size ratio of the MOSFETs Q1 to Q4 and the resistance ratio of the resistors R1 and R2 that form the bias circuit. In FIG. 5, the broken line B indicates the input current Icont to the resistor R3.
8 which is directly applied to the MOSFET Q0 via
The relationship between the temperature and the gain of the high frequency power amplifier circuit in the case of using the conventional bias circuit, and the solid line A represents the relationship between the temperature and the gain of the high frequency power amplifier circuit in the case of using the bias circuit of the above embodiment. Show. From FIG. 5, when the conventional bias circuit is used, the temperature rises from -20 ° C to 85 ° C.
When the temperature is changed to ° C, the gain drops from 26.5 dB to 23.5 dB by about 3 dB, but when the bias circuit of the embodiment is used, the gain is 26 even when the temperature changes from -20 ° C to 85 ° C. It can be seen that only 1.4 dB drops from .2 dB to 24.8 dB.

Next, a second embodiment of the bias circuit according to the present invention will be described with reference to FIG. While the input of the bias circuit is the current Icont in the above embodiment, the second embodiment shows an example of the bias circuit in which the constant voltage Vcont is input. The same elements as those constituting the circuit of the first embodiment are designated by the same reference numerals. That is, reference numeral 211
Is a power amplification FET that constitutes a high frequency power amplification circuit, Q0
Is a MOSFET connected in current mirror with the power amplification FET 211, and MOSFET Q0 is a power amplification F
It is simultaneously formed on the same semiconductor chip as the ET211.
That is, the MOSFET Q0 and the power amplification FET 211 have the same structure. In the bias circuit of this embodiment, the current mirror MOSFE is provided between a terminal to which a bias voltage Vbias such as a battery voltage is applied and a ground point.
MOSFET Q11, resistors R3 and M in series with T Q0
OSFETs Q12 and Q13 are connected, and MOSFET
A constant voltage Vcont is applied to the gate terminal of Q11 regardless of the temperature supplied from the APC circuit or the like.
The MOSFETs Q12 and Q13 each have a gate and a drain coupled to each other and operate as a diode. Although not particularly limited, MOSFETs Q11, Q1
2, Q13 are formed on the same semiconductor chip as elements having the same structure, and the resistor R3 is connected as an external element for adjusting the bias current Ib.

The bias circuit of this embodiment is a MOSFE
The threshold voltage of TQ11, Q12, Q13 is Vth, the gate-source voltage is Vgs, the threshold voltage of the power amplification FET 211 is VTH, the gate-source voltage is VGS, and the resistance value of the resistor R3 is r3, R3. Let Idd be the current flowing through the line. Idd = (Vcont-3Vgs-VGS) / r3. When this equation is differentiated by the temperature T, the following equation ΔIdd / ΔT = (Vcont / ΔT−3Vth / ΔT−VTH /
ΔT) / r3 is obtained. From the condition that the constant voltage Vcont is constant irrespective of temperature, the first term of the above equation is 0. Therefore, the above equation is ΔIdd / ΔT = (− 3Vth / ΔT−VTH / ΔT) / r3 ... … (8) Since the threshold voltages of the MOSFETs Q11, Q12, Q13 and the power amplification FET 211 have a negative temperature characteristic, and the resistor R3 has a positive temperature characteristic, the equation (8) has ΔIdd / ΔT = (− negative−negative ) / Positive = (Positive + Positive)
/ Becomes positive, and ΔIdd / ΔT is “positive”, that is, MOSFET
It can be seen that the current Idd flowing through Q0 has a positive temperature characteristic. Therefore, the bias current Ib of the power amplification FET 211, which is current-mirror connected to Q0 and in which the same current as Idd flows, also has a positive temperature characteristic. As a result, even if the temperature rises and the gain of the power amplification EFT211 as an element decreases, the drain current Idd of Q0 increases and the drain current Ib of the power amplification EFT211 also increases, which acts to increase the gain. Therefore, the decrease in gain is prevented.

FIG. 6 shows a configuration example of a mobile phone as an example of a wireless communication system capable of transmitting and receiving by the CDMA system using the high frequency power amplifier circuit and the bias circuit of the above embodiment. In FIG. 6, ANT is an antenna for transmitting and receiving a signal radio wave, 100 is a front end module, 200 is a high frequency power module including the high frequency power amplifier circuit and the bias circuit of the above embodiment, and 300 converts a voice signal into a baseband signal. A baseband circuit that converts a received signal into a voice signal or generates a modulation method switching signal or a band switching signal. 400 down-converts and demodulates the received signal to generate a baseband signal or modulate a transmitted signal. Modulation and demodulation LSI,
CPL is a coupler for detecting the output level of the high frequency power module 200, and APC is for comparing the output level designation signal output from the baseband circuit 300 with the detection signal of the coupler CPL so as to match the output level with the designated level. Power control circuit for generating a high bias current Icont and outputting it to the high frequency power module 200, F
LT is a filter that removes noise and interference waves from the received signal, and LNA is the modulation / demodulation LSI 400 that amplifies the received signal.
It is a low noise amplifier to be passed to.

The baseband circuit 300 is a microprocessor (CPU) or DSP (Digital Signal Processo).
r), a semiconductor memory or other semiconductor integrated circuits. The baseband circuit 300 outputs an output level instruction signal to the automatic power control circuit APC according to the requested transmission level sent from the base station. The front-end module 100 is composed of an impedance matching circuit 121 that is connected to a transmission output terminal of the high frequency power module 200 to perform impedance matching, a low pass filter 122 that attenuates harmonics, a switch circuit 123 for switching between transmission and reception, and the like. , These circuits and elements are mounted on one ceramic substrate to form a module. The switching signal CNT of the switch circuit 123 for switching between transmission and reception is the baseband circuit 300.
Supplied from

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the high-frequency power amplifier circuit of the above-mentioned embodiment, two power amplifier FETs are connected, and the second stage has two FETs 21 arranged in parallel.
2, 213, the second stage may be configured by one FET and then the other stage FET may be connected to form a three-stage configuration, or a configuration of four or more stages. Further, in the above-described embodiment, the power amplification FETs 211 to 213 and the MOSFETs Q0 and Q0 ′ connected to them in a current mirror are configured as one semiconductor integrated circuit, and the MOSFETs Q1 to Q4 and the resistors R1 and R2 that configure the bias circuit are formed. Although it is described that the semiconductor integrated circuit is configured by another semiconductor integrated circuit, these elements, that is, the power amplification FETs 211 to 213 and the bias circuit 220 may be formed on one semiconductor chip to configure as a semiconductor integrated circuit. .

Further, in the above embodiment, the power amplification FET
Has described a high frequency power amplifier circuit for CDMA communication operated in a linear region. For example, in addition to the CDMA system, for example, in data communication, EDGE (Enhanced Data Rate) in which an amplitude shift is further added to a phase shift of GMSK modulation.
Since the power amplification FET of the high frequency power amplification circuit that operates in the s for GMS Evolution) system is also operated in the linear region, it is possible to prevent the gain from decreasing due to the temperature rise by applying the bias circuit of the above-described embodiment. Also, CDM
A system, GSM system having EDGE mode and DCS
In a dual-band or triple-band communication system configured to enable communication by a plurality of communication methods, such as a CDMA system, a bias circuit of a CDMA high-frequency power amplifier circuit and a high-frequency power operating in an EDGE mode of a GSM method or a DCS method. It may be configured to be shared with the bias circuit of the amplifier circuit.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, in a high frequency power amplifier circuit that amplifies and outputs an input high frequency signal by a power amplifier element including a field effect transistor, the temperature fluctuates and the gate-source voltage-drain current of the power amplifier element increases. When the characteristic changes, a bias that compensates for the change is applied by the bias circuit and the bias current is changed, so that the temperature dependence of the gain of the high-frequency power amplifier circuit is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a high frequency power amplifier circuit and a bias circuit according to the present invention.

FIG. 2 is a circuit configuration diagram of the bias circuit in which the positions of elements are changed to explain the operation of the bias circuit in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the bias circuit.

FIG. 4 is a graph showing the relationship between the input current of the bias circuit and the bias current of the high frequency power amplifier circuit in the first embodiment.

FIG. 5 is a graph showing the temperature dependence of the gain of the high frequency power amplifier circuit when the present invention is applied and when it is not applied.

FIG. 6 is a block diagram showing an example of a mobile phone system capable of transmitting and receiving in a CDMA system using the high frequency power amplifier circuit and the bias circuit of the embodiment.

FIG. 7 is a graph showing gate-source voltage-drain current characteristics at high temperature and low temperature of the power amplification FET of the high-frequency power amplification circuit.

FIG. 8 is a circuit configuration diagram showing an example of a bias circuit of a conventional high frequency power amplifier circuit.

[Explanation of symbols]

210 High frequency power amplifier circuit 211-213 power amplification FET 220 bias circuit 230 Operating voltage generator 221 Bias circuit of power amplification FET 211 222 Bias circuit of power amplification FETs 212 and 213

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroyuki Nagamori             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Masayuki Miyoshi             180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Standing Communication System Co., Ltd. F-term (reference) 5J067 AA01 AA04 AA41 CA02 CA22                       CA81 FA10 HA10 HA25 HA29                       HA33 HA39 KA12 KA29 KA42                       KA53 KS01 KS11 LS12 MA22                       SA14 TA01 TA02 TA04                 5J090 AA01 AA04 AA41 CA02 CA22                       CA81 CN04 FN03 FN06 HA10                       HA25 HA29 HA33 HA39 KA12                       KA29 KA42 KA53 MA22 SA14                       TA01 TA02 TA04                 5J500 AA01 AA04 AA41 AC02 AC22                       AC81 AH10 AH25 AH29 AH33                       AH39 AK12 AK29 AK42 AK53                       AM22 AS14 AT01 AT02 AT04                       NC04 NF03 NF06

Claims (9)

[Claims] 1. A high-frequency power amplifier circuit comprising a field effect transistor for amplifying and outputting an input signal, and a bias applied to the gate of the field effect transistor to operate the field effect transistor in a linear region. A wireless communication electronic component including a bias circuit, wherein the bias circuit is configured to generate a bias voltage that compensates for the temperature dependence of the gain and drain current of the field effect transistor. Characteristic electronic components for wireless communication. 2. A high-frequency power amplifier circuit for amplifying and outputting an input high-frequency signal by a power amplification element composed of a field effect transistor, and a power amplification element applied to the gate of the power amplification element to operate the power amplification element in a linear region. A bias circuit for applying such a bias, wherein the bias circuit includes a first MOSFET that is current-mirror connected to the power amplification element, and the bias circuit includes the first MOSFET. An electronic component for wireless communication, which is configured to flow a bias current that compensates for temperature dependence of gain and drain current. 3. The bias circuit comprises the first MOS
A first resistor and a second MOSFET that are connected in series between the drain of the FET and the power supply voltage terminal, and a second resistor that is connected in series between the current input terminal to which the constant current is input and the ground point. Of the second MOSFET, the third resistor, the third MOSFET and the fourth MOSFET, and the fifth MOSFET connected between the gate terminal of the second MOSFET and the ground point.
And T, the gate of the second MOSFET is connected to the current input terminal, the third MOSFET and the fourth MOSFET are diode-connected with their gates and drains coupled, and the fifth MOSFET is included.
The electronic component for wireless communication according to claim 2, wherein a gate is connected to a connection node of the second and third resistors. 4. The gate of the power amplification element and the first
The electronic component for wireless communication according to claim 3, wherein a fourth resistor is connected between the gate of the MOSFET and the gate of the MOSFET. 5. The power amplification element and the first MOS
The FET and the fourth resistor are formed on the first semiconductor chip, the second to fifth MOSFETs, the second resistor and the third resistor are formed on the second semiconductor chip, and The resistor 1 is formed as an individual component, and the individual component, the first semiconductor chip, and the second semiconductor chip are 1
The electronic component for wireless communication according to claim 4, wherein the electronic component is mounted on one insulating substrate. 6. The high-frequency power amplifier circuit is configured in multiple stages by cascade-connecting a plurality of power amplifier elements,
The bias circuit composed of a fifth MOSFET and first to fourth resistors is provided corresponding to each of the power amplifying elements of each stage, and the bias circuit is provided. Wireless communication electronic components. 7. The first bias circuit is connected to the field effect transistor in a current mirror connection.
T, and second and third MOSFEs connected in series between the drain of the first MOSFET and the power supply voltage terminal.
The wireless device according to claim 1, further comprising T, a first resistor, and a fourth MOSFET, wherein a gate of the fourth MOSFET is connected to a voltage input terminal to which a constant voltage is input. Electronic components for communication. 8. A high frequency power amplifier circuit comprising a field effect transistor for amplifying and outputting an input signal, and a bias applied to the gate of the field effect transistor to operate the field effect transistor in a linear region. A semiconductor integrated circuit for communication, comprising a bias circuit and formed on one semiconductor chip, wherein the bias circuit is a bias voltage for compensating the temperature dependence of gain and drain current of the field effect transistor. A semiconductor integrated circuit for communication, characterized in that it is configured to generate. 9. The bias circuit includes a first MOSFE connected to the field effect transistor in a current mirror.
T, a first resistor and a second MO connected in series between the drain of the first MOSFET and the power supply voltage terminal.
An SFET, a second resistor, a third resistor, a third MOSFET and a fourth MOSFET, which are connected in series between a current input terminal to which a constant current is input and a ground point; and the second MOSFET. A fifth MOSFET connected between the gate terminal and a ground point of the second MOSFET, the element other than the first resistor is formed on the one semiconductor chip, and the second MOSFET has a gate A third MOSFET and a fourth MOSFET which are connected to a current input terminal
9. Each of the fifth MOSFETs is a diode connection in which a gate and a drain are coupled to each other, and the fifth MOSFET has a gate connected to a connection node between the second resistor and the third resistor. A semiconductor integrated circuit for communication according to claim 1.