WO2013065401A1 - Power amplifying circuit - Google Patents

Power amplifying circuit Download PDF

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Publication number
WO2013065401A1
WO2013065401A1 PCT/JP2012/073029 JP2012073029W WO2013065401A1 WO 2013065401 A1 WO2013065401 A1 WO 2013065401A1 JP 2012073029 W JP2012073029 W JP 2012073029W WO 2013065401 A1 WO2013065401 A1 WO 2013065401A1
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Prior art keywords
transistor
diode
circuit
source
resistance element
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Application number
PCT/JP2012/073029
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French (fr)
Japanese (ja)
Inventor
慎吾 大石
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シャープ株式会社
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Publication of WO2013065401A1 publication Critical patent/WO2013065401A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/555—A voltage generating circuit being realised for biasing different circuit elements

Definitions

  • the present invention relates to a power amplifier circuit.
  • the present invention relates to a power amplifier circuit including a bias circuit that compensates for temperature characteristics of a power amplifier circuit that amplifies a high-frequency signal used in a wireless communication system such as a mobile phone or a wireless LAN (Local Area Network), and the like.
  • the present invention relates to a provided multistage power amplifier circuit.
  • Transistors used in a power amplifier circuit are roughly classified into a field effect transistor (FET: Field Effect Transistor) and a heterojunction bipolar transistor (HBT: Heterojunction Bipolar Transistor).
  • FET Field Effect Transistor
  • HBT Heterojunction Bipolar Transistor
  • a field effect transistor with low noise in a high frequency region is applied to a low noise amplifier circuit (LNA: Low Noise Amplifier) of a reception system, and a heterojunction bipolar transistor is a power amplifier (PA: Power Amplifier) of a transmission system. It is often applied to.
  • LNA Low Noise Amplifier
  • PA Power Amplifier
  • a low-noise amplifier circuit is provided to amplify a weak high-frequency signal received from an antenna to a power intensity higher than the reception sensitivity of RFIC (Radio-Frequency Integrated Circuit).
  • the power amplifier is provided in front of the antenna in order to amplify the high-frequency signal to a power intensity sufficient to transmit a signal from the RFIC from the antenna to a base station, a terminal, a repeater, or the like according to usage.
  • the power amplifier circuit is required to reduce the gain fluctuation due to the environment.
  • the stability of gain with temperature is important as the performance of the power amplifier circuit.
  • FIG. 8 is a diagram for explaining the gain of the power amplifier circuit when the bias current is constant with respect to temperature.
  • the vertical axis represents the gain of the power amplifier circuit
  • the horizontal axis represents the frequency.
  • the gain of the power amplifier circuit is temperature dependent. The gain decreases greatly as the temperature increases.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2003-234622
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2004-159123
  • the bias circuit includes a temperature detection circuit, a rectification circuit, and a broken line circuit, each including an arithmetic circuit.
  • the bias circuit increases or decreases the bias current according to the ambient temperature, and makes the gain of the power amplifier circuit constant.
  • Patent Document 2 Japanese Patent Laid-Open No. 2004-159123 (Patent Document 2) has a configuration in which the bias circuit includes an arithmetic circuit. According to the techniques described in these documents, there is a problem of an increase in circuit scale.
  • an object of an embodiment of the present invention is to provide a power amplifier circuit having a simple configuration that suppresses the temperature dependence of the gain of the power amplifier circuit and includes a bias circuit having a temperature compensation circuit.
  • a power amplifier circuit includes an amplifying transistor having a drain connected to a high potential and a source grounded, and a current mirror transistor having a source grounded and a gate connected to the gate of the amplifying transistor.
  • a first diode whose anode is connected to the control power supply terminal, and a second diode whose anode is coupled to the cathode of the first diode and whose cathode is connected to the drain of the current mirror transistor
  • a first resistance element having one terminal connected to the cathode of the second diode and the other terminal grounded, and a second resistance element connected in parallel with the second diode.
  • the power amplifier circuit further includes a first transistor having a drain connected to the cathode of the first diode, a source connected to the anode of the second diode, and a gate connected to the cathode of the second diode.
  • the first or second diode includes a diode-connected transistor.
  • a power amplifier circuit includes an amplifying transistor having a drain connected to a high potential and a source grounded, and a current mirror having a source grounded and a gate connected to the gate of the amplifying transistor.
  • a current mirror circuit including a transistor; a first diode having an anode connected to the control power supply terminal; a gate coupled to the cathode of the first diode; and a source coupled to the drain of the current mirror transistor.
  • a transistor, a first resistance element having one terminal connected to the source of the first transistor and the other terminal grounded; a second resistance element connected between the gate and source of the first transistor; And a current source circuit connected between the drain of the amplifying transistor and the drain of the first transistor.
  • the current source circuit includes a second transistor having a drain connected to the drain of the amplifying transistor and a gate connected to the drain of the first transistor, and is connected between the source and the gate of the second transistor. And a third resistance element.
  • it further includes a third transistor having a drain connected to the cathode of the first diode, a source connected to the gate of the first transistor, and a gate connected to the source of the first transistor.
  • each of the first resistance element and the second resistance element includes a plurality of resistance elements connected in series, and the plurality of resistance elements include a resistance element having a resistance temperature coefficient of ⁇ 500 ppm / ° C. or more. And a resistance element having a resistance temperature coefficient of less than ⁇ 500 ppm / ° C.
  • the first diode includes a diode-connected transistor.
  • a power amplifier circuit includes an amplifying transistor having a collector connected to a high potential and an emitter grounded, and a current mirror having an emitter grounded and a base connected to a base of the amplifying transistor.
  • a current mirror circuit including a transistor; a first diode having an anode connected to the control power supply terminal; a second having an anode coupled to the cathode of the first diode and a cathode connected to a collector of the current mirror transistor; A diode; a first resistance element having one terminal connected to the cathode of the second diode and the other terminal grounded; and a second resistance element connected in parallel to the second diode.
  • a power amplifier circuit includes an amplifying transistor having a collector connected to a high potential and an emitter grounded, and a current mirror having an emitter grounded and a base connected to the base of the amplifying transistor.
  • a first mirror having a gate coupled to the cathode of the first diode and a source coupled to the collector of the current mirror transistor; a current mirror circuit including a transistor; a first diode having an anode connected to the control power supply terminal; A transistor, a first resistance element having one terminal connected to the source of the first transistor and the other terminal grounded; a second resistance element connected between the gate and source of the first transistor; And a current source circuit connected between the collector of the amplifying transistor and the drain of the first transistor.
  • the current source circuit has a drain connected to the collector of the amplifying transistor and a gate connected to the drain of the first transistor, and is connected between the source and gate of the second transistor. And a third resistance element.
  • the present invention by having the configuration of the bias circuit including the temperature compensation circuit, the temperature dependence of the gain of the power amplifier circuit can be easily suppressed, and the gain of the power amplifier circuit can be made constant.
  • FIG. 2 is a diagram illustrating an example of a configuration of a power amplifier circuit 100 having a temperature compensation bias circuit according to the first embodiment.
  • FIG. FIG. 10 is a diagram showing an example of a circuit configuration of a power amplifier circuit 100A that is a modification of the first embodiment. It is a figure which shows an example of a circuit structure of the power amplifier circuit 100B which is Embodiment 2.
  • FIG. It is a figure which shows an example of a circuit structure of the power amplifier circuit 100C which is the modification 1 of Embodiment 2.
  • FIG. It is a figure which shows an example of a circuit structure of power amplification circuit 100D which is the modification 2 of Embodiment 2.
  • FIG. 1 is a diagram showing an example of a configuration of a power amplifier circuit 100 having a temperature compensation bias circuit according to the first embodiment.
  • power amplifier circuit 100 includes a current mirror circuit 110 and a current mirror current supply circuit 120.
  • the current mirror circuit 110 includes a current mirror transistor CMTr and an amplifying transistor GTr.
  • the output from the current mirror current supply circuit 120 is supplied to the gate and drain of the current mirror transistor CMTr.
  • a ground potential is supplied to the source of the current mirror transistor CMTr.
  • a ground potential is applied to the source of the amplifying transistor GTr.
  • a high potential VDD is applied to the drain of the amplifying transistor GTr from the VDD power supply terminal P1.
  • the gate of the amplifying transistor GTr receives the output from the current mirror current supply circuit 120.
  • the current mirror current supply circuit 120 includes a diode D1 and a temperature compensation circuit 140.
  • the anode of the diode D1 is connected to the control voltage terminal P2.
  • the temperature compensation circuit 140 includes a diode D2, a resistance element R1, and a resistance element R2.
  • the anode of diode D2 is coupled to the cathode of diode D1.
  • the cathode of the diode D2 is connected to the drain (and gate) of the current mirror transistor CMTr.
  • Resistance element R1 is connected between node N1 and the ground potential.
  • Resistance element R2 is connected in parallel with diode D2 between nodes N1 and N2.
  • the “coupling” described above is not limited to the direct connection of the diode D1 and the diode D2, but includes the case where some circuit element is included between the diode D1 and the diode D2.
  • the two systems are a VDD power supply terminal P1 that supplies a drain voltage to the amplifying transistor GTr and a control voltage terminal P2 that drives the current mirror current supply circuit 120.
  • a circuit including the current mirror current supply circuit 120 and the current mirror transistor CMTr is a circuit that supplies a bias current to the amplifying transistor GTr. For this reason, the above circuit is also referred to as a bias circuit 1.
  • the amplification function is turned on / off by switching the voltage of the control voltage terminal P2.
  • the voltage supplied from the system to turn off the amplification function is not usually 0V, but may be set to a low voltage, for example, 0.4V. Even in such a case, the diode D1 is inserted in series with the control voltage terminal P2 in order to turn off the amplification function.
  • the number of stages of the diode D1 depends on the threshold voltage of the diode D1, and is often one stage, but is not limited thereto.
  • the drain current of the current mirror transistor CMTr is determined by the resistance ratio of the resistance elements R1 and R2.
  • the voltage applied to the resistance element R1 is reduced as compared with the normal temperature, and the drain current of the current mirror transistor CMTr is reduced.
  • the drain current has a positive slope with respect to the temperature, the gain does not decrease too much when the temperature rises, and the gain does not increase too much when the temperature decreases.
  • This slope is determined by the temperature characteristics of the diode.
  • FIG. 2 is a diagram illustrating an example of a circuit configuration of a power amplifier circuit 100A which is a modification of the first embodiment.
  • the power amplifier circuit 100A will be described in comparison with the power amplifier circuit 100 of the first embodiment shown in FIG.
  • power amplification circuit 100 ⁇ / b> A includes the configuration of power amplification circuit 100.
  • the power amplifier circuit 100A includes a current mirror current supply circuit 120A instead of the current mirror current supply circuit 120 of the power amplifier circuit 100.
  • the current mirror current supply circuit 120A further includes a diode D1, a current source circuit 150, a temperature compensation circuit 140, and a transistor Tr1.
  • the anode of the diode D1 is connected to the control voltage terminal P2.
  • the temperature compensation circuit 140 includes a diode D2, a resistance element R1, and a resistance element R2.
  • the anode of the diode D2 is connected to the source of the transistor Tr1.
  • the cathode of the diode D2 is connected to the drain (and gate) of the current mirror transistor CMTr.
  • Resistance element R1 is connected between node N1 and the ground potential.
  • Resistance element R2 is connected in parallel with diode D2 between nodes N1 and N2.
  • the cathode of the diode D1 is connected to the drain of the transistor Tr1.
  • the anode of the diode D2 is connected to the source of the transistor Tr1.
  • the cathode of the diode D2 is connected to the gate of the transistor Tr1.
  • the circuit including the current mirror current supply circuit 120A and the current mirror transistor CMTr is a circuit that supplies a bias current to the amplifying transistor GTr.
  • the above-described circuit is also referred to as a bias circuit 1A.
  • the current source circuit 150 has a configuration in which a resistor element R2 is connected between the gate and source of the transistor Tr1.
  • the diode D2 is connected in parallel with the resistance element R2.
  • FIG. 3 is a diagram illustrating an example of a circuit configuration of the power amplifier circuit 100B according to the second embodiment.
  • the power amplifier circuit 100B will be described in comparison with the power amplifier circuit 100 of FIG.
  • power amplifying circuit 100B includes the configuration of power amplifying circuit 100 according to the first embodiment.
  • the power amplifier circuit 100B includes a current mirror current supply circuit 120B instead of the current mirror current supply circuit 120 of the power amplifier circuit 100.
  • the current mirror current supply circuit 120B includes a diode D1, a current source circuit 130, and a temperature compensation circuit 140A.
  • the anode of the diode D1 is connected to the control voltage terminal P2.
  • the temperature compensation circuit 140A includes a transistor Tr1, a resistance element R1, and a resistance element R2.
  • the gate of transistor Tr1 is coupled to the cathode of diode D1.
  • the source of the transistor Tr1 is connected to the drain of the current mirror transistor CMTr.
  • Resistance element R1 is connected between node N1 and the ground potential.
  • the resistive element R2 is connected between the gate and source of the transistor Tr1.
  • the current source circuit 130 includes a transistor Tr2 and a resistance element R3.
  • the drain of the transistor Tr2 is connected to the VDD power supply terminal P1 that supplies the drain voltage of the amplifying transistor GTr.
  • the gate of the transistor Tr2 is connected to the drain of the transistor Tr1.
  • the resistance element R3 is connected between the source and gate of the transistor Tr2.
  • the circuit including the current mirror current supply circuit 120B and the current mirror transistor CMTr is a circuit that supplies a bias current to the amplifying transistor GTr.
  • the above-described circuit is also referred to as a bias circuit 1B.
  • the drain current of the current mirror transistor CMTr is supplied from the transistor Tr2.
  • the transistor Tr2 is driven by a voltage applied from the VDD power supply terminal P1.
  • a depletion type FET or a high electron mobility transistor (HEMT: High Electron Mobility Transistor) is disposed as the transistor Tr2.
  • HEMT High Electron Mobility Transistor
  • the current value between the source and drain of the transistor Tr2 is determined by the resistance value of the resistance element R3.
  • the transistor Tr2 functions as a current source having no temperature characteristics in the configuration of the current mirror current supply circuit 120B.
  • the current mirror current supply circuit 120B can significantly reduce the control current as compared with the configuration of the current mirror current supply circuit 120 of FIG.
  • the current mirror current supply circuit 120B becomes more advantageous.
  • the transistor Tr2 works as long as a voltage is applied from the VDD power supply terminal P1.
  • the transistor Tr1 is turned off and no current flows through the current mirror transistor CMTr. That is, the transistor Tr1 has both a temperature compensation function for compensating the temperature characteristic of the gate-source current and a switch function. This prevents an increase in circuit.
  • FIG. 4 is a diagram illustrating an example of a circuit configuration of a power amplifier circuit 100C which is a modification of the second embodiment.
  • the power amplifier circuit 100C will be described in comparison with the power amplifier circuit 100B according to the second embodiment shown in FIG.
  • power amplification circuit 100C includes a current mirror current supply circuit 120C instead of current mirror current supply circuit 120B of power amplification circuit 100B.
  • the current mirror current supply circuit 120C further includes a transistor Tr3 in addition to the configuration of the current mirror current supply circuit 120B.
  • the cathode of the diode D1 is coupled to the drain of the transistor Tr3.
  • a resistance element R2 is connected between the source and gate of the transistor Tr3.
  • the circuit composed of the transistor Tr3 and the resistance element R2 has a configuration similar to that of the current source circuit 130. For this reason, the above circuit is also referred to as a current source circuit 150.
  • FIG. 5 is a diagram illustrating an example of a circuit configuration of a power amplifying circuit 100D that is the second modification of the second embodiment.
  • the power amplifier circuit 100D will be described in comparison with the power amplifier circuit 100C of FIG.
  • the power amplifier circuit 100D corresponds to a modification of the modification 1 (power amplification circuit 100C).
  • power amplification circuit 100D includes a current mirror current supply circuit 120D instead of current mirror current supply circuit 120C of power amplification circuit 100C.
  • the current mirror current supply circuit 120D has a configuration of a current mirror current supply circuit 120C.
  • the current mirror current supply circuit 120D includes a temperature compensation circuit 140B instead of the temperature compensation circuit 140A.
  • Temperature compensation circuit 140B includes resistance elements R1A and R2A instead of resistance elements R1 and R2 of temperature compensation circuit 140A, as compared with temperature compensation circuit 140A of FIG.
  • the resistance element R1A includes a resistance element R12 having a large temperature coefficient and a resistance element R11 having a small temperature coefficient.
  • the resistance element R2A includes a resistance element R22 having a large temperature coefficient and a resistance element R21 having a small temperature coefficient.
  • Resistance element R11 and resistance element R12 are connected in series between node N1 and the ground potential.
  • resistance element R21 and resistance element R22 are connected in series between node N2 and node N1.
  • the circuit composed of the transistor Tr3 and the resistance element R2A has the same configuration as the current source circuit 130. Therefore, the above circuit is also referred to as a current source circuit 150A.
  • a resistance element having a large temperature coefficient is a semiconductor resistance element using a semiconductor epitaxial layer according to a semiconductor process
  • a resistance element having a small temperature coefficient is a metal resistance element.
  • the temperature coefficient is determined by the material and cannot be changed freely by the designer.
  • a semiconductor resistance element and a metal resistance are combined.
  • the gradient of the temperature characteristic can be flexibly controlled by changing the effective temperature coefficient according to the ratio of the resistance values.
  • a semiconductor resistance element having a resistance temperature coefficient of 2000 ppm / ° C. and a metal resistance having a resistance temperature coefficient of ⁇ 200 ppm / ° C. are combined.
  • the effective temperature coefficient of resistance can be controlled in the range of ⁇ 200 ppm / ° C. to 2000 ppm / ° C.
  • a plurality of resistance elements (R11, R12, R21, R22) connected in series to each of the resistance element R1A and the resistance element R2A are provided.
  • the plurality of resistance elements are preferably a combination of a resistance element having a resistance temperature coefficient of at least ⁇ 500 ppm / ° C.
  • a resistance element having a temperature coefficient of resistance of ⁇ 500 ppm / ° C. or higher means a resistance element having a resistance temperature coefficient value of 500 ppm / ° C. or higher or ⁇ 500 ppm / ° C. or lower.
  • a resistance element having a resistance temperature coefficient of less than ⁇ 500 ppm / ° C. refers to a resistance element having a resistance temperature coefficient value of less than ⁇ 500 ppm / ° C. to less than +500 ppm / ° C.
  • FIG. 6 is a diagram showing the relationship between the drain current flowing through the current mirror transistor CMTr controlled by the configuration of the power amplifier circuit 100D and the temperature.
  • the vertical axis represents drain current (mA)
  • the horizontal axis represents temperature ( ⁇ 40 ° C. to 100 ° C.).
  • Waveforms W1 and W2 are both waveforms showing simulation results of the power amplifier circuit 100D shown in FIG.
  • the difference in slope between the waveform W1 and the waveform W2 is due to the difference in effective resistance temperature coefficient between the resistance elements R1A and R2A.
  • the drain current of the current mirror transistor CMTr which is the source of the output current of the power amplifier circuit, can be freely controlled.
  • FIG. 7 is a diagram showing the relationship between the gain and temperature of the power amplifier circuit 100D of the present embodiment.
  • the vertical axis represents the gain of the power amplifier circuit
  • the horizontal axis represents the frequency.
  • the current mirror transistor CMTr and the amplifying transistor GTr are described as FETs or HEMTs, but the present invention is limited to this. Instead, they may be replaced with bipolar transistors.
  • the above-described gate, drain, and source correspond to the base, collector, and emitter, respectively.
  • the VDD power supply terminal corresponds to the VCC power supply terminal.
  • the diode includes a diode-connected transistor.
  • the current mirror is configured with the most general connection. However, it is sufficient that the current corresponding to the size ratio of the current mirror transistor CMTr and the amplifying transistor GTr flows in the amplifying transistor, and it goes without saying that the configuration of the current mirror is not limited to that shown in the figure. . Further, although the diode is used as the configuration of each embodiment, the present invention is not limited to this, and a diode-connected transistor may be used.
  • the power amplifier circuit according to the first embodiment and the modification of the first embodiment includes an amplifying transistor GTr whose drain is connected to a high potential and whose source is grounded. Is a power amplifying circuit for controlling the bias current of the amplifying transistor GTr by a current mirror transistor CMTr having a gate connected to the gate of the amplifying transistor GTr, and a diode D1 whose anode is connected to the control voltage terminal P2.
  • a diode D2 having an anode coupled to the cathode of the diode D1, a cathode connected to the drain of the current mirror transistor CMTr, a resistance element R1 having one terminal connected to the cathode of the diode D2 and the other terminal grounded; A resistor element R2 connected in parallel with the diode D2.
  • the drain is connected to the cathode of the diode D1
  • the source is connected to the anode of the diode D2
  • the gate is connected to the cathode of the diode D2, as shown in FIG. Is further provided.
  • the diodes D1 and D2 include diode-connected transistors.
  • the power amplifying circuit according to the second embodiment and its modification includes an amplifying transistor GTr whose drain is connected to a high potential and whose source is grounded, and the source is grounded.
  • the transistor Tr1 coupled to the cathode of the diode D1, the source connected to the drain of the current mirror transistor CMTr, the resistance element R1 having one terminal connected to the source of the transistor Tr1 and the other terminal grounded, and the transistor Tr1 A resistance element R2 connected between the gate and the source;
  • a current source circuit 130 connected between the drains of the transistors Tr1 width transistor GTr.
  • the current source circuit 130 has a drain connected to the drain of the amplifying transistor GTr, a gate connected to the drain of the transistor Tr1, and a source connected to the source and gate of the transistor Tr2. And a resistance element R3.
  • the drain is connected to the cathode of the diode D1
  • the source is connected to the gate of the transistor
  • the gate is connected to the source of the transistor.
  • the transistor Tr3 is further included.
  • the first modification of the second embodiment has a plurality of resistance elements (R11, R12, R21) connected in series to each of the resistance elements R1A and R2A. , R22), and the plurality of resistance elements include a resistance element having a resistance temperature coefficient of at least ⁇ 500 ppm / ° C. and a resistance element having a resistance temperature coefficient of less than ⁇ 500 ppm / ° C.
  • the diode D1 included in the second embodiment and the modification of the second embodiment includes a diode-connected transistor.
  • power amplifying circuit 100E corresponding to the first embodiment using a bipolar transistor includes an amplifying transistor GTr whose collector is connected to a high potential and whose emitter is grounded, and whose emitter is grounded and amplified.
  • a power amplifying circuit that controls a bias current of the amplifying transistor GTr by a current mirror transistor CMTr having a base connected to a base of the transistor for transistor GTr, a diode D1 whose anode is connected to the control voltage terminal P2, and a diode that is a diode
  • the diode D2 is coupled to the cathode of D1, the cathode is connected to the collector of the current mirror transistor CMTr, the resistance element R1 having one terminal connected to the cathode of the diode D2 and the other terminal grounded, and the diode D2. Connected resistance element R2 Equipped with a.
  • power amplifier circuit 100F corresponding to the second embodiment using a bipolar transistor includes an amplifying transistor GTr whose collector is connected to a high potential and whose emitter is grounded, and whose emitter is grounded.
  • a power amplifying circuit that controls the bias current of the amplifying transistor GTr by a current mirror transistor CMTr whose base is connected to the base of the amplifying transistor GTr, and has a diode D1 whose anode is connected to the control voltage terminal P2, and a gate Is coupled to the cathode of the diode D1, the source is connected to the collector of the current mirror transistor CMTr, the transistor Tr1, one terminal connected to the source of the transistor Tr1, and the other terminal grounded, and the transistor Tr1
  • the gate and saw It includes a resistance element R2 connected between, and a current source circuit which is connected between the drain of the collector and the first transistor of the amplifying transistor.
  • this current source circuit includes a transistor Tr2 having a drain connected to the collector of the amplifying transistor GMTr and a gate connected to the drain of the transistor Tr1, and a resistance element R3 connected between the source and gate of the transistor Tr2. Including.
  • 1, 1A-1D bias circuit 100, 100A-100D power amplification circuit, 110 current mirror circuit, 120, 120A-120D current mirror current supply circuit, 130, 150, 150A current source circuit, 140, 140A, 140B temperature compensation circuit , CMTr current mirror transistor, D1, D2 diode, GTr amplification transistor, P1, VDD power supply terminal, P2, control voltage terminal, R1, R2, R1A, R2A, R11, R12, R21, R22 resistance element, Tr1, Tr2, Tr3 transistor .

Abstract

This power amplifying circuit is provided with an amplifying transistor, which has the drain thereof connected at high potential, and the source thereof grounded, and controls a bias current of the amplifying transistor by means of a current mirror transistor (CMTr), which has the source thereof grounded, and the gate thereof connected to the gate of an amplifying transistor (GTr). The power amplifying circuit is provided with: a first diode (D1) having the anode thereof connected to a control power supply terminal; a second diode (D2), which has the anode thereof coupled to the cathode of the first diode (D1), and the cathode thereof connected to the drain of the current mirror transistor (CMTr); a first resistive element (R1) having one terminal connected to the cathode of the second diode (D2), and the other terminal grounded; and a second resistive element (R2), which is connected in parallel to the second diode (D2).

Description

電力増幅回路Power amplifier circuit
　本発明は、電力増幅回路に関する。特に本発明は、携帯電話あるいは無線ＬＡＮ（Ｌｏｃａｌ　Ａｒｅa　Ｎｅｔｗｏｒｋ）等の無線通信システムに使用される高周波信号を増幅する電力増幅回路の温度特性を補償するバイアス回路を備えた電力増幅回路、及びそれを備えた多段電力増幅回路に関する。 The present invention relates to a power amplifier circuit. In particular, the present invention relates to a power amplifier circuit including a bias circuit that compensates for temperature characteristics of a power amplifier circuit that amplifies a high-frequency signal used in a wireless communication system such as a mobile phone or a wireless LAN (Local Area Network), and the like. The present invention relates to a provided multistage power amplifier circuit.
　電力増幅回路に用いられるトランジスタには大別して電界効果トランジスタ（ＦＥＴ：Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）とヘテロ接合バイポーラトランジスタ（ＨＢＴ：Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）がある。 Transistors used in a power amplifier circuit are roughly classified into a field effect transistor (FET: Field Effect Transistor) and a heterojunction bipolar transistor (HBT: Heterojunction Bipolar Transistor).
　具体的には、高周波域でのノイズの小さい電界効果トランジスタが受信系の低雑音増幅回路（ＬＮＡ：Ｌｏｗ　Ｎｏｉｓｅ　Ａｍｐｌｉｆｉｅｒ）に適用され、ヘテロ接合バイポーラトランジスタが送信系のパワーアンプ（ＰＡ：Ｐｏｗｅｒ　Ａｍｐｌｉｆｉｅｒ）に適用されることが多い。 Specifically, a field effect transistor with low noise in a high frequency region is applied to a low noise amplifier circuit (LNA: Low Noise Amplifier) of a reception system, and a heterojunction bipolar transistor is a power amplifier (PA: Power Amplifier) of a transmission system. It is often applied to.
　携帯電話あるいは無線ＬＡＮ等の高周波無線システムにおいて、低雑音増幅回路は、アンテナから受信された微弱な高周波信号をＲＦＩＣ（Ｒａｄｉｏ－Ｆｒｅｑｕｅｎｃｙ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）の受信感度以上の電力強度に増幅するために備えられる。また、パワーアンプは、ＲＦＩＣからの信号をアンテナから基地局、端末、中継器等、用途に応じた距離を伝送するに十分な電力強度に高周波信号を増幅するためにアンテナの前段に備えられる。 In a high-frequency wireless system such as a cellular phone or a wireless LAN, a low-noise amplifier circuit is provided to amplify a weak high-frequency signal received from an antenna to a power intensity higher than the reception sensitivity of RFIC (Radio-Frequency Integrated Circuit). . In addition, the power amplifier is provided in front of the antenna in order to amplify the high-frequency signal to a power intensity sufficient to transmit a signal from the RFIC from the antenna to a base station, a terminal, a repeater, or the like according to usage.
　このような観点から、電力増幅回路には、環境による利得変動を小さくすることが要求される。特に温度による利得の安定性が電力増幅回路の性能として重要となる。 From this point of view, the power amplifier circuit is required to reduce the gain fluctuation due to the environment. In particular, the stability of gain with temperature is important as the performance of the power amplifier circuit.
　たとえば、温度変化にかかわらず一定のバイアス電流を流すバイアス回路の場合、温度の上昇に伴い、電界効果トランジスタにおいては、ｇｍ（相互コンダクタンス＝Ｉｄ／Ｖｇｓ）が減少した際、電力増幅回路の利得が低下する。また、ヘテロ接合バイポーラトランジスタにおいては、β（電流増幅率＝Ｉｃ／Ｉｂ）が減少した際、電力増幅回路の利得が低下する。 For example, in the case of a bias circuit that allows a constant bias current to flow regardless of a temperature change, the gain of the power amplification circuit increases when the gm (mutual conductance = Id / Vgs) decreases in the field effect transistor as the temperature increases. descend. In the heterojunction bipolar transistor, when β (current amplification factor = Ic / Ib) decreases, the gain of the power amplifier circuit decreases.
　この利得の低下を見込んだ上で、システムとして電力増幅回路に要求される利得の最小値を下回らないようにバイアス電流を設定する場合には、室温での消費電流を高めに設定しなければならない。このことは消費電力の増加につながる。 In consideration of this decrease in gain, when setting the bias current so that it does not fall below the minimum gain required for the power amplifier circuit as a system, the current consumption at room temperature must be set higher. . This leads to an increase in power consumption.
　また、高温で利得を減少させないためには、高温でのバイアス電流を常温でのバイアス電流に対し増加させる必要がある。 Also, in order not to decrease the gain at high temperature, it is necessary to increase the bias current at high temperature relative to the bias current at normal temperature.
　図８は、バイアス電流が温度に対して一定の場合の電力増幅回路の利得を説明するための図である。図８を参照して、縦軸に電力増幅回路の利得が示され、横軸に周波数が示される。電力増幅回路の利得は温度依存を示す。高温になるにつれてその利得は大きく減少している。 FIG. 8 is a diagram for explaining the gain of the power amplifier circuit when the bias current is constant with respect to temperature. Referring to FIG. 8, the vertical axis represents the gain of the power amplifier circuit, and the horizontal axis represents the frequency. The gain of the power amplifier circuit is temperature dependent. The gain decreases greatly as the temperature increases.
　電力増幅回路の利得を温度に依存しないようにするための技術として、下記のような技術がある。特開２００３－２３４６２２号公報（特許文献１）や特開２００４－１５９１２３号公報（特許文献２）に示すような手法が提案されている。 There are the following techniques as techniques for making the gain of the power amplifier circuit independent of temperature. Techniques as shown in Japanese Patent Application Laid-Open No. 2003-234622 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2004-159123 (Patent Document 2) have been proposed.
特開２００３－２３４６２２号公報JP 2003-234622 A 特開２００４－１５９１２３号公報JP 2004-159123 A
　特開２００３－２３４６２２号公報（特許文献１）では、バイアス回路は、演算回路から成る、温度検知回路、整流回路、折れ線回路を有する。バイアス回路は、周囲温度に応じてバイアス電流を増減して、電力増幅回路の利得を一定としている。特開２００４－１５９１２３号公報（特許文献２）も同様に、バイアス回路は演算回路を有した構成になっている。これらの文献に記載された技術によれば、回路規模の増大という課題があった。 In Japanese Patent Application Laid-Open No. 2003-234622 (Patent Document 1), the bias circuit includes a temperature detection circuit, a rectification circuit, and a broken line circuit, each including an arithmetic circuit. The bias circuit increases or decreases the bias current according to the ambient temperature, and makes the gain of the power amplifier circuit constant. Similarly, Japanese Patent Laid-Open No. 2004-159123 (Patent Document 2) has a configuration in which the bias circuit includes an arithmetic circuit. According to the techniques described in these documents, there is a problem of an increase in circuit scale.
　そこで、本発明の一実施例の目的は、電力増幅回路の利得の温度依存性を抑制し、温度補償回路を有するバイアス回路を備えた電力増幅回路を、簡素な構成で提供することである。 Therefore, an object of an embodiment of the present invention is to provide a power amplifier circuit having a simple configuration that suppresses the temperature dependence of the gain of the power amplifier circuit and includes a bias circuit having a temperature compensation circuit.
　本発明のある局面によれば、電力増幅回路は、ドレインが高電位に接続され、ソースが接地された増幅用トランジスタと、ソースが接地され増幅用トランジスタのゲートにゲートが接続されたカレントミラートランジスタとを含むカレントミラー回路と、アノードが制御電源端子に接続された第１のダイオードと、アノードが第１のダイオードのカソードに結合され、カソードがカレントミラートランジスタのドレインに接続された第２のダイオードと、一方の端子が第２のダイオードのカソードに接続され他方の端子が接地された第１の抵抗素子と、第２のダイオードと並列接続された第２の抵抗素子とを備える。 According to an aspect of the present invention, a power amplifier circuit includes an amplifying transistor having a drain connected to a high potential and a source grounded, and a current mirror transistor having a source grounded and a gate connected to the gate of the amplifying transistor. A first diode whose anode is connected to the control power supply terminal, and a second diode whose anode is coupled to the cathode of the first diode and whose cathode is connected to the drain of the current mirror transistor And a first resistance element having one terminal connected to the cathode of the second diode and the other terminal grounded, and a second resistance element connected in parallel with the second diode.
　好ましくは、電力増幅回路は、第１のダイオードのカソードにドレインが接続され、第２のダイオードのアノードにソースが接続され、第２のダイオードのカソードにゲートが接続された第１のトランジスタをさらに備える。 Preferably, the power amplifier circuit further includes a first transistor having a drain connected to the cathode of the first diode, a source connected to the anode of the second diode, and a gate connected to the cathode of the second diode. Prepare.
　さらに好ましくは、第１または第２のダイオードは、ダイオード接続されたトランジスタを含む。 More preferably, the first or second diode includes a diode-connected transistor.
　本発明の別の局面からみれば、電力増幅回路は、ドレインが高電位に接続され、ソースが接地された増幅用トランジスタと、ソースが接地され増幅用トランジスタのゲートにゲートが接続されたカレントミラートランジスタとを含むカレントミラー回路と、アノードが制御電源端子に接続された第１のダイオードと、ゲートが第１のダイオードのカソードに結合され、ソースがカレントミラートランジスタのドレインに接続された第１のトランジスタと、一方の端子が第１のトランジスタのソースに接続され他の端子が接地された第１の抵抗素子と、第１のトランジスタのゲートとソースの間に接続された第２の抵抗素子と、増幅用トランジスタのドレインと第１のトランジスタのドレインとの間に接続される電流源回路とを備える。 According to another aspect of the present invention, a power amplifier circuit includes an amplifying transistor having a drain connected to a high potential and a source grounded, and a current mirror having a source grounded and a gate connected to the gate of the amplifying transistor. A current mirror circuit including a transistor; a first diode having an anode connected to the control power supply terminal; a gate coupled to the cathode of the first diode; and a source coupled to the drain of the current mirror transistor. A transistor, a first resistance element having one terminal connected to the source of the first transistor and the other terminal grounded; a second resistance element connected between the gate and source of the first transistor; And a current source circuit connected between the drain of the amplifying transistor and the drain of the first transistor.
　好ましくは、電流源回路は、ドレインが増幅用トランジスタのドレインに接続され、ゲートが第１のトランジスタのドレインに接続された第２のトランジスタと、第２のトランジスタのソースとゲートとの間に接続された第３の抵抗素子とを含む。 Preferably, the current source circuit includes a second transistor having a drain connected to the drain of the amplifying transistor and a gate connected to the drain of the first transistor, and is connected between the source and the gate of the second transistor. And a third resistance element.
　さらに好ましくは、第１のダイオードのカソードにドレインが接続され、第１のトランジスタのゲートにソースが接続され、第１のトランジスタのソースにゲートが接続された第３のトランジスタをさらに含む。 More preferably, it further includes a third transistor having a drain connected to the cathode of the first diode, a source connected to the gate of the first transistor, and a gate connected to the source of the first transistor.
　さらに好ましくは、第１の抵抗素子と第２の抵抗素子の各々は、直列接続された複数の抵抗素子を含み、複数の抵抗素子は、±５００ｐｐｍ／℃以上の抵抗温度係数を有する抵抗素子と、±５００ｐｐｍ／℃未満の抵抗温度係数を有する抵抗素子とを含む。 More preferably, each of the first resistance element and the second resistance element includes a plurality of resistance elements connected in series, and the plurality of resistance elements include a resistance element having a resistance temperature coefficient of ± 500 ppm / ° C. or more. And a resistance element having a resistance temperature coefficient of less than ± 500 ppm / ° C.
　好ましくは、第１のダイオードはダイオード接続されたトランジスタを含む。
　本発明の別の局面からみれば、電力増幅回路は、コレクタが高電位に接続され、エミッタが接地された増幅用トランジスと、エミッタが接地され増幅用トランジスタのベースにベースが接続されたカレントミラートランジスタとを含むカレントミラー回路と、アノードが制御電源端子に接続された第１のダイオードと、アノードが第１のダイオードのカソードに結合され、カソードがカレントミラートランジスタのコレクタに接続された第２のダイオードと、一方の端子が第２のダイオードのカソードに接続され他方の端子が接地された第１の抵抗素子と、第２のダイオードと並列接続された第２の抵抗素子とを備える。 Preferably, the first diode includes a diode-connected transistor.
According to another aspect of the present invention, a power amplifier circuit includes an amplifying transistor having a collector connected to a high potential and an emitter grounded, and a current mirror having an emitter grounded and a base connected to a base of the amplifying transistor. A current mirror circuit including a transistor; a first diode having an anode connected to the control power supply terminal; a second having an anode coupled to the cathode of the first diode and a cathode connected to a collector of the current mirror transistor; A diode; a first resistance element having one terminal connected to the cathode of the second diode and the other terminal grounded; and a second resistance element connected in parallel to the second diode.
　本発明の別の局面からみれば、電力増幅回路は、コレクタが高電位に接続され、エミッタが接地された増幅用トランジスタと、エミッタが接地され増幅用トランジスタのベースにベースが接続されたカレントミラートランジスタとを含むカレントミラー回路と、アノードが制御電源端子に接続された第１のダイオードと、ゲートが第１のダイオードのカソードに結合され、ソースがカレントミラートランジスタのコレクタに接続された第１のトランジスタと、一方の端子が第１のトランジスタのソースに接続され他の端子が接地された第１の抵抗素子と、第１のトランジスタのゲートとソースの間に接続された第２の抵抗素子と、増幅用トランジスタのコレクタと第１のトランジスタのドレインとの間に接続される電流源回路とを備える。 According to another aspect of the present invention, a power amplifier circuit includes an amplifying transistor having a collector connected to a high potential and an emitter grounded, and a current mirror having an emitter grounded and a base connected to the base of the amplifying transistor. A first mirror having a gate coupled to the cathode of the first diode and a source coupled to the collector of the current mirror transistor; a current mirror circuit including a transistor; a first diode having an anode connected to the control power supply terminal; A transistor, a first resistance element having one terminal connected to the source of the first transistor and the other terminal grounded; a second resistance element connected between the gate and source of the first transistor; And a current source circuit connected between the collector of the amplifying transistor and the drain of the first transistor.
　好ましくは、電流源回路は、ドレインが増幅用トランジスタのコレクタに接続され、ゲートが第１のトランジスタのドレインに接続された第２のトランジスタと、第２のトランジスタのソースとゲートとの間に接続された第３の抵抗素子とを含む。 Preferably, the current source circuit has a drain connected to the collector of the amplifying transistor and a gate connected to the drain of the first transistor, and is connected between the source and gate of the second transistor. And a third resistance element.
　本発明によれば、温度補償回路を備えるバイアス回路の構成を有することにより、容易に電力増幅回路の利得の温度依存性を抑制し、電力増幅回路の利得を一定にできる。 According to the present invention, by having the configuration of the bias circuit including the temperature compensation circuit, the temperature dependence of the gain of the power amplifier circuit can be easily suppressed, and the gain of the power amplifier circuit can be made constant.
本実施の形態１の温度補償バイアス回路を持つ電力増幅回路１００の構成の一例を示す図である。2 is a diagram illustrating an example of a configuration of a power amplifier circuit 100 having a temperature compensation bias circuit according to the first embodiment. FIG. 実施の形態１の変形例である電力増幅回路１００Ａの回路の構成の一例を示す図である。FIG. 10 is a diagram showing an example of a circuit configuration of a power amplifier circuit 100A that is a modification of the first embodiment. 実施の形態２である電力増幅回路１００Ｂの回路の構成の一例を示す図である。It is a figure which shows an example of a circuit structure of the power amplifier circuit 100B which is Embodiment 2. FIG. 実施の形態２の変形例１である電力増幅回路１００Ｃの回路の構成の一例を示す図である。It is a figure which shows an example of a circuit structure of the power amplifier circuit 100C which is the modification 1 of Embodiment 2. FIG. 実施の形態２の変形例２である電力増幅回路１００Ｄの回路の構成の一例を示す図である。It is a figure which shows an example of a circuit structure of power amplification circuit 100D which is the modification 2 of Embodiment 2. FIG. 電力増幅回路１００Ｄの構成により制御したカレントミラートランジスタＣＭＴｒに流れるドレイン電流と温度との関係を示す図である。It is a figure which shows the relationship between the drain current which flows into the current mirror transistor CMTr controlled by the structure of power amplifier circuit 100D, and temperature. 本実施の形態の電力増幅回路１００Ｄの利得と温度との関係を示す図である。It is a figure which shows the relationship between the gain of power amplifier circuit 100D of this Embodiment, and temperature. バイアス電流が温度に対して一定の場合の電力増幅回路の利得を説明するための図である。It is a figure for demonstrating the gain of a power amplifier circuit in case a bias current is constant with respect to temperature. バイポーラトランジスタを用いた電力増幅回路１００Ｅの回路の構成の一例を示す図である。It is a figure which shows an example of a circuit structure of the power amplifier circuit 100E using a bipolar transistor. バイポーラトランジスタを用いた電力増幅回路１００Ｆの回路の構成の一例を示す図である。It is a figure which shows an example of a circuit structure of the power amplifier circuit 100F using a bipolar transistor.
　以下、本発明について図面を参照して詳しく説明する。なお、図中同一又は相当部分には同一の符号を付してその説明は繰返さない。以下、本発明の実施の形態を図面を用いて説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　［実施の形態１］
　図１は本実施の形態１の温度補償バイアス回路を持つ電力増幅回路１００の構成の一例を示す図である。 [Embodiment 1]
FIG. 1 is a diagram showing an example of a configuration of a power amplifier circuit 100 having a temperature compensation bias circuit according to the first embodiment.
　図１を参照して、電力増幅回路１００は、カレントミラー回路１１０と、カレントミラー電流供給回路１２０とを含む。 Referring to FIG. 1, power amplifier circuit 100 includes a current mirror circuit 110 and a current mirror current supply circuit 120.
　カレントミラー回路１１０は、カレントミラートランジスタＣＭＴｒと、増幅用トランジスタＧＴｒとを含む。カレントミラー電流供給回路１２０からの出力が、カレントミラートランジスタＣＭＴｒのゲートとドレインとに供給される。カレントミラートランジスタＣＭＴｒのソースに接地電位が供給される。増幅用トランジスタＧＴｒのソースに接地電位が与えられる。増幅用トランジスタＧＴｒのドレインにＶＤＤ電源端子Ｐ１から高電位のＶＤＤが与えられる。増幅用トランジスタＧＴｒのゲートは、カレントミラー電流供給回路１２０からの出力を受ける。 The current mirror circuit 110 includes a current mirror transistor CMTr and an amplifying transistor GTr. The output from the current mirror current supply circuit 120 is supplied to the gate and drain of the current mirror transistor CMTr. A ground potential is supplied to the source of the current mirror transistor CMTr. A ground potential is applied to the source of the amplifying transistor GTr. A high potential VDD is applied to the drain of the amplifying transistor GTr from the VDD power supply terminal P1. The gate of the amplifying transistor GTr receives the output from the current mirror current supply circuit 120.
　カレントミラー電流供給回路１２０は、ダイオードＤ１と、温度補償回路１４０とを含む。ダイオードＤ１のアノードが制御電圧端子Ｐ２に接続される。 The current mirror current supply circuit 120 includes a diode D1 and a temperature compensation circuit 140. The anode of the diode D1 is connected to the control voltage terminal P2.
　温度補償回路１４０は、ダイオードＤ２と、抵抗素子Ｒ１と、抵抗素子Ｒ２とを含む。ダイオードＤ２のアノードがダイオードＤ１のカソードに結合される。ダイオードＤ２のカソードが、カレントミラートランジスタＣＭＴｒのドレイン（およびゲート）に接続される。抵抗素子Ｒ１は、ノードＮ１と接地電位との間に接続される。抵抗素子Ｒ２は、ノードＮ１とノードＮ２との間にダイオードＤ２と並列接続される。なお、上述した「結合」とは、ダイオードＤ１とダイオードＤ２とが直接接続されることだけに限定されず、ダイオードＤ１とダイオードＤ２との間に何らかの回路素子が含まれている場合も含む。 The temperature compensation circuit 140 includes a diode D2, a resistance element R1, and a resistance element R2. The anode of diode D2 is coupled to the cathode of diode D1. The cathode of the diode D2 is connected to the drain (and gate) of the current mirror transistor CMTr. Resistance element R1 is connected between node N1 and the ground potential. Resistance element R2 is connected in parallel with diode D2 between nodes N1 and N2. The “coupling” described above is not limited to the direct connection of the diode D1 and the diode D2, but includes the case where some circuit element is included between the diode D1 and the diode D2.
　電源が供給される系統は２系統である。２つの系統は、増幅用トランジスタＧＴｒにドレイン電圧を与えるＶＤＤ電源端子Ｐ１と、カレントミラー電流供給回路１２０を駆動させる制御電圧端子Ｐ２とである。 * There are two systems to which power is supplied. The two systems are a VDD power supply terminal P1 that supplies a drain voltage to the amplifying transistor GTr and a control voltage terminal P2 that drives the current mirror current supply circuit 120.
　なお、カレントミラー電流供給回路１２０とカレントミラートランジスタＣＭＴｒとを合わせた回路は、増幅用トランジスタＧＴｒへのバイアス電流を供給する回路である。このため、上記の回路は、バイアス回路１とも称される。 Note that a circuit including the current mirror current supply circuit 120 and the current mirror transistor CMTr is a circuit that supplies a bias current to the amplifying transistor GTr. For this reason, the above circuit is also referred to as a bias circuit 1.
　増幅機能のオン／オフは制御電圧端子Ｐ２の電圧の切替によってなされる。システムから供給される、増幅機能をオフとすべき電圧は、通常０Ｖでなく、例えば０．４Ｖと低電圧に設定されている場合がある。このような場合においても増幅機能をオフとするために、ダイオードＤ１が制御電圧端子Ｐ２に直列に挿入されている。 The amplification function is turned on / off by switching the voltage of the control voltage terminal P2. The voltage supplied from the system to turn off the amplification function is not usually 0V, but may be set to a low voltage, for example, 0.4V. Even in such a case, the diode D1 is inserted in series with the control voltage terminal P2 in order to turn off the amplification function.
　ダイオードＤ１の段数はダイオードＤ１の持つ閾値電圧に拠り、１段の場合が多いがこれに限られることは無い。カレントミラートランジスタＣＭＴｒのドレイン電流は抵抗素子Ｒ１とＲ２の抵抗比によって決まる。 The number of stages of the diode D1 depends on the threshold voltage of the diode D1, and is often one stage, but is not limited thereto. The drain current of the current mirror transistor CMTr is determined by the resistance ratio of the resistance elements R1 and R2.
　具体的には温度が上昇したとき、ダイオードＤ１の電圧降下分が減少する。抵抗素子Ｒ２と並列に接続されているダイオードＤ２の温度特性により並列合成抵抗が減少する。その結果、抵抗素子Ｒ１にかかる電圧が増加し、カレントミラートランジスタＣＭＴｒのドレイン電流が増加する。 Specifically, when the temperature rises, the voltage drop of the diode D1 decreases. The parallel combined resistance decreases due to the temperature characteristics of the diode D2 connected in parallel with the resistor element R2. As a result, the voltage applied to the resistance element R1 increases and the drain current of the current mirror transistor CMTr increases.
　逆に温度が低下した場合は、抵抗素子Ｒ１にかかる電圧が常温に比べ減少し、カレントミラートランジスタＣＭＴｒのドレイン電流が減少する。このようにドレイン電流が温度に対し正の傾きを持つので、温度上昇時に利得が落ちすぎず、温度低下時に利得が上がり過ぎない。 Conversely, when the temperature is lowered, the voltage applied to the resistance element R1 is reduced as compared with the normal temperature, and the drain current of the current mirror transistor CMTr is reduced. Thus, since the drain current has a positive slope with respect to the temperature, the gain does not decrease too much when the temperature rises, and the gain does not increase too much when the temperature decreases.
　この傾きはダイオードの温度特性により決まる。抵抗素子Ｒ１、Ｒ２を比較的大きな温度係数を持つ抵抗素子とすることで、常温のドレイン電流を変えずに、傾きだけを微調整することができる。 This slope is determined by the temperature characteristics of the diode. By making the resistance elements R1 and R2 resistance elements having a relatively large temperature coefficient, only the slope can be finely adjusted without changing the drain current at room temperature.
　例えば、抵抗素子Ｒ１に正の温度係数を持つ抵抗素子を適用すると、傾きが増す。抵抗素子Ｒ１に負の温度係数を持つ抵抗素子を適用すると、傾きが緩やかになる。温度係数を持つ抵抗素子を抵抗素子Ｒ２に適用する場合は、上記の正負の関係を逆にすることで同様の効果を得る。 For example, when a resistance element having a positive temperature coefficient is applied to the resistance element R1, the inclination increases. When a resistance element having a negative temperature coefficient is applied to the resistance element R1, the inclination becomes gentle. When a resistance element having a temperature coefficient is applied to the resistance element R2, the same effect can be obtained by reversing the positive / negative relationship.
　［実施の形態１の変形例］
　図２は、実施の形態１の変形例である電力増幅回路１００Ａの回路の構成の一例を示す図である。図１の実施の形態１の電力増幅回路１００と比較しつつ、電力増幅回路１００Ａについて説明する。図２を参照して、電力増幅回路１００Ａは、電力増幅回路１００の構成を備える。加えて、電力増幅回路１００Ａは、電力増幅回路１００のカレントミラー電流供給回路１２０に代えて、カレントミラー電流供給回路１２０Ａを含む。 [Modification of Embodiment 1]
FIG. 2 is a diagram illustrating an example of a circuit configuration of a power amplifier circuit 100A which is a modification of the first embodiment. The power amplifier circuit 100A will be described in comparison with the power amplifier circuit 100 of the first embodiment shown in FIG. Referring to FIG. 2, power amplification circuit 100 </ b> A includes the configuration of power amplification circuit 100. In addition, the power amplifier circuit 100A includes a current mirror current supply circuit 120A instead of the current mirror current supply circuit 120 of the power amplifier circuit 100.
　カレントミラー電流供給回路１２０Ａは、ダイオードＤ１と、電流源回路１５０と、温度補償回路１４０と、トランジスタＴｒ１とをさらに含む。ダイオードＤ１のアノードは、制御電圧端子Ｐ２に接続される。 The current mirror current supply circuit 120A further includes a diode D1, a current source circuit 150, a temperature compensation circuit 140, and a transistor Tr1. The anode of the diode D1 is connected to the control voltage terminal P2.
　温度補償回路１４０は、ダイオードＤ２と、抵抗素子Ｒ１と、抵抗素子Ｒ２とを含む。ダイオードＤ２のアノードがトランジスタＴｒ１のソースに接続される。ダイオードＤ２のカソードがカレントミラートランジスタＣＭＴｒのドレイン（およびゲート）に接続される。抵抗素子Ｒ１は、ノードＮ１と接地電位との間に接続される。抵抗素子Ｒ２は、ノードＮ１とノードＮ２との間にダイオードＤ２と並列接続される。 The temperature compensation circuit 140 includes a diode D2, a resistance element R1, and a resistance element R2. The anode of the diode D2 is connected to the source of the transistor Tr1. The cathode of the diode D2 is connected to the drain (and gate) of the current mirror transistor CMTr. Resistance element R1 is connected between node N1 and the ground potential. Resistance element R2 is connected in parallel with diode D2 between nodes N1 and N2.
　トランジスタＴｒ１のドレインにダイオードＤ１のカソードが接続される。トランジスタＴｒ１のソースにダイオードＤ２のアノードが接続される。トランジスタＴｒ１のゲートにダイオードＤ２のカソードが接続される。 The cathode of the diode D1 is connected to the drain of the transistor Tr1. The anode of the diode D2 is connected to the source of the transistor Tr1. The cathode of the diode D2 is connected to the gate of the transistor Tr1.
　実施の形態１のバイアス回路１と同様に、カレントミラー電流供給回路１２０ＡとカレントミラートランジスタＣＭＴｒとを合わせた回路は、増幅用トランジスタＧＴｒへのバイアス電流を供給する回路である。このため、上述の回路は、バイアス回路１Ａとも称される。 Similarly to the bias circuit 1 of the first embodiment, the circuit including the current mirror current supply circuit 120A and the current mirror transistor CMTr is a circuit that supplies a bias current to the amplifying transistor GTr. For this reason, the above-described circuit is also referred to as a bias circuit 1A.
　電流源回路１５０は、トランジスタＴｒ１のゲートとソースの間に抵抗素子Ｒ２が接続された構成を備える。ダイオードＤ２は抵抗素子Ｒ２と並列に接続されている。電流源が適用されることで、抵抗素子Ｒ１にかかる電圧の制御電圧依存性が著しく改善される。制御電圧の増減分のほとんどが、トランジスタＴｒ１のドレイン－ソース間電圧の増減として吸収される。 The current source circuit 150 has a configuration in which a resistor element R2 is connected between the gate and source of the transistor Tr1. The diode D2 is connected in parallel with the resistance element R2. By applying the current source, the control voltage dependency of the voltage applied to the resistance element R1 is significantly improved. Most of the increase / decrease in the control voltage is absorbed as the increase / decrease in the drain-source voltage of the transistor Tr1.
　なお、電力増幅回路１００Ａの他の構成については、電力増幅回路１００と同様なため、説明はここでは繰返さない。 Since the other configuration of power amplifier circuit 100A is the same as that of power amplifier circuit 100, description thereof will not be repeated here.
　［実施の形態２］
　図３は、実施の形態２である電力増幅回路１００Ｂの回路の構成の一例を示す図である。図１の電力増幅回路１００と比較しつつ、電力増幅回路１００Ｂについて説明する。図３を参照して、電力増幅回路１００Ｂは、実施の形態１である電力増幅回路１００の構成を備える。加えて、電力増幅回路１００Ｂは、電力増幅回路１００のカレントミラー電流供給回路１２０に代えてカレントミラー電流供給回路１２０Ｂを含む。 [Embodiment 2]
FIG. 3 is a diagram illustrating an example of a circuit configuration of the power amplifier circuit 100B according to the second embodiment. The power amplifier circuit 100B will be described in comparison with the power amplifier circuit 100 of FIG. Referring to FIG. 3, power amplifying circuit 100B includes the configuration of power amplifying circuit 100 according to the first embodiment. In addition, the power amplifier circuit 100B includes a current mirror current supply circuit 120B instead of the current mirror current supply circuit 120 of the power amplifier circuit 100.
　カレントミラー電流供給回路１２０Ｂは、ダイオードＤ１と、電流源回路１３０と、温度補償回路１４０Ａとを含む。ダイオードＤ１のアノードは、制御電圧端子Ｐ２に接続される。 The current mirror current supply circuit 120B includes a diode D1, a current source circuit 130, and a temperature compensation circuit 140A. The anode of the diode D1 is connected to the control voltage terminal P2.
　温度補償回路１４０Ａは、トランジスタＴｒ１と、抵抗素子Ｒ１と、抵抗素子Ｒ２とを含む。トランジスタＴｒ１のゲートがダイオードＤ１のカソードに結合される。トランジスタＴｒ１のソースがカレントミラートランジスタＣＭＴｒのドレインに接続される。抵抗素子Ｒ１は、ノードＮ１と接地電位との間に接続される。抵抗素子Ｒ２は、トランジスタＴｒ１のゲートとソースの間に接続される。 The temperature compensation circuit 140A includes a transistor Tr1, a resistance element R1, and a resistance element R2. The gate of transistor Tr1 is coupled to the cathode of diode D1. The source of the transistor Tr1 is connected to the drain of the current mirror transistor CMTr. Resistance element R1 is connected between node N1 and the ground potential. The resistive element R2 is connected between the gate and source of the transistor Tr1.
　電流源回路１３０は、トランジスタＴｒ２と、抵抗素子Ｒ３とを含む。トランジスタＴｒ２のドレインが、増幅用トランジスタＧＴｒのドレイン電圧を供給するＶＤＤ電源端子Ｐ１に接続される。トランジスタＴｒ２のゲートが、トランジスタＴｒ１のドレインに接続される。抵抗素子Ｒ３は、トランジスタＴｒ２のソースとゲートの間に接続される。 The current source circuit 130 includes a transistor Tr2 and a resistance element R3. The drain of the transistor Tr2 is connected to the VDD power supply terminal P1 that supplies the drain voltage of the amplifying transistor GTr. The gate of the transistor Tr2 is connected to the drain of the transistor Tr1. The resistance element R3 is connected between the source and gate of the transistor Tr2.
　実施の形態１のバイアス回路１と同様に、カレントミラー電流供給回路１２０ＢとカレントミラートランジスタＣＭＴｒとを合わせた回路は、増幅用トランジスタＧＴｒへのバイアス電流を供給する回路である。このため、上述の回路は、バイアス回路１Ｂとも称される。 Similarly to the bias circuit 1 of the first embodiment, the circuit including the current mirror current supply circuit 120B and the current mirror transistor CMTr is a circuit that supplies a bias current to the amplifying transistor GTr. For this reason, the above-described circuit is also referred to as a bias circuit 1B.
　カレントミラートランジスタＣＭＴｒのドレイン電流は、トランジスタＴｒ２から供給される。トランジスタＴｒ２は、ＶＤＤ電源端子Ｐ１から印加される電圧によって駆動される。 The drain current of the current mirror transistor CMTr is supplied from the transistor Tr2. The transistor Tr2 is driven by a voltage applied from the VDD power supply terminal P1.
　たとえばトランジスタＴｒ２としてディプレッション型のＦＥＴもしくは高電子移動度トランジスタ（ＨＥＭＴ：Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）が配置される。 For example, a depletion type FET or a high electron mobility transistor (HEMT: High Electron Mobility Transistor) is disposed as the transistor Tr2.
　このトランジスタＴｒ２のソース－ドレイン間の電流値は、抵抗素子Ｒ３の抵抗値によって定められる。トランジスタＴｒ２は、カレントミラー電流供給回路１２０Ｂの構成においては温度特性の無い電流源として働く。 The current value between the source and drain of the transistor Tr2 is determined by the resistance value of the resistance element R3. The transistor Tr2 functions as a current source having no temperature characteristics in the configuration of the current mirror current supply circuit 120B.
　このような構成を取ることにより、電力増幅回路１００Ｂを駆動させるための大部分の電流は電流源回路１３０（具体的にはトランジスタＴｒ２）から供給される。カレントミラー電流供給回路１２０Ｂの温度特性は、トランジスタＴｒ２および抵抗素子Ｒ３以外の素子である、ダイオードＤ１、抵抗素子Ｒ１、Ｒ２、トランジスタＴｒ１により制御される。このため図１のカレントミラー電流供給回路１２０の構成に比べカレントミラー電流供給回路１２０Ｂは制御電流を大幅に減少することができる。ベースバンドＩＣから供給できる電流の上限が低めに設定されている場合に、カレントミラー電流供給回路１２０Ｂは、より有利になる。 With such a configuration, most of the current for driving the power amplifier circuit 100B is supplied from the current source circuit 130 (specifically, the transistor Tr2). The temperature characteristics of the current mirror current supply circuit 120B are controlled by a diode D1, resistance elements R1, R2, and a transistor Tr1, which are elements other than the transistor Tr2 and the resistance element R3. Therefore, the current mirror current supply circuit 120B can significantly reduce the control current as compared with the configuration of the current mirror current supply circuit 120 of FIG. When the upper limit of the current that can be supplied from the baseband IC is set lower, the current mirror current supply circuit 120B becomes more advantageous.
　トランジスタＴｒ２はＶＤＤ電源端子Ｐ１から電圧が印加されている限り働く。制御電圧端子Ｐ２にオフの電圧値が印加された時、トランジスタＴｒ１がオフし、カレントミラートランジスタＣＭＴｒに電流が流れなくなる。つまり、トランジスタＴｒ１はゲート－ソース電流の温度特性を補償する温度補償機能と、スイッチの機能を兼ねている。これにより、回路の増大を防いでいる。 The transistor Tr2 works as long as a voltage is applied from the VDD power supply terminal P1. When an off voltage value is applied to the control voltage terminal P2, the transistor Tr1 is turned off and no current flows through the current mirror transistor CMTr. That is, the transistor Tr1 has both a temperature compensation function for compensating the temperature characteristic of the gate-source current and a switch function. This prevents an increase in circuit.
　なお、電力増幅回路１００Ｂの他の構成については、電力増幅回路１００と同様なため、説明はここでは繰返さない。 Since the other configuration of power amplifier circuit 100B is the same as that of power amplifier circuit 100, description thereof will not be repeated here.
　［実施の形態２の変形例１］
　図４は、実施の形態２の変形例である電力増幅回路１００Ｃの回路の構成の一例を示す図である。図３の実施の形態２である電力増幅回路１００Ｂと比較しつつ、電力増幅回路１００Ｃについて説明する。図４を参照して、電力増幅回路１００Ｃは、電力増幅回路１００Ｂのカレントミラー電流供給回路１２０Ｂに代えて、カレントミラー電流供給回路１２０Ｃを含む。 [Modification 1 of Embodiment 2]
FIG. 4 is a diagram illustrating an example of a circuit configuration of a power amplifier circuit 100C which is a modification of the second embodiment. The power amplifier circuit 100C will be described in comparison with the power amplifier circuit 100B according to the second embodiment shown in FIG. Referring to FIG. 4, power amplification circuit 100C includes a current mirror current supply circuit 120C instead of current mirror current supply circuit 120B of power amplification circuit 100B.
　カレントミラー電流供給回路１２０Ｃは、カレントミラー電流供給回路１２０Ｂの構成に加えて、トランジスタＴｒ３をさらに含む。トランジスタＴｒ３のドレインにダイオードＤ１のカソードが結合される。トランジスタＴｒ３のソースとゲートとの間に抵抗素子Ｒ２が接続される。 The current mirror current supply circuit 120C further includes a transistor Tr3 in addition to the configuration of the current mirror current supply circuit 120B. The cathode of the diode D1 is coupled to the drain of the transistor Tr3. A resistance element R2 is connected between the source and gate of the transistor Tr3.
　このトランジスタＴｒ３と抵抗素子Ｒ２とで構成される回路は、電流源回路１３０と同様な構成をとる。このため上記の回路は、電流源回路１５０とも称される。 The circuit composed of the transistor Tr3 and the resistance element R2 has a configuration similar to that of the current source circuit 130. For this reason, the above circuit is also referred to as a current source circuit 150.
　このような構成を取ることにより、トランジスタＴｒ２の構成による制御電流の減少効果と、トランジスタＴｒ３の構成による制御電圧依存性改善効果との両方の効果が期待できる。 By adopting such a configuration, it is possible to expect both the effect of reducing the control current due to the configuration of the transistor Tr2 and the effect of improving the control voltage dependency due to the configuration of the transistor Tr3.
　なお、電力増幅回路１００Ｃの他の構成については、電力増幅回路１００Ｂと同様なため、説明はここでは繰返さない。 Since the other configuration of power amplifier circuit 100C is the same as that of power amplifier circuit 100B, description thereof will not be repeated here.
　［実施の形態２の変形例２］
　図５は、実施の形態２の変形例２である電力増幅回路１００Ｄの回路の構成の一例を示す図である。図４の電力増幅回路１００Ｃと比較しつつ、電力増幅回路１００Ｄについて説明する。なお、電力増幅回路１００Ｄは、変形例１（電力増幅回路１００Ｃ）の変形例に相当する。図５を参照して、電力増幅回路１００Ｄは、電力増幅回路１００Ｃのカレントミラー電流供給回路１２０Ｃに代えて、カレントミラー電流供給回路１２０Ｄを含む。 [Modification 2 of Embodiment 2]
FIG. 5 is a diagram illustrating an example of a circuit configuration of a power amplifying circuit 100D that is the second modification of the second embodiment. The power amplifier circuit 100D will be described in comparison with the power amplifier circuit 100C of FIG. The power amplifier circuit 100D corresponds to a modification of the modification 1 (power amplification circuit 100C). Referring to FIG. 5, power amplification circuit 100D includes a current mirror current supply circuit 120D instead of current mirror current supply circuit 120C of power amplification circuit 100C.
　カレントミラー電流供給回路１２０Ｄは、カレントミラー電流供給回路１２０Ｃの構成を備える。加えて、カレントミラー電流供給回路１２０Ｄは、温度補償回路１４０Ａに代え、温度補償回路１４０Ｂを含む。 The current mirror current supply circuit 120D has a configuration of a current mirror current supply circuit 120C. In addition, the current mirror current supply circuit 120D includes a temperature compensation circuit 140B instead of the temperature compensation circuit 140A.
　温度補償回路１４０Ｂは、図４の温度補償回路１４０Ａと比較して、温度補償回路１４０Ａの抵抗素子Ｒ１，Ｒ２に代え、抵抗素子Ｒ１Ａ，Ｒ２Ａを含む。抵抗素子Ｒ１Ａは、温度係数の大きい抵抗素子Ｒ１２と温度係数の小さい抵抗素子Ｒ１１とを含む。同様に、抵抗素子Ｒ２Ａは、温度係数の大きい抵抗素子Ｒ２２と温度係数の小さい抵抗素子Ｒ２１とを含む。 Temperature compensation circuit 140B includes resistance elements R1A and R2A instead of resistance elements R1 and R2 of temperature compensation circuit 140A, as compared with temperature compensation circuit 140A of FIG. The resistance element R1A includes a resistance element R12 having a large temperature coefficient and a resistance element R11 having a small temperature coefficient. Similarly, the resistance element R2A includes a resistance element R22 having a large temperature coefficient and a resistance element R21 having a small temperature coefficient.
　抵抗素子Ｒ１１と抵抗素子Ｒ１２とは、ノードＮ１と接地電位との間に直列接続される。一方、抵抗素子Ｒ２１と抵抗素子Ｒ２２とは、ノードＮ２とノードＮ１との間に直列接続される。 Resistance element R11 and resistance element R12 are connected in series between node N1 and the ground potential. On the other hand, resistance element R21 and resistance element R22 are connected in series between node N2 and node N1.
　このトランジスタＴｒ３と抵抗素子Ｒ２Ａとで構成される回路は、電流源回路１３０と同様な構成をとる。このため上記の回路は、電流源回路１５０Ａとも称される。 The circuit composed of the transistor Tr3 and the resistance element R2A has the same configuration as the current source circuit 130. Therefore, the above circuit is also referred to as a current source circuit 150A.
　一般に大きい温度係数を有する抵抗素子には、半導体プロセスに応じた、半導体エピタキシャル層を利用した半導体抵抗素子が使用され、温度係数の小さい抵抗素子には金属抵抗素子が使用される。また、温度係数は材料によって決まっており、設計者が自由に変更できない。 Generally, a resistance element having a large temperature coefficient is a semiconductor resistance element using a semiconductor epitaxial layer according to a semiconductor process, and a resistance element having a small temperature coefficient is a metal resistance element. Also, the temperature coefficient is determined by the material and cannot be changed freely by the designer.
　たとえば、図１から図４に示したような電力増幅回路１００，１００Ａ～１００Ｃにおいて、抵抗素子Ｒ１や抵抗素子Ｒ２を単に半導体抵抗素子に置き換えるとしても、温度特性の傾きの変化は離散的で、柔軟に制御できない。 For example, in the power amplifying circuits 100, 100A to 100C as shown in FIGS. 1 to 4, even if the resistance element R1 or the resistance element R2 is simply replaced with a semiconductor resistance element, the change in the slope of the temperature characteristic is discrete, It cannot be controlled flexibly.
　そこで、電力増幅回路１００Ｄにおいては、半導体抵抗素子と金属抵抗を組み合わせる。それらの抵抗値の比により実効的な温度係数を変化させて、温度特性の傾きを柔軟に制御できる。 Therefore, in the power amplifier circuit 100D, a semiconductor resistance element and a metal resistance are combined. The gradient of the temperature characteristic can be flexibly controlled by changing the effective temperature coefficient according to the ratio of the resistance values.
　例えば抵抗温度係数が２０００ｐｐｍ／℃の半導体抵抗素子と抵抗温度係数が－２００ｐｐｍ／℃の金属抵抗とを組み合わせる。これにより、実効的な抵抗温度係数を、－２００ｐｐｍ／℃～２０００ｐｐｍ／℃の範囲で制御することができる。抵抗素子Ｒ１Ａと抵抗素子Ｒ２Ａのそれぞれに直列接続された複数の抵抗素子（Ｒ１１，Ｒ１２，Ｒ２１，Ｒ２２）が設けられる。複数の抵抗素子は、少なくとも±５００ｐｐｍ／℃以上の抵抗温度係数を有する抵抗素子と、±５００ｐｐｍ／℃未満の抵抗温度係数を有する抵抗素子とを組み合わせることが好ましい。なお、±５００ｐｐｍ／℃以上の抵抗温度係数を有する抵抗素子とは、抵抗温度係数の値が５００ｐｐｍ／℃以上または－５００ｐｐｍ／℃以下の抵抗素子のことをいう。±５００ｐｐｍ／℃未満の抵抗温度係数を有する抵抗素子とは、抵抗温度係数の値が－５００ｐｐｍ／℃未満～＋５００ｐｐｍ／℃未満の抵抗素子のことをいう。 For example, a semiconductor resistance element having a resistance temperature coefficient of 2000 ppm / ° C. and a metal resistance having a resistance temperature coefficient of −200 ppm / ° C. are combined. As a result, the effective temperature coefficient of resistance can be controlled in the range of −200 ppm / ° C. to 2000 ppm / ° C. A plurality of resistance elements (R11, R12, R21, R22) connected in series to each of the resistance element R1A and the resistance element R2A are provided. The plurality of resistance elements are preferably a combination of a resistance element having a resistance temperature coefficient of at least ± 500 ppm / ° C. and a resistance element having a resistance temperature coefficient of less than ± 500 ppm / ° C. A resistance element having a temperature coefficient of resistance of ± 500 ppm / ° C. or higher means a resistance element having a resistance temperature coefficient value of 500 ppm / ° C. or higher or −500 ppm / ° C. or lower. A resistance element having a resistance temperature coefficient of less than ± 500 ppm / ° C. refers to a resistance element having a resistance temperature coefficient value of less than −500 ppm / ° C. to less than +500 ppm / ° C.
　図６は、電力増幅回路１００Ｄの構成により制御したカレントミラートランジスタＣＭＴｒに流れるドレイン電流と温度との関係を示す図である。図６を参照して、縦軸にドレイン電流（ｍＡ）が示され、横軸に温度（－４０℃～１００℃）が示される。 FIG. 6 is a diagram showing the relationship between the drain current flowing through the current mirror transistor CMTr controlled by the configuration of the power amplifier circuit 100D and the temperature. Referring to FIG. 6, the vertical axis represents drain current (mA), and the horizontal axis represents temperature (−40 ° C. to 100 ° C.).
　波形Ｗ１，Ｗ２は、ともに図５に示した電力増幅回路１００Ｄのシミュレーション結果を示す波形である。波形Ｗ１と波形Ｗ２との傾きの差は、抵抗素子Ｒ１Ａ，Ｒ２Ａの実効的な抵抗温度係数の差によるものである。このように、抵抗素子の抵抗温度係数を任意に変更することにより、電力増幅回路の出力電流の元となるカレントミラートランジスタＣＭＴｒのドレイン電流を自由に制御することができる。 Waveforms W1 and W2 are both waveforms showing simulation results of the power amplifier circuit 100D shown in FIG. The difference in slope between the waveform W1 and the waveform W2 is due to the difference in effective resistance temperature coefficient between the resistance elements R1A and R2A. As described above, by arbitrarily changing the resistance temperature coefficient of the resistance element, the drain current of the current mirror transistor CMTr, which is the source of the output current of the power amplifier circuit, can be freely controlled.
　図７は、本実施の形態の電力増幅回路１００Ｄの利得と温度との関係を示す図である。図７を参照して、縦軸に電力増幅回路の利得が示され、横軸に周波数が示される。図５の電力増幅回路１００Ｄの抵抗素子Ｒ１Ａ，Ｒ２Ａの抵抗温度係数が調整されることによって、電力増幅回路１００Ｄの利得の温度依存性を減少させ、その利得を一定に保つことができていることが分かる。 FIG. 7 is a diagram showing the relationship between the gain and temperature of the power amplifier circuit 100D of the present embodiment. Referring to FIG. 7, the vertical axis represents the gain of the power amplifier circuit, and the horizontal axis represents the frequency. By adjusting the resistance temperature coefficient of the resistance elements R1A and R2A of the power amplifier circuit 100D of FIG. 5, the temperature dependence of the gain of the power amplifier circuit 100D can be reduced and the gain can be kept constant. I understand.
　ここで、図１～図５に示した各実施の形態の電力増幅回路の回路構成において、カレントミラートランジスタＣＭＴｒと増幅用トランジスタＧＴｒはＦＥＴかＨＥＭＴとして説明したが、本発明はこれに限られるものではなく、これらはバイポーラトランジスタに置き換えたとしても良い。置き換えた場合には、上述したゲート、ドレイン、ソースはそれぞれベース、コレクタ、エミッタに対応する。またＶＤＤ電源端子は、ＶＣＣ電源端子に対応する。さらに、ダイオードにはダイオード接続されたトランジスタも含まれる。 Here, in the circuit configuration of the power amplifying circuit of each embodiment shown in FIGS. 1 to 5, the current mirror transistor CMTr and the amplifying transistor GTr are described as FETs or HEMTs, but the present invention is limited to this. Instead, they may be replaced with bipolar transistors. In the case of replacement, the above-described gate, drain, and source correspond to the base, collector, and emitter, respectively. The VDD power supply terminal corresponds to the VCC power supply terminal. Further, the diode includes a diode-connected transistor.
　また、図１から図５に示した各実施の形態について、カレントミラーの構成を最も一般的な接続で成している。しかし、カレントミラートランジスタＣＭＴｒと増幅用トランジスタＧＴｒのサイズ比に応じた電流が増幅トランジスタに反映して流れる構成であればよく、カレントミラーの構成は、図に示した限りでないことは言うまでも無い。また、各実施の形態の構成としてダイオードを用いたが、これに限定されることなく、ダイオード接続されたトランジスタを利用してもよい。 In each of the embodiments shown in FIGS. 1 to 5, the current mirror is configured with the most general connection. However, it is sufficient that the current corresponding to the size ratio of the current mirror transistor CMTr and the amplifying transistor GTr flows in the amplifying transistor, and it goes without saying that the configuration of the current mirror is not limited to that shown in the figure. . Further, although the diode is used as the configuration of each embodiment, the present invention is not limited to this, and a diode-connected transistor may be used.
　最後に各実施の形態について図１等を用いて総括する。
　実施の形態１および実施の形態１の変形例である電力増幅回路は、図１、図２に示すように、ドレインが高電位に接続され、ソースが接地された増幅用トランジスタＧＴｒを備え、ソースが接地され増幅用トランジスタＧＴｒのゲートにゲートが接続されたカレントミラートランジスタＣＭＴｒによって増幅用トランジスタＧＴｒのバイアス電流を制御する電力増幅回路であって、アノードが制御電圧端子Ｐ２に接続されたダイオードＤ１と、アノードがダイオードＤ１のカソードに結合され、カソードがカレントミラートランジスタＣＭＴｒのドレインに接続されたダイオードＤ２と、一方の端子がダイオードＤ２のカソードに接続され他方の端子が接地された抵抗素子Ｒ１と、ダイオードＤ２と並列接続された抵抗素子Ｒ２とを備える。 Finally, each embodiment will be summarized with reference to FIG.
As shown in FIGS. 1 and 2, the power amplifier circuit according to the first embodiment and the modification of the first embodiment includes an amplifying transistor GTr whose drain is connected to a high potential and whose source is grounded. Is a power amplifying circuit for controlling the bias current of the amplifying transistor GTr by a current mirror transistor CMTr having a gate connected to the gate of the amplifying transistor GTr, and a diode D1 whose anode is connected to the control voltage terminal P2. A diode D2 having an anode coupled to the cathode of the diode D1, a cathode connected to the drain of the current mirror transistor CMTr, a resistance element R1 having one terminal connected to the cathode of the diode D2 and the other terminal grounded; A resistor element R2 connected in parallel with the diode D2.
　好ましくは、実施の形態１の変形例である電力増幅回路は、図２で示すように、ダイオードＤ１のカソードにドレインが接続され、ダイオードＤ２のアノードにソースが接続され、ダイオードＤ２のカソードにゲートが接続されたトランジスタＴｒ１をさらに備える。 Preferably, in the power amplifying circuit which is a modification of the first embodiment, the drain is connected to the cathode of the diode D1, the source is connected to the anode of the diode D2, and the gate is connected to the cathode of the diode D2, as shown in FIG. Is further provided.
　また、さらに好ましくは、ダイオードＤ１，Ｄ２は、ダイオード接続されたトランジスタを含む。 More preferably, the diodes D1 and D2 include diode-connected transistors.
　次に実施の形態２とその変形例の電力増幅回路は、図３～図５に示すように、ドレインが高電位に接続され、ソースが接地された増幅用トランジスタＧＴｒを備え、ソースが接地され増幅用トランジスタＧＴｒのゲートにゲートが接続されたカレントミラートランジスタＣＭＴｒによって増幅用トランジスタＧＴｒのバイアス電流を制御する電力増幅回路であって、アノードが制御電圧端子Ｐ２に接続されたダイオードＤ１と、ゲートがダイオードＤ１のカソードに結合され、ソースがカレントミラートランジスタＣＭＴｒのドレインに接続されたトランジスタＴｒ１と、一方の端子がトランジスタＴｒ１のソースに接続され他の端子が接地された抵抗素子Ｒ１と、トランジスタＴｒ１のゲートとソースの間に接続された抵抗素子Ｒ２と、増幅用トランジスタＧＴｒのドレインとトランジスタＴｒ１のドレインとの間に接続される電流源回路１３０とを備える。 Next, as shown in FIGS. 3 to 5, the power amplifying circuit according to the second embodiment and its modification includes an amplifying transistor GTr whose drain is connected to a high potential and whose source is grounded, and the source is grounded. A power amplifying circuit for controlling the bias current of the amplifying transistor GTr by a current mirror transistor CMTr having a gate connected to the gate of the amplifying transistor GTr, the diode D1 having an anode connected to the control voltage terminal P2, and a gate having a gate The transistor Tr1 coupled to the cathode of the diode D1, the source connected to the drain of the current mirror transistor CMTr, the resistance element R1 having one terminal connected to the source of the transistor Tr1 and the other terminal grounded, and the transistor Tr1 A resistance element R2 connected between the gate and the source; And a current source circuit 130 connected between the drains of the transistors Tr1 width transistor GTr.
　特に、好ましくは、電流源回路１３０は、ドレインが増幅用トランジスタＧＴｒのドレインに接続され、ゲートがトランジスタＴｒ１のドレインに接続されたトランジスタＴｒ２と、トランジスタＴｒ２のソースとゲートとの間に接続された抵抗素子Ｒ３とを含む。 In particular, preferably, the current source circuit 130 has a drain connected to the drain of the amplifying transistor GTr, a gate connected to the drain of the transistor Tr1, and a source connected to the source and gate of the transistor Tr2. And a resistance element R3.
　さらに好ましくは、実施の形態２の変形例等は、図４、図５に示すように、ダイオードＤ１のカソードにドレインが接続され、トランジスタのゲートにソースが接続され、トランジスタのソースにゲートが接続されたトランジスタＴｒ３をさらに含む。 More preferably, in the modified example of the second embodiment, as shown in FIGS. 4 and 5, the drain is connected to the cathode of the diode D1, the source is connected to the gate of the transistor, and the gate is connected to the source of the transistor. The transistor Tr3 is further included.
　さらに好ましくは、実施の形態２の変形例１の変形例は、図５に示すように、抵抗素子Ｒ１Ａと抵抗素子Ｒ２Ａのそれぞれには、直列接続された複数の抵抗素子（Ｒ１１，Ｒ１２，Ｒ２１，Ｒ２２）が設けられ、複数の抵抗素子は、少なくとも±５００ｐｐｍ／℃以上の抵抗温度係数を有する抵抗素子と、±５００ｐｐｍ／℃未満の抵抗温度係数を有する抵抗素子とを含む。 More preferably, as shown in FIG. 5, the first modification of the second embodiment has a plurality of resistance elements (R11, R12, R21) connected in series to each of the resistance elements R1A and R2A. , R22), and the plurality of resistance elements include a resistance element having a resistance temperature coefficient of at least ± 500 ppm / ° C. and a resistance element having a resistance temperature coefficient of less than ± 500 ppm / ° C.
　好ましくは、実施の形態２および実施の形態２の変形例等に含まれるダイオードＤ１は、ダイオード接続されたトランジスタを含む。 Preferably, the diode D1 included in the second embodiment and the modification of the second embodiment includes a diode-connected transistor.
　上述したトランジスタは、ＦＥＴあるいはＨＥＭＴを前提として説明したが、これに限定されることなく、バイポーラトランジスタを用いても同様な効果を奏する。図９を参照して、バイポーラトランジスタを用いた実施の形態１に対応する電力増幅回路１００Ｅは、コレクタが高電位に接続され、エミッタが接地された増幅用トランジスタＧＴｒを備え、エミッタが接地され増幅用トランジスタＧＴｒのベースにベースが接続されたカレントミラートランジスタＣＭＴｒによって増幅用トランジスタＧＴｒのバイアス電流を制御する電力増幅回路であって、アノードが制御電圧端子Ｐ２に接続されたダイオードＤ１と、アノードがダイオードＤ１のカソードに結合され、カソードがカレントミラートランジスタＣＭＴｒのコレクタに接続されたダイオードＤ２と、一方の端子がダイオードＤ２のカソードに接続され他方の端子が接地された抵抗素子Ｒ１と、ダイオードＤ２と並列接続された抵抗素子Ｒ２とを備える。 Although the above-described transistor has been described on the assumption of an FET or HEMT, the present invention is not limited to this, and the same effect can be obtained by using a bipolar transistor. Referring to FIG. 9, power amplifying circuit 100E corresponding to the first embodiment using a bipolar transistor includes an amplifying transistor GTr whose collector is connected to a high potential and whose emitter is grounded, and whose emitter is grounded and amplified. A power amplifying circuit that controls a bias current of the amplifying transistor GTr by a current mirror transistor CMTr having a base connected to a base of the transistor for transistor GTr, a diode D1 whose anode is connected to the control voltage terminal P2, and a diode that is a diode The diode D2 is coupled to the cathode of D1, the cathode is connected to the collector of the current mirror transistor CMTr, the resistance element R1 having one terminal connected to the cathode of the diode D2 and the other terminal grounded, and the diode D2. Connected resistance element R2 Equipped with a.
　また、図１０を参照して、バイポーラトランジスタを用いた実施の形態２に対応する電力増幅回路１００Ｆは、コレクタが高電位に接続され、エミッタが接地された増幅用トランジスタＧＴｒを備え、エミッタが接地され増幅用トランジスタＧＴｒのベースにベースが接続されたカレントミラートランジスタＣＭＴｒによって増幅用トランジスタＧＴｒのバイアス電流を制御する電力増幅回路であって、アノードが制御電圧端子Ｐ２に接続されたダイオードＤ１と、ゲートがダイオードＤ１のカソードに結合され、ソースがカレントミラートランジスタＣＭＴｒのコレクタに接続されたトランジスタＴｒ１と、一方の端子がトランジスタＴｒ１のソースに接続され他の端子が接地された抵抗素子Ｒ１と、トランジスタＴｒ１のゲートとソースの間に接続された抵抗素子Ｒ２と、増幅用トランジスタのコレクタと第１のトランジスタのドレインとの間に接続される電流源回路とを備える。 Referring to FIG. 10, power amplifier circuit 100F corresponding to the second embodiment using a bipolar transistor includes an amplifying transistor GTr whose collector is connected to a high potential and whose emitter is grounded, and whose emitter is grounded. A power amplifying circuit that controls the bias current of the amplifying transistor GTr by a current mirror transistor CMTr whose base is connected to the base of the amplifying transistor GTr, and has a diode D1 whose anode is connected to the control voltage terminal P2, and a gate Is coupled to the cathode of the diode D1, the source is connected to the collector of the current mirror transistor CMTr, the transistor Tr1, one terminal connected to the source of the transistor Tr1, and the other terminal grounded, and the transistor Tr1 The gate and saw It includes a resistance element R2 connected between, and a current source circuit which is connected between the drain of the collector and the first transistor of the amplifying transistor.
　特に、この電流源回路は、ドレインが増幅用トランジスタＧＭＴｒのコレクタに接続され、ゲートがトランジスタＴｒ１のドレインに接続されたトランジスタＴｒ２と、トランジスタＴｒ２のソースとゲートとの間に接続された抵抗素子Ｒ３とを含む。 In particular, this current source circuit includes a transistor Tr2 having a drain connected to the collector of the amplifying transistor GMTr and a gate connected to the drain of the transistor Tr1, and a resistance element R3 connected between the source and gate of the transistor Tr2. Including.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　１，１Ａ～１Ｄ　バイアス回路、１００，１００Ａ～１００Ｄ　電力増幅回路、１１０　カレントミラー回路、１２０，１２０Ａ～１２０Ｄ　カレントミラー電流供給回路、１３０，１５０，１５０Ａ　電流源回路、１４０，１４０Ａ，１４０Ｂ　温度補償回路、ＣＭＴｒ　カレントミラートランジスタ、Ｄ１，Ｄ２　ダイオード、ＧＴｒ　増幅用トランジスタ、Ｐ１　ＶＤＤ電源端子、Ｐ２　制御電圧端子、Ｒ１，Ｒ２，Ｒ１Ａ，Ｒ２Ａ，Ｒ１１，Ｒ１２，Ｒ２１，Ｒ２２　抵抗素子、Ｔｒ１，Ｔｒ２，Ｔｒ３　トランジスタ。 1, 1A-1D bias circuit, 100, 100A-100D power amplification circuit, 110 current mirror circuit, 120, 120A-120D current mirror current supply circuit, 130, 150, 150A current source circuit, 140, 140A, 140B temperature compensation circuit , CMTr current mirror transistor, D1, D2 diode, GTr amplification transistor, P1, VDD power supply terminal, P2, control voltage terminal, R1, R2, R1A, R2A, R11, R12, R21, R22 resistance element, Tr1, Tr2, Tr3 transistor .

Claims (11)

  1. 　電力増幅回路であって、
    　ドレインが高電位に接続され、ソースが接地された増幅用トランジスタと、ソースが接地され前記増幅用トランジスタのゲートにゲートが接続されたカレントミラートランジスタとを含むカレントミラー回路と、
    　アノードが制御電源端子に接続された第１のダイオードと、
    　アノードが前記第１のダイオードのカソードに結合され、カソードが前記カレントミラートランジスタのドレインに接続された第２のダイオードと、
    　一方の端子が前記第２のダイオードのカソードに接続され他方の端子が接地された第１の抵抗素子と、
    　前記第２のダイオードと並列接続された第２の抵抗素子とを備える、電力増幅回路。     A power amplifier circuit,
    A current mirror circuit including an amplifying transistor having a drain connected to a high potential and a source grounded; and a current mirror transistor having a source grounded and a gate connected to a gate of the amplifying transistor;
    A first diode having an anode connected to the control power supply terminal;
    A second diode having an anode coupled to the cathode of the first diode and a cathode connected to the drain of the current mirror transistor;
    A first resistance element having one terminal connected to the cathode of the second diode and the other terminal grounded;
    A power amplifier circuit comprising: a second resistance element connected in parallel with the second diode.
  2. 　前記電力増幅回路は、
    　前記第１のダイオードのカソードにドレインが接続され、前記第２のダイオードのアノードにソースが接続され、前記第２のダイオードのカソードにゲートが接続された第１のトランジスタをさらに備える、請求項１に記載の電力増幅回路。     The power amplifier circuit includes:
    The first transistor, further comprising a first transistor having a drain connected to the cathode of the first diode, a source connected to the anode of the second diode, and a gate connected to the cathode of the second diode. The power amplifier circuit described in 1.
  3. 　前記第１または第２のダイオードは、ダイオード接続されたトランジスタを含む、請求項１に記載の電力増幅回路。 The power amplification circuit according to claim 1, wherein the first or second diode includes a diode-connected transistor.
  4. 　電力増幅回路であって、
    　ドレインが高電位に接続され、ソースが接地された増幅用トランジスタと、ソースが接地され前記増幅用トランジスタのゲートにゲートが接続されたカレントミラートランジスタとを含むカレントミラー回路と、
    　アノードが制御電源端子に接続された第１のダイオードと、
    　ゲートが前記第１のダイオードのカソードに結合され、ソースが前記カレントミラートランジスタのドレインに接続された第１のトランジスタと、
    　一方の端子が前記第１のトランジスタのソースに接続され他の端子が接地された第１の抵抗素子と、
    　前記第１のトランジスタのゲートとソースの間に接続された第２の抵抗素子と、
    　前記増幅用トランジスタのドレインと前記第１のトランジスタのドレインとの間に接続される電流源回路とを備える、電力増幅回路。     A power amplifier circuit,
    A current mirror circuit including an amplifying transistor having a drain connected to a high potential and a source grounded; and a current mirror transistor having a source grounded and a gate connected to the gate of the amplifying transistor;
    A first diode having an anode connected to the control power terminal;
    A first transistor having a gate coupled to the cathode of the first diode and a source connected to the drain of the current mirror transistor;
    A first resistance element having one terminal connected to the source of the first transistor and the other terminal grounded;
    A second resistance element connected between a gate and a source of the first transistor;
    A power amplifier circuit comprising: a current source circuit connected between the drain of the amplifying transistor and the drain of the first transistor.
  5. 　前記電流源回路は、
    　ドレインが前記増幅用トランジスタのドレインに接続され、ゲートが前記第１のトランジスタのドレインに接続された第２のトランジスタと、
    　前記第２のトランジスタのソースとゲートとの間に接続された第３の抵抗素子とを含む、請求項４に記載の電力増幅回路。     The current source circuit is:
    A second transistor having a drain connected to the drain of the amplification transistor and a gate connected to the drain of the first transistor;
    The power amplifier circuit according to claim 4, further comprising a third resistance element connected between a source and a gate of the second transistor.
  6. 　前記第１のダイオードのカソードにドレインが接続され、前記第１のトランジスタのゲートにソースが接続され、前記第１のトランジスタのソースにゲートが接続された第３のトランジスタをさらに含む、請求項５に記載の電力増幅回路。 6. The method further comprises a third transistor having a drain connected to the cathode of the first diode, a source connected to the gate of the first transistor, and a gate connected to the source of the first transistor. The power amplifier circuit described in 1.
  7. 　前記第１の抵抗素子と前記第２の抵抗素子との各々は、
    　直列接続された複数の抵抗素子を含み、
    　前記複数の抵抗素子は、±５００ｐｐｍ／℃以上の抵抗温度係数を有する抵抗素子と、±５００ｐｐｍ／℃未満の抵抗温度係数を有する抵抗素子とを含む、請求項６に記載の電力増幅回路。     Each of the first resistance element and the second resistance element is:
    Including a plurality of resistance elements connected in series;
    The power amplification circuit according to claim 6, wherein the plurality of resistance elements include a resistance element having a resistance temperature coefficient of ± 500 ppm / ° C. or more and a resistance element having a resistance temperature coefficient of less than ± 500 ppm / ° C.
  8. 　前記第１のダイオードはダイオード接続されたトランジスタを含む、請求項４に記載の電力増幅回路。 The power amplifier circuit according to claim 4, wherein the first diode includes a diode-connected transistor.
  9. 　電力増幅回路であって、
    　コレクタが高電位に接続され、エミッタが接地された増幅用トランジスタと、エミッタが接地され前記増幅用トランジスタのベースにベースが接続されたカレントミラートランジスタとを含むカレントミラー回路と、
    　アノードが制御電源端子に接続された第１のダイオードと、
    　アノードが前記第１のダイオードのカソードに結合され、カソードが前記カレントミラートランジスタのコレクタに接続された第２のダイオードと、
    　一方の端子が前記第２のダイオードのカソードに接続され他方の端子が接地された第１の抵抗素子と、
    　前記第２のダイオードと並列接続された第２の抵抗素子とを備える、電力増幅回路。     A power amplifier circuit,
    A current mirror circuit including an amplifying transistor having a collector connected to a high potential and an emitter grounded, and a current mirror transistor having an emitter grounded and a base connected to a base of the amplifying transistor;
    A first diode having an anode connected to the control power supply terminal;
    A second diode having an anode coupled to the cathode of the first diode and a cathode connected to the collector of the current mirror transistor;
    A first resistance element having one terminal connected to the cathode of the second diode and the other terminal grounded;
    A power amplifier circuit comprising: a second resistance element connected in parallel with the second diode.
  10. 　電力増幅回路であって、
    　コレクタが高電位に接続され、エミッタが接地された増幅用トランジスタと、エミッタが接地され前記増幅用トランジスタのベースにベースが接続されたカレントミラートランジスタとを含むカレントミラー回路と、
    　アノードが制御電源端子に接続された第１のダイオードと、
    　ゲートが前記第１のダイオードのカソードに結合され、ソースが前記カレントミラートランジスタのコレクタに接続された第１のトランジスタと、
    　一方の端子が前記第１のトランジスタのソースに接続され他の端子が接地された第１の抵抗素子と、
    　前記第１のトランジスタのゲートとソースの間に接続された第２の抵抗素子と、
    　前記増幅用トランジスタのコレクタと前記第１のトランジスタのドレインとの間に接続される電流源回路とを備える、電力増幅回路。     A power amplifier circuit,
    A current mirror circuit including an amplifying transistor having a collector connected to a high potential and an emitter grounded, and a current mirror transistor having an emitter grounded and a base connected to a base of the amplifying transistor;
    A first diode having an anode connected to the control power supply terminal;
    A first transistor having a gate coupled to the cathode of the first diode and a source connected to the collector of the current mirror transistor;
    A first resistance element having one terminal connected to the source of the first transistor and the other terminal grounded;
    A second resistance element connected between the gate and source of the first transistor;
    A power amplifier circuit comprising: a current source circuit connected between a collector of the amplifying transistor and a drain of the first transistor.
  11. 　前記電流源回路は、
    　ドレインが前記増幅用トランジスタのコレクタに接続され、ゲートが前記第１のトランジスタのドレインに接続された第２のトランジスタと、
    　前記第２のトランジスタのソースとゲートとの間に接続された第３の抵抗素子とを含む、請求項１０に記載の電力増幅回路。     The current source circuit is:
    A second transistor having a drain connected to the collector of the amplifying transistor and a gate connected to the drain of the first transistor;
    The power amplifier circuit according to claim 10, further comprising a third resistance element connected between a source and a gate of the second transistor.
PCT/JP2012/073029 2011-11-04 2012-09-10 Power amplifying circuit WO2013065401A1 (en)

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