JP2003177717A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily use a display device, depending on the situation, for a digital data image display, which is suitable for still picture display, and an analog data display, which is suitable for multigradation display such as a natural picture or the like. <P>SOLUTION: When digital data image display is to be conducted, digital data supplied from first display control lines 1 to n are written into digital memory elements 100. A white or a black display reference voltage is supplied to pixel electrodes 5 from second display control lines 2 to n or a third display control line 3 through second switch elements 9 or third switch elements 10 in accordance with the contents of the memory storage. When analog data display is to be conducted, the elements 100 are made non-active, analog data being supplied from the lines 2 to n through the elements 9 are supplied to the electrodes 5. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as an active matrix type liquid crystal display device, and in particular, it realizes a display of a high definition image suitable for a display device such as a mobile phone or a small information terminal with low power consumption. The present invention relates to a display device that can be used.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is widely used as a display device for replacing a cathode ray tube (CRT) in a display device of various information processing devices, a portable telephone, a wall-mounted television, and the like. In particular, in recent years, it has been attracting attention as a display device that can be made thin and lightweight, and is used in a portable information processing device such as a so-called notebook computer.

Among such liquid crystal display devices, in particular,
Thin film transistor (hereinafter, referred to as T) formed of polycrystalline silicon (hereinafter, referred to as P-Si)
It is called FT. ) Is provided in the pixel portion as a switch element, while a TFT having the same structure is provided in the peripheral portion of the switch element array substrate to form a drive circuit. Research and development of a so-called drive circuit integrated active matrix type liquid crystal display device. Is being actively conducted.

The structure and operation of a conventional active matrix type liquid crystal display device will be briefly described below.

FIG. 10 is a diagram showing an outline of a circuit structure of a general conventional liquid crystal display device. The conventional liquid crystal display device includes a plurality of horizontal scanning lines 902 arranged in a matrix.
And a data line 901, a pixel electrode 903, a pixel portion switch element 904 controlled by a horizontal scanning line between the pixel electrode 903 and the data line 901, and a pixel electrode 903 which is located in a subsequent stage of the pixel portion switch element 904. A switch element array substrate 906 having one end connected to the preceding stage and the other end connected to a Cs line, and a switch element array substrate 906, and a counter electrode 907 provided with a counter electrode 907 which is arranged to face the pixel electrode 903 while keeping a gap. The pixel electrode 903 and the counter electrode 9 are sandwiched between a substrate (not shown) and the counter substrate and the switch element array substrate 906 so as to be sealed.
07, a liquid crystal layer that forms a liquid crystal capacitor 908, a data line driver 909 that drives the data line 901, and a horizontal scanning line driver 910 that drives a horizontal scanning line. .

Generally, as the drive circuit system, for example, an externally attached shift register type liquid crystal driver IC is used. Alternatively, for example, a P-SiTFT is used as the pixel part switching element 904, and the P-SiTFT is used.
Therefore, a so-called drive circuit integrated type liquid crystal display device in which the above drive circuit system is directly formed on the same substrate is also proposed.

Next, the operation of the liquid crystal display device having the conventional structure as described above will be briefly described. When a horizontal scanning line is selected by the horizontal scanning line driver 910, the pixel section switch element 90 connected to the horizontal scanning line is selected.
4 becomes conductive. At this time, the data line driver 90
A data line 901 corresponding to image data is selected by 9, and a voltage corresponding to image data such as a video signal is applied to the data line 901.

Then, the data line 90 is connected through the pixel section switch element 904 connected to the selected horizontal scanning line and the selected data line 901.
A voltage is supplied from 1 to accumulate charges in the charge storage capacitor 905, and the voltage is written to the pixel electrode 903 connected thereto. Then, the liquid crystal cell (liquid crystal capacitor) 908 is applied with this voltage and performs light modulation corresponding to the voltage, thereby realizing image display.

During the horizontal scanning period, the data line 901 is sequentially selected by the data line driver 909 from one of the left and right ends to the other end. Then, on the horizontal scanning line side, when writing of a video signal to one horizontal scanning line is completed, the next horizontal scanning line is selected. Such horizontal scanning lines are sequentially selected from top to bottom or vice versa. When this scanning selection reaches the final horizontal scanning line, the first horizontal scanning line is returned again and the above operation is repeated. By repeating such scanning selection, the image of the entire screen of the liquid crystal display device is selected and displayed, and one frame (or one field) of the screen is formed for each horizontal scanning period.

The greatest advantage of the liquid crystal display device as described above is generally that it is thin and lightweight as described above. Taking advantage of this advantage, liquid crystal display devices have come to be mounted as display devices for portable information processing devices such as notebook personal computers.

A portable information processing device such as a notebook type personal computer must be portable, so that a battery-driven system is generally adopted. Therefore, at present, a battery can be used for a long time with a single charge. There is a limit depending on the power capacity of. Therefore, various measures have been attempted to extend the usable time that can be continued by one charge, but it goes without saying that the power capacity of the battery itself is increased, and at the same time, the liquid crystal display device has a low power consumption. Power consumption is an important issue.

In particular, in recent years, with respect to the power capacity of the battery itself, it is an essential condition that it be portable, so that the power capacity must be increased without increasing the weight of the battery. However, the improvement of the power capacity density (capacity / weight) of the battery is already close to the limit of technical improvement in the field of commonly used batteries, and further substantial improvement is practically hardly expected. The current situation is that there are none. Therefore, the reduction of the power consumption of the liquid crystal display device has become an important issue.

In order to reduce the power consumption of the liquid crystal display device, two main measures can be considered. First, the liquid crystal display device is a non-light-emitting element, which requires illuminating light, but is to reduce the power for supplying the illuminating light.

However, in the conventional liquid crystal display device using a so-called backlight, the improvement of the light emission efficiency and the utilization efficiency of the backlight is almost at the limit at present. Moreover, as the screen definition and the number of pixels in the active matrix type liquid crystal display device using the TFT are further increased, the opening ratio of the pixel portion tends to be further decreased, so that the power consumption in terms of the backlight is reduced. There is a problem that is difficult.

A second measure for reducing the power consumption of the liquid crystal display device is to reduce the so-called driving power required to drive the liquid crystal display device itself to display an image on the liquid crystal panel. . However, in the conventional liquid crystal display device, it is very difficult to greatly reduce the amount of driving power.

In the conventional liquid crystal display device, a drive system generally called a dynamic drive type is adopted. That is, in the conventional liquid crystal display device, as shown in FIG. 10, the voltage of the data line is once stored in the charge storage capacitor and is also applied to the pixel electrode to write the liquid crystal applied voltage to the liquid crystal cell for each pixel. It is carried out.

Therefore, during the period after the voltage of the data line is written in the liquid crystal cell of one pixel after one selection period, current leaks from the liquid crystal capacitance and charge storage capacitance of the pixel. The voltage held by the liquid crystal capacitor is lowered, causing display deterioration such as a decrease in brightness and contrast.

Therefore, in order to maintain a high quality display image,
Even when displaying a still image, the data line driver and the horizontal scanning line driver must be operated at all times to constantly write a voltage to each pixel and hold the voltage. This means that the circuit structure including the liquid crystal capacitance, the charge storage capacitance, and the pixel section switching element must always be refreshed as if it were a DRAM (dynamic RAM). As described above, the power for constantly operating the drive circuit system and the power for refreshing each pixel portion are required, which is extremely disadvantageous in terms of power consumption, and is rather contrary to power consumption reduction. The problem was that it was even something.

As a low power consumption type liquid crystal display device intended to solve such a problem, a static type liquid crystal display device in which a digital memory element is arranged in a pixel has been proposed. This liquid crystal display device is capable of (1) stopping input of a video signal from the outside during still image display, achieving low power consumption, and (2) digitizing pixel voltages for display by crosstalk or the like. It has the advantage that quality deterioration is unlikely to occur.

However, on the other hand, since the structure is such that a digital memory element formed by combining a plurality of switching elements composed of thin film transistors (TFTs) is formed for each pixel, one TFT per pixel is used as a pixel section switching element. As compared with the dynamic type liquid crystal display device used as above, there is a problem that the structure is extremely complicated and the manufacturing yield thereof is reduced.

In a liquid crystal display device used in a portable information processing device in which the number of pixels and the definition are increasing more and more in recent years, since the pixels are further miniaturized, the structure of the pixel portion as described above is used. However, there is a problem in that the circuit structure including the digital memory element cannot fit in each pixel area in some cases.

That is, there is a problem that the above structure cannot be practically adopted. Alternatively, the pixel opening cannot be provided only for a small area left by being occupied by the circuit structure that requires such a complicated and large occupied area. As a result, the brightness of the screen becomes low, or the power required for lighting such as a backlight must be increased in order to obtain a predetermined brightness with a narrow pixel aperture area, which is contrary to low power consumption. The problem of.

A static type liquid crystal display device having a digital memory element in such a pixel is disclosed and proposed in, for example, JP-A-58-23091. FIG. 11 shows a first example of a circuit structure relating to such a conventional static type liquid crystal display device, and FIG. 12 shows a second example thereof.

In these conventional examples, a pixel section switch element 904 connected to a data line 901 and controlled by a scanning line 902, a digital memory element 911,
An additional circuit 912 for inverting the polarity of the applied voltage at a predetermined timing for AC driving the liquid crystal cell (liquid crystal capacitor 908) of each pixel is formed.

These basic operations are to latch the video signal from the data line 901 in the digital memory element 911 and write the signal to the liquid crystal cell (liquid crystal capacitor 908) of each pixel.

Here, the digital memory element holds the previous signal until a new signal is written. Therefore, once the signal is written, the data line driver 909 and the scanning line driver 910 are set. Even when stopped, it is possible to continuously display the images written so far as a still image. Therefore, it is possible to realize low power consumption of driving as a liquid crystal display device when displaying a still image.

As the additional circuit 912, an example in which an exclusive NOR circuit is used in the first conventional example, and a transfer gate is used in the second conventional example to selectively input an AC signal from the outside for each pixel. Examples are given for each.

By the way, as described above, when a DC voltage is continuously applied to the liquid crystal cell, dielectric polarization occurs in the liquid crystal molecules and the characteristics are deteriorated. In the example, the liquid crystal cell is AC driven by applying positive and negative signals to both the counter electrode and the pixel electrode.

[0029]

However, the above-mentioned conventional liquid crystal display device is capable of displaying only digital data using a digital memory element that always has a memory function, and displays a natural image or the like which is analog data. You have the problem that you can not do.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to have excellent low power consumption characteristics at the time of displaying a still image by digital data and to provide a high quality multi-story without increasing the manufacturing process. An object is to provide a display device capable of key display.

[0031]

In order to solve the above-mentioned problems, the display device of the present invention sends the first display reference voltage to the pixel in the digital data display mode, and when in the analog data display mode. First switch means for sending an analog data signal to the pixel, a second switch means for sending a second display reference voltage to the pixel in the digital data display mode, and a digital data signal in the digital data display mode. And a digital memory element that has a high impedance in the analog data display mode while each of the first and second switch means is selectively turned on.

According to the above invention, the digital data signal is stored in the digital memory element in the digital data display mode. The first or second switch means is selectively turned on by the digital memory element. As a result, a first display reference voltage (for example, a black display reference voltage) is supplied to the pixel via the first switch means,
Alternatively, a second display reference voltage (eg, white display reference voltage) is supplied to the pixel via the second switch means. As a result, digital data display is performed according to the storage state of the digital memory element.

As described above, since the first and second display reference voltages are supplied to the pixel via the first and second switch means, the pixel voltage is the same as the above-mentioned first or second display reference voltage. And does not change over time. Therefore, when there is no change in the data itself, the rewriting operation that is required every predetermined period as in the past is not necessary.

As the frame writing frequency,
Since it is possible to set the frequency to about 60 Hz which is normal or lower, it is possible to significantly reduce power consumption. This makes it possible to significantly reduce power consumption particularly when displaying a still image, and to provide a display device suitable for a portable information processing device.

On the other hand, in the analog data display mode, the digital memory element has a high impedance,
Stop the memory function. Therefore, the digital data display according to the storage state of the digital memory element is not performed.

At this time, the analog data signal is the first
It is supplied to the pixel through the switch means. This allows
The brightness of the pixel is controlled according to the analog data signal supplied to the pixel (in the case of a liquid crystal display device, the alignment state of liquid crystal molecules is changed to control the brightness of the pixel), and multi-gradation analog data display Is possible.

In the conventional static drive type liquid crystal display device and the like, the digital memory element always fulfilled the memory function, so that the analog data display could not be performed. In addition, both the digital data display according to the storage state of the digital memory element and the analog data display such as a natural image performed by stopping the memory function of the digital memory element can be performed by one display device.

According to the above invention, since it has the function of stopping the memory function of the digital memory element as described above, the digital data display mode which is a low power consumption mode and the high-quality analog data display mode. It is possible to use different modes. Such a structure is effective for downsizing by adopting a reflective cell structure and integrally forming a drive circuit.

The digital memory element comprises a NAND circuit and a clocked inverter element. In the analog data display mode, the clocked inverter element has a high impedance and stops the memory function of the digital memory element. It is preferable.

The clocked inverter element is the first P
Type MOS transistor, first N-type MOS transistor,
And a second N-type MOS transistor are connected in series between the power supplies in this order, and the first P-type MOS transistor and the gate of the first N-type MOS transistor are connected as an input, and the first P-type MOS transistor and the first N-type M transistor are connected.
It is preferable that the connection point of the OS transistor be an output and that the clocked inverter element has a high impedance when the second N-type MOS transistor is non-conductive.

As described above, the memory function of the digital memory element can be stopped in the analog data display mode with a simple structure.

The digital memory device is a NOR
The clocked inverter element may include a circuit and a clocked inverter element, and in the analog data display mode, the clocked inverter element has a high impedance and stops the memory function of the digital memory element.

Further, the clocked inverter element is
The first P-type MOS transistor, the second P-type MOS transistor, and the first N-type MOS transistor are serially connected between the power supplies in this order, and the gates of the second P-type MOS transistor and the first N-type MOS transistor are connected. And a second P-type MOS transistor and a first
In addition to outputting the connection point of the N-type MOS transistor,
The clocked inverter element may have a high impedance when the first P-type MOS transistor is non-conductive.

One of the first and second display reference voltages is a black display reference voltage, the other is a white display reference voltage, and at least one is an AC voltage whose polarity is inverted every predetermined period. Preferably there is. in this case,
It is possible to reliably avoid deterioration of the display characteristics of the display device.

When the display device is a liquid crystal display device,
The white display reference voltage supplied in the normally white mode is preferably the same voltage as the voltage applied to the counter electrode of the pixel.

When the display device is a liquid crystal display device,
The black display reference voltage supplied in the normally black mode is preferably the same voltage as the voltage applied to the counter electrode of the pixel.

In these cases, since the same voltage as the counter electrode of the pixel can be used (shared) as the white display reference voltage or the black display reference voltage, it is not necessary to separately prepare a power source, and the configuration can be simplified.

At least a part of the pixel electrode is formed with a film whose surface reflects light via an electrically insulating layer on at least one of the digital memory element, the first switch means, and the second switch means. It is preferable that the pixel electrode is a reflective or semi-transmissive pixel electrode.

In this case, since the pixel electrode can be formed on the circuit of the digital memory element or the like, the area occupied by the pixel electrode can be made sufficiently wide without being affected by the area occupied by the digital memory element and its wiring. . Moreover, since a backlight etc. is not necessary, a display with higher brightness can be displayed.
Furthermore, it can be realized with low power consumption, and is very suitable as a portable display device.

A plurality of drive circuits for supplying various drive signals to the pixels are provided, and these drive circuits are provided on the switch element array substrate provided with the first and second switch means. It is preferably formed of the same material as at least one of the two switch means. In this case, since they are formed of the same material, it is possible to surely reduce the manufacturing cost and downsize the device.

A plurality of drive circuits for supplying various drive signals to the pixels are provided, and the drive capability of these drive circuits as a whole is preferably larger than the drive capability of the clocked inverter element. In this case, the output is performed from the clocked inverter in the initial state, but since the signal is supplied with a driving force larger than that, reliable operation can be secured.

It is preferable that each of the switch means is formed of a thin film transistor. Further, it is more preferable that each of the switch means is formed of a polycrystalline silicon thin film transistor. In this case, the device can be made thin and lightweight.

It is preferable that each of the above switch means is formed at a process temperature of 600 ° C. or lower.

[0054]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 1 to 9.

Embodiments in which the display device of the present invention is applied to a liquid crystal display device will be described below in detail with reference to the drawings. First, the first embodiment of the liquid crystal display device will be described in detail.

FIG. 1 is an equivalent circuit diagram showing the outline of the configuration of the liquid crystal display device according to the first embodiment of the present invention. In FIG. 1, a plurality of first display control lines 1-n, a plurality of second display control lines 2-n, a third display control line 3 and a plurality of X address signal lines 4-n are arranged in a matrix form. They are arranged almost orthogonally. Each lattice of this matrix corresponds to one pixel, and one pixel electrode 5 for forming a pixel is formed in this lattice.

The pixel electrode 5 itself is not shown in FIG. 1, but is represented as an upper electrode (terminal) of each liquid crystal cell in an equivalent circuit.

The main part of the liquid crystal display device according to the present embodiment is, for each pixel in each grid, a plurality of X address signal lines 4-n and a plurality of first display controls which are arranged in a matrix so as to intersect each other. A line 1-n, a plurality of second display control lines 2-n, a third display control line 3, a pixel electrode 5 arranged for each grid of this matrix, and the X address signal line 4-n to turn on. The first switch element 8 whose off state is controlled, and the display mode control line 15 controls the active or inactive state.
The digital memory element 100 that holds the voltage supplied from the first display control line 1-n via the above as digital data, and the output of this digital memory element 100 causes the pixel electrode 5 and the second display control line to pass. 2-n or a switch including a second switch element 9 (first switch means) and a third switch element 10 (second switch means) provided for each grid for controlling connection with the third display control line 3. An element array substrate, an opposed substrate having an opposed electrode 7 opposed to the pixel electrode 5 with a gap therebetween, and a liquid crystal layer sandwiched between the switch element array substrate and the opposed substrate. And a liquid crystal cell 6 which is formed.

The above digital memory device 100 is shown in FIG.
As shown in (a), it is composed of a NAND circuit 11 and a clocked inverter element 13. In the digital memory element 100, one input terminal of the NAND circuit 11 and the output terminal of the clocked inverter element 13 are connected to the gate of the second switch element 9. The output terminal of the NAND circuit 11 and the input terminal of the clocked inverter element 13 are connected to the gate of the third switch element 10. NAND circuit 11
The other input terminal and the clock input terminal of the clocked inverter element 13 are connected to the display mode control line 15.

The above clocked inverter element 13 is
As shown in FIG. 2B, one P-type MOS transistor 13a and two N-type MOS transistors 13b and 13c are connected in series in this order between the HI power supply and the LO power supply. There is. The gate of the P-type MOS transistor 13a and the gate of the N-type MOS transistor 13b are
It is connected to the gate of the third switch element 10 described above. In addition, the P-type MOS transistor 13a and the N-type MOS
The connection point of the transistor 13b is connected to the gate of the second switch element 9 described above. The gate of the N-type MOS transistor 13c is connected to the display mode control line 15.

The N-type MOS transistor 13c becomes conductive when a high level signal is applied to its gate, and the above digital memory device 100 becomes active, while it becomes non-conductive when a low level signal is applied to its gate. It becomes conductive and becomes high impedance (Hi-Z), and the digital memory device 100 becomes non-active (see FIG. 2).
(See (c)).

The counter electrode 7 is connected to a constant voltage power supply circuit (not shown) that outputs a constant voltage. Also, X
The address scanning line driver 18, the digital data driver 19, and the analog data driver 20 are provided on the peripheral edge portion (not shown) of the TFT array substrate together with the materials used for at least one of the TFTs. They are arranged using the same material. In this case, it is possible to surely reduce the manufacturing cost and the manufacturing process and downsize the device.

FIG. 3 is a plan view showing a specific circuit configuration of the liquid crystal display device according to the present embodiment, particularly in a pixel portion, and a schematic sectional structure thereof is a cross-sectional view taken along the line AA of FIG. 4 shows.

According to FIGS. 3 and 4, a P-Si (polycrystalline silicon) film 302 is used as an active layer on a glass substrate 301 which is an electrically insulating substrate, and the first switch element 8 and the first switch element 8 are provided for each pixel. 2 switch elements 9, 3rd switch element 1
0, the NAND circuit 11 constituting the digital memory device 100, various TFTs 303 such as the clocked inverter 13
Are formed.

The P-Si film 302 was formed by forming an a-Si (amorphous silicon) thin film by a low pressure CVD apparatus and then annealing it in a nitrogen atmosphere at 600 ° C. in an annealing furnace. This annealing is 60
It is preferable to carry out at a temperature of 0 ° C. or lower.

The gate insulating film 304 and the first interlayer insulating film 305 are SiO formed by an atmospheric pressure CVD apparatus.
An x (silicon oxide) film was used. As the gate electrode 306, a TaN / W multilayer thin film was used in order to reduce the resistance. Then, an electrode 30 such as a source electrode or a drain electrode
7 was formed using an Al film.

The display mode control line 15, the Hi power supply line 16, and the Lo power supply line 17 are formed by using TaN / W multilayer thin films as wirings in a direction substantially parallel to the X address signal line 4-n. The first display control line 1-n, the second display control line 2-n, and the third display control line 3 were each formed by using an Al film as wiring in a direction substantially orthogonal to the X address signal line 4-n. Then, the digital memory device 10
0, the first display control line 1-n, the second display control line 2-n, and the third display control line 3 are covered with the second interlayer insulating film 310 to secure electrical insulation. A reflective pixel electrode 5 was formed on the second interlayer insulating film by using an Al film.

The second interlayer insulative film 310 has a two-layer structure of a SiOx (silicon oxide) film formed by an atmospheric pressure CVD apparatus and a SiNx (silicon nitride) film formed by a plasma CVD apparatus. The pixel electrode 5 and the circuit element formed for each pixel portion are electrically connected through the contact hole 311 and the alignment film 3 is formed so as to cover almost the entire surface thereof.
13 is formed.

On the other hand, the counter electrode 12 made of a transparent conductive film such as black matrix BM and ITO is formed on the second glass substrate 312, and further includes almost the entire surface of the glass substrate 312. Alignment film 31
3 is formed, and the main part of the counter substrate 314 is formed. The liquid crystal composition 315 is provided between these two substrates.
Is sealed and injected and sandwiched.

In the structure as described above, light is incident from the counter substrate 314 side, reflected on the pixel electrode 5 and light-modulated by the liquid crystal cell for each pixel, and reflected from the liquid crystal cell on the pixel electrode. The light is emitted again to the counter substrate 314 side, and is formed so as to function as a so-called reflective liquid crystal display device.

Such a structure has a digital memory device 1
Since the pixel electrode 5 can be formed on a circuit such as 00, the occupied area of the pixel electrode 5 can be made sufficiently wide without being affected by the occupied area of the digital memory element 100 and its wiring. Moreover, since such a structure does not require a backlight or the like, it has an excellent advantage which is extremely suitable as a portable liquid crystal display device in that a display with higher brightness can be realized with lower power consumption. .

In the present embodiment, in order to make the above effect of using the pixel electrode 5 as a reflective electrode more effective, a guest-host capable of performing light modulation without using a polarizing plate. Type liquid crystal was used as a liquid crystal composition. If guest-host type liquid crystal is used, by changing the dye mixed in the liquid crystal variously, in addition to black and white display,
A color liquid crystal can be realized without using a color filter. As described above, by using the guest-host type liquid crystal, a polarizing plate and a color filter, which are one of the main factors that cause a large light transmission loss and reduce the light utilization efficiency, are not required.

Next, the operation of the liquid crystal display device according to this embodiment will be described. This liquid crystal display device can selectively use a digital data image display mode suitable for still image display and an analog data display mode suitable for multi-gradation display of natural images and the like. According to the present invention, it is possible to dramatically reduce the power consumption in the digital data image display mode among these modes.

First, the operation in the digital data image display mode will be described in detail. First, the voltage of the X address signal line 4-n (n is a natural number indicating the row of the X address signal line) corresponding to the pixel to be written is raised to the high level. As a result, the first display control line 1-n of the pixel in the nth row corresponding to the X address signal line 4-n is connected to the first display control line 1-n.
The switch element 8 becomes conductive.

Then, a digital data signal is sent to the first display control line 1-n. In this state, the digital data signal from the first display control line 1-n is written in the digital memory element 100 composed of the NAND circuit 11 and the clocked inverter element 13. At this time, the display mode control line 15 is at the high level and the digital memory device 100 is in the active state.

However, in order to enable this writing, it is necessary to make the driving ability of the entire driving circuit system including the first switch element 8 and the digital data driver 19 larger than that of the clocked inverter element 13. is there. This is because, in the initial state, since the clocked inverter element 13 outputs the signal, the drive capacity of the entire drive circuit system needs to be larger than that of the clocked inverter element 13. In addition, this means that the clocked inverter element 14 of FIG.
The same can be said of the case.

The output of the digital memory element 100 is connected to the third switch element 10, and the input is connected to the second switch element 9. Either the second switch element 9 or the third switch element 10 is selectively turned on by the output of the digital memory element 100.

Second display control line 2-n, third display control line 3
, The white display reference voltage is supplied to one of them, and the black display reference voltage is supplied to the other, and the white display reference voltage or the black display reference voltage is supplied to the pixel electrode 5. 5 and 6 show examples of the white display reference voltage and the black display reference voltage. FIG. 5 is a VT (applied voltage-transmittance) characteristic diagram showing an example of optical characteristics of a normally white mode liquid crystal cell in the liquid crystal display device, and FIG.
FIG. 5 is a VT characteristic diagram showing an example of optical characteristics of a normally black mode liquid crystal cell in the liquid crystal display device.

In a general so-called dynamic drive type liquid crystal display device, the pixel voltage changes with time due to the leak current of the pixel switch or the liquid crystal cell itself, so that even if the data itself written in the pixel is the same. Rewriting was required every period (generally 1/60 second).

However, according to the present invention, the pixel voltage is the second
Since it becomes the same as the white or black display reference voltage supplied from the display control line 2-n or the third display control line 3 and does not change with time, it is not necessary to rewrite when the data itself does not change. Becomes Therefore, the X address signal line driver 18, the digital data driver 19,
Also, the analog data driver 20 is stopped, and a white display reference voltage is supplied to either one of the second display control line 2-n and the third display control line 3 and a black display reference voltage is supplied to the other display. It can be performed. The frame writing frequency can be about 60 Hz, which is a normal value, or can be further increased, so that the power consumption can be significantly reduced.

Next, the operation in the analog data image display mode will be described in detail. First, the voltage of the X address signal line 4-n (n is a natural number indicating the row of the X address signal line) corresponding to the pixel to be written is raised to the high level. As a result, the first switch element 8 connected to the first display control line of the pixel in the nth row corresponding to the X address signal line 4-n becomes conductive.

At this time, the display mode control line 15 is at the low level and the digital memory device 100 is in the inactive state. This is because the output of the NAND circuit 11 forming the digital memory element 100 that controls the on / off of the third switch element 10 is always at a high level, and thus the third switch element formed by the P-type MOS transistor. 10 is always off, and the input of the clocked inverter element 13 forming the digital memory element 100 is also always at the high level. Therefore, FIG.
This is because the output of the clocked inverter element 13 has high impedance (Hi-Z) as shown in (c). As a result, the digital memory device 100 stops the memory function (the memory device does not have the memory function).

That is, on / off of the second switch element 9 is controlled by the Y address signal supplied from the first display control line 1-n via the first switch element 8.

Then, the Y address signal is changed from the high level to the low level while the first switch element 8 is on. As a result, the second display control line 2-n and the pixel electrode 5 are brought into conduction.

Then, an analog data signal is sent to the second display control line 2-n. As a result, an analog data voltage is supplied to the pixel electrode 5, and charges are stored in Cs (auxiliary capacitance) provided in parallel with the capacitance of the liquid crystal cell 6. In the present embodiment, Cs is electrically provided between the pixel electrode 5 and the LO power supply line 17, but the present invention is not limited to this, and the Cs line is provided separately from the LO power supply line 17. May be provided.

After that, while the first switch element 8 is on, the voltage of the Y address signal is changed from low level to high level. As a result, the second display control line 2-n
Then, the pixel electrode 5 becomes non-conductive. Furthermore, after that, X
The voltage of the address signal line 4-n is changed from high level to low level.

By writing one pixel based on such an operation, the alignment state of the liquid crystal molecules is changed according to the voltage applied to the liquid crystal cell 6 to control the brightness and darkness of the pixel, and multi-gradation is performed. Analog data display is performed. At this time, since the third switch element 10 is always off, the voltage of the third display control line may be any voltage.

Next, a second embodiment relating to the case where the present invention is applied to a liquid crystal display device will be described, but a description overlapping with the first embodiment will be omitted.

FIG. 7 is an equivalent circuit diagram showing an outline of the circuit configuration of the liquid crystal display device. In FIG. 7, a plurality of first
Display control line 1-n, a plurality of second display control lines 2-n, third
The display control line 3 and the plurality of X address signal lines 4-n are
They are arranged in a matrix and substantially orthogonal to each other. Each lattice of this matrix corresponds to one pixel, and one pixel electrode 5 for forming a pixel is formed in this lattice. Note that the pixel electrode 5 itself is not shown in FIG. 7, and is represented as an upper electrode (terminal) in the drawing of each liquid crystal cell in an equivalent circuit.

The main part of the liquid crystal display device of this embodiment is, for each pixel in each grid, a plurality of X address signal lines 4-n arranged in a matrix so as to intersect each other and a plurality of first display. Control line 1-n, plural second display control lines 2-
n, the third display control line 3, the pixel electrode 5 provided for each matrix of the matrix, and the X address signal line 4-n.
A first switch element 8 whose on / off is controlled by
A digital memory device 101 which is controlled to be active or inactive by a display mode control line 15, and which holds digital data by a voltage supplied from the first display control line 1 via the first switch device 8 when active; The output of the digital memory element 101 controls the connection between the pixel electrode 5 and the second display control line 2-n or the third display control line 3, and the second and third switch elements 9 are provided for each grid. A switch element array substrate including the switch element array substrate, a counter substrate including a counter electrode having a counter electrode disposed opposite to the pixel electrode with a gap therebetween, and sandwiched between the switch element array substrate and the counter substrate. And a liquid crystal cell 6 formed of the formed liquid crystal layer.

The above digital memory device 101 is shown in FIG.
As shown in (a), it is composed of a NOR circuit 12 and a clocked inverter element 14. In the digital memory element 101, one input terminal of the NOR circuit 12 and the output terminal of the clocked inverter element 14 are connected to the gate of the second switch element 9. The output terminal of the NOR circuit 12 and the input terminal of the clocked inverter element 14 are connected to the third switch element 1 described above.
It is connected to the 0 gate. The other input terminal of the NOR circuit 12 and the clock input terminal of the clocked inverter element 14 are connected to the display mode control line 15.

The above clocked inverter element 14 is
As shown in FIG. 8B, two P-type MOS transistors 14a and 14b and one N-type MOS transistor 14c are connected in series in this order between the HI power supply and the LO power supply. There is. The gate of the P-type MOS transistor 14b and the gate of the N-type MOS transistor 14c are
It is connected to the gate of the third switch element 10 described above. In addition, the P-type MOS transistor 14b and the N-type MOS
The connection point of the transistor 14c is connected to the gate of the second switch element 9 described above. The gate of the N-type MOS transistor 14 a is connected to the display mode control line 15.

The P-type MOS transistor 14a becomes conductive when a low level signal is applied to its gate, and the above-mentioned digital memory element 101 becomes active, while it becomes non-conductive when a high level signal is applied to its gate. It becomes conductive and becomes high impedance (Hi-Z), and the digital memory element 101 becomes non-active (see FIG. 8).
(See (c)).

The counter electrode 7 is connected to a constant voltage power supply circuit (not shown) that outputs a constant voltage. Also, X
The address scan line driver 18, the digital data driver 19, and the analog data driver 20 are provided on the peripheral green part of the TFT array substrate with the same material as that used for each TFT and at least one of them. It is arranged using.

FIG. 9 is a plan view showing a specific circuit configuration of the liquid crystal display device according to the present embodiment, particularly in a pixel portion, and an outline of its cross-sectional structure taken along the line AA of FIG. 4 shows.

According to FIGS. 9 and 4, the P-Si (polycrystalline silicon) film 302 is used as an active layer on the glass substrate 301 which is an electrically insulating substrate, and the first switch element 8 is provided for each pixel. , Various TFTs 303 such as the NOR circuit 12 and the clocked inverter 14 which constitute the second switch element 9, the third switch element 10 and the digital memory element 101.
Are formed.

Next, the operation of the liquid crystal display device according to this embodiment will be described. First, the operation in the digital data image display mode will be described in detail.

First, the voltage of the X address signal line 4-n (n is a natural number indicating the row of the X address signal line) corresponding to the pixel to be written is raised to the high level. As a result, the first switch element 8 connected to the first display control line 1-n of the pixel in the nth row corresponding to the X address signal line 4-n becomes conductive.

Then, a digital data signal is sent to the first display control line 1-n. In this state, the digital data signal from the first display control line 1-n is written in the digital memory element 101 composed of the NOR circuit 12 and the clocked inverter element 14. At this time, the display mode control line 15 is at the low level and the digital memory device 10
1 is in the active state. However, in order to enable this writing, the drive capability of the entire drive circuit system including the first switch element 8 and the digital data driver 19 needs to be larger than the drive capability of the clocked inverter element 14. The reason for this is that the drive capability of the entire drive circuit system and the clocked inverter element 1 in the case of FIG.
It is the same as that relating to the driving ability of No. 3 above.

The output of the digital memory element 101 is connected to the third switch element 10, and the input of the digital memory element 101 is connected to the second switch element 9, respectively. Either the second switch element 9 or the third switch element 10 is selectively made conductive by the input / output of the digital memory element 101.

Second display control line 2-n, third display control line 3
, The white display reference voltage is supplied to one of them, and the black display reference voltage is supplied to the other, and the white display reference voltage or the black display reference voltage is supplied to the pixel electrode 5.

Next, the operation in the analog data image display mode will be described in detail. First, the voltage of the X address signal line 4-n (n is a natural number indicating the row of the X address signal line) corresponding to the pixel to be written is raised to the high level. As a result, the first switch element 8 connected to the first display control line of the pixel in the nth row corresponding to the X address signal line 4-n becomes conductive.

At this time, the display mode control line 15 is at the high level and the digital memory element 101 is in the inactive state. This is because the output of the NOR circuit 12 forming the digital memory element 101 that controls the on / off of the third switch element 10 is always at the low level, and thus the third switch element formed by the N-type MOS transistor is used. 10 is always off, and the input of the clocked inverter element 14 constituting the digital memory element 101 is always at the low level as well. Therefore, as shown in FIG. 8, the output of the clocked inverter element 14 has a high impedance. Because it is. As a result, the digital memory element stops the memory function (it becomes a state without the memory function). That is, the second switch element 9 has the first
ON / OFF is controlled by the Y address signal supplied from the display control line 1-n via the first switch element 8.

Then, the Y address signal is changed from the low level to the high level while the first switch element 8 is on. As a result, the second display control line 2-n and the pixel electrode 5 are brought into conduction.

Then, an analog data signal is sent to the second display control line 2-n. As a result, an analog data voltage is supplied to the pixel electrode 5, and charges are stored in Cs (auxiliary capacitance) provided in parallel with the capacitance of the liquid crystal cell 6. In the present embodiment, Cs is electrically provided between the pixel electrode 5 and the HI power supply line 16, but the present invention is not limited to this, and the Cs line is provided separately from the HI power supply line 16. May be provided.

After that, while the first switch element 8 is on, the voltage of the Y address signal is changed from the high level to the low level. As a result, the second display control line 2-n and the pixel polar pole 5 are brought out of conduction. After that, the voltage of the X address signal line 4-n is changed from the high level to the low level.

By writing one pixel on the basis of such an operation, the alignment state of the liquid crystal molecules is changed according to the applied pressure of the liquid crystal to the liquid crystal cell 6, the brightness of the pixel is controlled, and multi-gradation is performed. Analog data is displayed. At this time, since the third switch element 10 is always off, the voltage of the third display control line may be any voltage.

In the first or second embodiment of the present invention as described above, an N-type MOS transistor is used as the first switch element 8, but a P-type MO transistor is used.
An S transistor may be used. Further, as the switch elements such as the first switch element 8 and the digital memory elements 100 and 101, elements which are circuit-equivalent to the above-mentioned switch elements may be used.

By the way, in a general so-called static drive type liquid crystal display device, since the digital memory element always functions as a memory, analog data such as a natural image cannot be displayed.

On the other hand, according to the present invention, the digital data display according to the memory storage contents by the digital memory elements 100 and 101 and the digital memory elements 100 and 101 are performed.
It is possible to properly use the analog data display in which 101 is made inactive.

Although the above-mentioned embodiments describe the liquid crystal display device of the reflection type structure, when the pixel size is relatively large and a sufficient pixel opening can be secured in the region excluding the circuit region in the pixel, By applying the present invention to a liquid crystal display device having a transmissive structure or a liquid crystal display device having a semi-transmissive structure, the same effect as that of the above-described embodiment can be obtained.

Further, in the above description, the liquid crystal display device is mentioned as an example, but the present invention is not limited to this, and can be applied to a display device such as an image device.

As described above, the display device of the present invention has a plurality of X address signal lines 4-n, a plurality of first display control lines 1-n, and a plurality of second display control lines 1-n which are arranged in a matrix so as to intersect each other. A display control line 2-n and a third display control line 3,
Pixel electrodes 5 arranged for each lattice of this matrix,
A first switch element 8 whose on / off is controlled by the X address signal line 4-n and an active or non-active control by a display mode control line 15, and when active, the first switch element 8 is used to control the on / off state. 1
A digital memory device 100 (10 that holds digital data according to the voltage supplied from the display control line 1-n)
1) and the output of the digital memory device 100 (101), the pixel electrode 5 and the second display control line 2-n.
Alternatively, a gap is held between the pixel electrode 5 and the switch element array substrate including the second switch element 9 and the third switch element 10 provided for each grid for controlling the connection with the third display control line 3. And a liquid crystal layer sandwiched between the switch element array substrate and the counter substrate.

The digital memory device 100 can be composed of a NAND circuit 11 and a clocked inverter device 13 which are cross-connected.

In this case, the digital memory device 100
When the clocked inverter element 13 is composed of a total of three transistors, a P-type MOS transistor 13a and N-type MOS transistors 13b and 13c, which are connected in series, It is preferable that the output becomes 0 or high impedance when the output becomes 1 and the input becomes 1.

NOR circuit 12 and clocked inverter element 14 in which the digital memory element 101 is cross-connected.
The configuration may be configured as follows.

In this case, the digital memory device 101
Is composed of a total of three transistors, a P-type transistor 14a and 14b and an N-type MOS transistor 14c, in which the clocked inverter element 14 constituting the above is connected in series. When the input of the clocked inverter element 14 is 0, the output is It is preferable that the configuration becomes 1 or high impedance (Hi-Z), and the output becomes 0 when the input is 1.

The digital memory device 100 (101)
Is active, the second display control line 2-n and the third display control line 2-n
It is preferable that the image display reference voltage supplied from the display control line 3 is supplied with a black display reference voltage and a white display reference voltage, and at least one of them is an AC voltage whose polarity is inverted every predetermined period.

The white display reference voltage supplied from the second display control line 2-n or the third display control line 3 in the normally white mode is preferably the same voltage as the voltage applied to the counter electrode. .

The black display reference voltage supplied from the second display control line 2-n or the third display control line 3 in the normally black mode is preferably the same voltage as the voltage applied to the counter electrode. .

At least a part of the pixel electrode 5 includes at least the digital memory element 100 (101) and the first, second and third switch elements 8, 9 and 1.
It is preferable that the pixel electrode is a reflective or semi-transmissive pixel electrode in which a film whose surface reflects light is formed on any of 0 through an electrically insulating layer.

In this case, since the structure is of a reflective type or a semi-transmissive type, it is possible to form a transistor or the like without restrictions on the area. That is, the digital memory device 100
Since the pixel electrode can be formed on the circuit such as (101), the area occupied by the pixel electrode can be reduced to the digital memory element 100 (10
It can be made sufficiently wide without being affected by the area occupied by 1) and its wiring. Moreover, since no backlight or the like is required, display with higher brightness can be realized with lower power consumption, which is extremely suitable as a portable display device.

The digital memory device 100 (101)
Further includes drive circuits 18, 19 and 20 for selectively supplying a voltage to the X address signal line and the first display control line, respectively, when the drive circuit 1 is inactive.
It is preferable that 8, 19, and 20 are integrally formed on the switch element array substrate using at least the same material as the switch element forming material.
In this case, a compact shape can be realized.

The gate-on driving force of the first switch element 8 connected to the X address signal line 4-n and the first display control line 1-n is set to G1, and the digital memory element 10 is set.
When the gate-on driving force of the clocked inverter element 13 (14) forming 0 (101) is G2, the magnitude relationship between the gate-on driving forces of the respective elements is G1.
> G2 is preferably set.

The switch elements 8 to 10 are preferably formed of thin film transistors. It is further preferable that each of the switch elements 8 to 10 is formed of a polycrystalline silicon thin film transistor. Further, each of the switch elements 8 to 10 is preferably formed at a process temperature of 600 ° C. or lower.

According to the above display device, the pixel has the digital memory element 100 (101), and the second display control line 2-n or the second display control line 2-n is selected depending on the stored content of the digital memory element 100 (101). 3 Display control line 3 and pixel electrode 5
Since it has the switch elements 9 and 10 for controlling the connection with, it becomes possible to use a constant voltage for a specific display. When displaying digital data images, it is possible to significantly reduce power consumption, especially when displaying still images.
A liquid crystal display device suitable for a portable information processing device can be provided.

Further, according to the present invention, since it has a function of stopping the memory function of the digital memory element 100 (101), the digital data image display mode which is a low power consumption mode and high quality analog data can be obtained. It is possible to provide a liquid crystal display device that can be used in different display modes. Such a structure adopts a reflection type cell structure, and the driving circuit is integrally formed, which is effective for downsizing.

[0128]

As described above, the display device of the present invention sends the first display reference voltage to the pixel in the digital data display mode and sends the analog data signal to the pixel in the analog data display mode. A first switch means for sending, a second switch means for sending a second display reference voltage to the pixel in the digital data display mode, and a digital data signal for storing the digital data signal in the digital data display mode. Alternatively, each pixel is provided with a digital memory element that has a high impedance in the analog data display mode while selectively conducting the second switch means.

According to the above invention, the digital data signal is stored in the digital memory element in the digital data display mode. The first or second switch means is selectively turned on by the digital memory element.

As a result, the first display reference voltage (eg, black display reference voltage) is supplied to the pixel via the first switch means, or the second display reference voltage (eg, white display reference voltage). Are supplied to the pixels via the second switch means. As a result, digital data display is performed according to the storage state of the digital memory element.

As described above, since the first and second display reference voltages are supplied to the pixels via the first and second switch means, the pixel voltage is the same as the above-mentioned first or second display reference voltage. And does not change over time. Therefore, when there is no change in the data itself, the rewriting operation that is required every predetermined period as in the past is not necessary.

The frame writing frequency can be a normal 60 Hz or a lower frequency, so that the power consumption can be greatly reduced. This makes it possible to significantly reduce power consumption particularly when displaying a still image, and to provide a display device suitable for a portable information processing device.

On the other hand, in the analog data display mode, the digital memory element has a high impedance,
Stop the memory function. Therefore, the digital data display according to the storage state of the digital memory element is not performed.

At this time, the analog data signal is the first
It is supplied to the pixel through the switch means. This allows
The alignment state of the liquid crystal molecules is changed according to the analog data signal supplied to the pixel to control the brightness and darkness of the pixel, thereby enabling multi-level analog data display.

In the conventional static drive type liquid crystal display device and the like, analog data cannot be displayed because the digital memory element always fulfills the memory function. However, according to the above invention, the above is as follows. In addition, both the digital data display according to the storage state of the digital memory element and the analog data display such as a natural image performed by stopping the memory function of the digital memory element can be performed by one display device.

Since the above invention has the function of stopping the memory function of the digital memory element as described above, it has a digital data display mode which is a low power consumption mode and a high quality analog data display mode. It also has the effect that it is possible to use differently. Such a structure is effective for downsizing by adopting a reflective cell structure and integrally forming a drive circuit.

The digital memory element comprises a NAND circuit and a clocked inverter element. In the analog data display mode, the clocked inverter element has a high impedance and stops the memory function of the digital memory element. be able to.

In this case, the clocked inverter element has a first P-type MOS transistor, a first N-type MOS transistor, and a second N-type MOS transistor connected in series between the power supplies in this order. When the gate of the first N-type MOS transistor is connected to the input, the connection point of the first P-type MOS transistor and the first N-type MOS transistor is output, and when the second N-type MOS transistor is non-conductive, the clock It is preferable that the inverter element has high impedance.

As described above, the memory function of the digital memory element can be stopped in the analog data display mode with a simple structure.

Also, the digital memory device is a NOR
The clocked inverter element may include a circuit and a clocked inverter element, and in the analog data display mode, the clocked inverter element has a high impedance and stops the memory function of the digital memory element.

In this case, the clocked inverter element includes a first P-type MOS transistor, a second P-type MOS transistor, and a first N-type MOS transistor, which are connected in series between the power sources in this order. The gate of the first N-type MOS transistor is connected to the input, the connection point of the second P-type MOS transistor and the first N-type MOS transistor is output, and when the first P-type MOS transistor is non-conductive, the clock It is preferable that the inverter element has a high impedance.

One of the first and second display reference voltages is a black display reference voltage, the other is a white display reference voltage, and at least one is an AC voltage whose polarity is inverted every predetermined period. Preferably there is. in this case,
The effect that the deterioration of the display characteristics of the display device can be surely avoided is also achieved.

When the display device is a liquid crystal display device,
The white display reference voltage supplied in the normally white mode is preferably the same voltage as the voltage applied to the counter electrode of the pixel.

When the display device is a liquid crystal display device,
The black display reference voltage supplied in the normally black mode is preferably the same voltage as the voltage applied to the counter electrode of the pixel.

In these cases, since the same voltage as the counter electrode of the pixel can be used as the white display reference voltage or the black display reference voltage, it is not necessary to separately prepare a power source, and the structure can be simplified. Play.

At least a part of the pixel electrode is formed with a film whose surface reflects light through an electrically insulating layer on at least one of the digital memory element, the first switch means and the second switch means. It is preferable that the pixel electrode is a reflective or semi-transmissive pixel electrode. In this case, since the pixel electrode can be formed on the circuit of the digital memory element or the like, the area occupied by the pixel electrode can be made sufficiently wide without being affected by the area occupied by the digital memory element and its wiring, and the back electrode Since no light or the like is required, display with higher brightness can be realized with lower power consumption, and it is also extremely advantageous as a portable display device.

A plurality of drive circuits for supplying various drive signals to the pixels are provided, and these drive circuits are provided on the switch element array substrate provided with the first and second switch means. It is preferably formed of the same material as at least one of the two switch means. In this case, it is possible to achieve the effect that the size can be surely reduced.

A plurality of drive circuits for supplying various drive signals to the pixel are provided, and the drive capability of these drive circuits as a whole is preferably larger than the drive capability of the clocked inverter element. In this case, output is performed from the clocked inverter in the initial state, but since a signal is supplied with a driving force larger than that, there is an effect that a reliable operation can be secured.

It is preferable that each of the switch means is formed of a thin film transistor. Further, it is more preferable that each of the switch means is formed of a polycrystalline silicon thin film transistor. In this case, it is possible to reduce the thickness and the weight of the device.

The switch means are preferably formed at a process temperature of 600 ° C. or lower.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing an outline of a configuration according to a first embodiment when a display device of the present invention is applied to a liquid crystal display device.

2A is a circuit diagram showing a configuration example of a digital memory element of the liquid crystal display device, FIG. 2B is a circuit diagram showing a configuration example of a clocked inverter in the digital memory element, and FIG. ) It is a truth table of a clocked inverter.

FIG. 3 is a plan view showing a specific circuit configuration of a pixel portion of the liquid crystal display device.

4 is a cross-sectional view taken along the line AA of FIG.

FIG. 5 is a VT characteristic diagram showing an example of optical characteristics of a normally white mode liquid crystal cell in the liquid crystal display device.

FIG. 6 is a VT characteristic diagram showing an example of optical characteristics of a normally black mode liquid crystal cell in the liquid crystal display device.

FIG. 7 is a circuit diagram showing a configuration of a second embodiment when the present invention is applied to a liquid crystal display device.

8A is a circuit diagram showing a configuration example of a digital memory element of the liquid crystal display device shown in FIG. 7, and FIG. 8B is a circuit diagram showing a configuration example of a clocked inverter in the digital memory element. , (C) is a truth table of a clocked inverter.

FIG. 9 is a plan view showing a specific circuit structure of a pixel portion in the second embodiment of the liquid crystal display device according to the present invention.

FIG. 10 is a circuit diagram showing an outline of a circuit configuration of a general conventional liquid crystal display device.

FIG. 11 is a circuit diagram showing an example of a circuit configuration of a conventional static type liquid crystal display device.

FIG. 12 is a circuit diagram showing a circuit configuration of another conventional static type liquid crystal display device.

[Explanation of symbols]

1-n 1st display control line 2-n Second display control line 3rd display control line 5 pixel electrodes 6 Liquid crystal cell 7 Counter electrode 8 First switch element 9 Second switch element (first switch means) 10 Third switch element (second switch means) 11 NAND circuit 12 NOR circuit 13 Clocked inverter element 14 Clocked inverter element 15 Display mode control line 100 digital memory device 101 Digital memory device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 611 G09G 3/20 611A 624 624B (72) Inventor ▲ Takahashi Keiji Osaka Prefecture Osaka City Abeno 22-22, Nagaike-cho, Chuap Co., Ltd. (72) Kazuhiro Maeda Kazuhiro Maeda 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture In-house (72) 22nd, Nagaike-cho, Abeno-ku, Osaka, Osaka No. 22 Inside Sharp Co., Ltd. (72) Inventor, Lee Soicheng 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture F-term inside Sharp Co., Ltd. (reference) 2H092 GA17 GA29 HA05 JA24 JB07 KA04 KA12 KA18 KB04 KB25 NA07 PA06 RA10 2H093 NA11 NA16 NC11 NC34 NC49 NC71 ND39 NG20 5C006 BB16 BB28 BC06 BC11 BC20 BF04 BF26 BF27 BF34 EB05 FA47 5C080 AA10 BB05 DD26 FF11 GG12 JJ02 J J03 JJ05 JJ06 KK07 KK47

Claims (14)

[Claims] 1. A first switch means for sending a first display reference voltage to a pixel in the digital data display mode and an analog data signal to the pixel in the analog data display mode; A second switch means for sending a second display reference voltage to the pixel, and a digital data signal stored in the digital data display mode, and the first or second switch means is selectively turned on. , A display device provided with a digital memory element that becomes high impedance in each pixel in the analog data display mode. 2. The digital memory element comprises a NAND circuit and a clocked inverter element, and in the analog data display mode, the clocked inverter element has a high impedance, so that the memory function of the digital memory element is maintained. The display device according to claim 1, wherein the display device is stopped. 3. The clocked inverter element is a first P
Type MOS transistor, first N-type MOS transistor,
And a second N-type MOS transistor are connected in series between the power supplies in this order, and the first P-type MOS transistor and the gate of the first N-type MOS transistor are connected as an input, and the first P-type MOS transistor and the first N-type M transistor are connected.
3. The display device according to claim 2, wherein the clocked inverter element has a high impedance when the connection point of the OS transistor is an output and the second N-type MOS transistor is non-conductive. 4. The digital memory element comprises a NOR circuit and a clocked inverter element, and in the analog data display mode, the clocked inverter element has a high impedance, and the memory function of the digital memory element is maintained. The display device according to claim 1, wherein the display device is stopped. 5. The clocked inverter element is a first P
Type MOS transistor, second P-type MOS transistor,
And a first N-type MOS transistor are connected in series between the power sources in this order, and the gates of the second P-type MOS transistor and the first N-type MOS transistor are connected to the input, and the second P-type MOS transistor and the first N-type M transistor are input.
The display device according to claim 4, wherein the connection point of the OS transistor is an output, and the clocked inverter element has a high impedance when the first P-type MOS transistor is non-conductive. 6. One of the first and second display reference voltages is a black display reference voltage, the other is a white display reference voltage, and at least one of them is an alternating current whose polarity is inverted every predetermined period. It is a voltage, The claim 1 characterized by the above-mentioned.
5. The display device according to any one of 5 above. 7. The display device is a liquid crystal display device, and the white display reference voltage supplied in a normally white mode is the same voltage as a voltage applied to a counter electrode of the pixel. The display device according to claim 6. 8. The display device is a liquid crystal display device, and the black display reference voltage supplied in a normally black mode is the same voltage as a voltage applied to a counter electrode of the pixel. The display device according to claim 6. 9. A film in which at least a part of the pixel electrode has a surface that reflects light through an electrically insulating layer on at least one of the digital memory element, the first switch means, and the second switch means. 2. A reflective or semi-transmissive pixel electrode, in which is formed.
The display device according to claim 1. 10. A plurality of drive circuits for supplying various drive signals to the pixels are provided, and these drive circuits are provided on the switch element array substrate provided with the first and second switch means. The display device according to claim 1, wherein the display device is formed of the same material as at least one of the second switch means and the second switch means. 11. A drive circuit comprising a plurality of drive circuits for supplying various drive signals to the pixels, wherein the drive capability of the drive circuits as a whole is larger than that of the clocked inverter element. The display device according to any one of 2 to 10. 12. A display device according to claim 1, wherein each of the switch means is formed of a thin film transistor. 13. A display device according to claim 1, wherein each of the switch means is formed of a polycrystalline silicon thin film transistor. 14. The display device according to claim 1, wherein each of the switch means is formed at a process temperature of 600 ° C. or lower.