JP2003168798A - Mos field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an MOS field-effect transistor has gate capacitance structurally, the gate capacitance is increased as the channel area is increased and the gate oxide film is thinned, resulting in a limit due to the gate capacitance for improving high frequency operation characteristics. <P>SOLUTION: A p-type base region 34 is formed on a surface layer of an n<SP>-</SP>type drain layer 33, and an n-type source region 35 is formed on a surface layer of the base region 34. An n-type channel region 36 is formed on a surface layer of the base region 34 between the source region 35 and the drain layer 33 so as to realize a normally-on type. A gate electrode 39 is formed striding over a part between channel regions 36 of the respective adjacent unit cells B via a gate oxide film 37 constituted of a thin silicon oxide film on an n-type channel region 36 and via a thick silicon oxide film 38 on the drain layer 33. The gate electrode 39 is so constituted that dimension in a channel length direction is shorter than the channel length, on the channel region 36. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor, and more particularly to a normally-on vertical MOS transistor.
Field effect transistor.

[0002]

2. Description of the Related Art A conventional normally-on vertical MOS field effect transistor will be described with reference to FIG. In the figure, A is a cell portion as an element operating region inside the chip, and a large number of unit cells B having a transistor function are repeatedly arranged in the chip plane direction in the cell portion A, and these unit cells B are connected in parallel. Has been done. The cell portion A is a high-concentration n-type n ⁺ type in which the drain electrode 1 connected to the D terminal is provided in electrical contact with the back surface.
It is formed on the surface layer of the n ⁻ type drain layer 3 which is a low concentration n type and is formed on the surface of the type semiconductor substrate 2 by epitaxial growth and on the drain layer 3.

Explaining the unit cell B, a p-type base region 4 is formed on the surface layer of the drain layer 3, and an n-type source region 5 is formed on the surface layer of the base region 4. In the surface layer between the drain layer 3 and the source region 5 of the base region 4, an n-type channel region 6 is formed in order to have a normally-on type. A gate oxide film 7 made of a thin silicon oxide film and a drain layer are formed on the source region 5 and the channel region 6 so as to extend over a part of the source region 5 formed in the base region 4 of each adjacent unit cell B. A gate electrode 9 made of polycrystalline silicon and connected to the G terminal is formed on the upper surface 3 via a thick silicon oxide film 8. Then, a source electrode 11 is formed which is insulated from the gate electrode 9 by the interlayer insulating film 10 and electrically contacts the base region 4 and the source region 5 in common and is connected to the S terminal.

The operation of the MOS field effect transistor having the above structure will be described. When a positive voltage is applied between the D terminal and the S terminal and no voltage is applied between the G terminal and the S terminal, no voltage is applied to the gate electrode 9 and carriers in the channel region 6 remain unchanged. The drain field 3 and the source region 5 are electrically connected, and the MOS field effect transistor is on. When a negative voltage is applied between the G terminal and the S terminal while a positive voltage is applied between the D terminal and the S terminal, the negative voltage is applied to the gate electrode 9 and carriers are expelled from the channel region 6. The drain layer 3 and the source region 5 are brought out of conduction, and the MOS field effect transistor is turned off.

Next, a method of manufacturing the above-mentioned MOS field effect transistor will be described with reference to FIGS. 5 (a) to 5 (c) and 6 (d).
This will be described with reference to (f). (A) In the first step, after completion of this step, as shown in FIG. 5A, n ⁻ containing phosphorus or arsenic, which is an n-type impurity, at a low concentration on the surface of the n ⁺ -type semiconductor substrate 2. The type drain layer 3 is epitaxially grown, and a silicon oxide film 21 having a film thickness of 12000Å, for example, is formed on the surface thereof by a thermal oxidation method. Then, the silicon oxide film 21 on the region where the base region 4 of each unit cell B is to be formed is removed by photolithography and etching, and the patterned silicon oxide film 21 is used as a mask to form a p-type impurity. Ion implantation and thermal diffusion of boron are performed to form the base region 4. (B) In the second step, after the completion of this step, as shown in FIG. 5B, after the completion of the first step, the silicon oxide film 21 and the resist pattern 22 formed by the photolithography method are used as a mask to form the base region. The source region 5 is formed by ion-implanting and thermally diffusing arsenic into the region of the surface layer where the source region 5 is to be formed. (C) In the third step, after the completion of this step, as shown in FIG. 5C, after the second step is completed, the resist pattern 22 is removed, and then each unit cell is formed by photolithography and etching. The silicon oxide film 21 on the region where the channel region 6 of B is to be formed is removed, and the newly patterned silicon oxide film 8 and the resist pattern 23 formed by photolithography are used as a mask to ion-implant and thermally diffuse arsenic. Then, a channel region 6 is formed in the surface layer between the drain layer 3 and the source region 5 of the base region 4. (D) In the fourth step, after the completion of this step, as shown in FIG. 6D, after the completion of the third step, the resist pattern 23 is removed, and then a gate made of a thin silicon oxide film is formed by a thermal oxidation method. An oxide film 7 is formed, and then LP is applied to the wafer surface.
A polysilicon film 24 is deposited by the CVD method. (E) In the fifth step, after the completion of this step, as shown in FIG. 6E, the polysilicon film 24 and the gate oxide film 7 are selectively removed by the photolithography method and the etching method after the completion of the fourth step. The gate oxide film 7 is formed on the source region 5 and the channel region 6, and the gate region is thick on the drain region 3 so as to extend over a part of the source region 5 formed in the base region 4 of each adjacent unit cell B. A gate electrode 9 is formed via the silicon oxide film 8. After that, the interlayer insulating film 10 is deposited on the wafer by the CVD method. (F) In the sixth step, after the completion of this step, as shown in FIG. 6 (f), after the completion of the fifth step, the interlayer insulating film 10 is selectively removed by photolithography and etching to form the source region. 5 and the surface of the base region 4 are exposed, and then an aluminum film is deposited on the wafer by vacuum deposition, and the aluminum film is selectively removed by the photolithography method and the etching method to form the source region 5
And the source electrode 11 which makes electrical contact with the base region 4 is formed. Then, metal is deposited on the back surface of the semiconductor substrate 2 to form the drain electrode 1.

[0006]

By the way, the MOS field effect transistor structurally has a gate capacitance. The capacitance increases as the channel area increases and the gate oxide film becomes thinner. Since the high frequency operation is hindered, there is a limit in improving the high frequency operation. In the above-mentioned conventional MOS field effect transistor, the gate electrode 9 also overlaps the channel region 6 and a part of the source region 5 via the gate oxide film 7, which also increases the gate capacitance. .
In view of the above problems, it is an object of the present invention to provide a MOS field effect transistor having a reduced gate capacitance.

[0007]

A MOS field effect transistor according to the present invention includes a drain layer of one conductivity type formed on a semiconductor substrate, a plurality of base regions of another conductivity type formed on the drain layer, and a drain region formed on the base region. In a MOS field effect transistor having a conductive type source region, a one conductive type channel region formed between a drain region and a source region of a base region, and a gate electrode formed on the channel region via a gate oxide film, a gate electrode Are not overlapped with the source region, and the dimension of the gate electrode in the channel length direction on the channel region is shorter than the channel length. In the above MOS field effect transistor, the dimension of the gate electrode in the channel length direction on the channel region is in the range of 50 to 70% of the channel length.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A normally-on vertical MOS field effect transistor according to an embodiment of the present invention will be described below with reference to FIG. In the figure, A is a cell portion as an element operating region inside the chip, and a large number of unit cells B having a transistor function are repeatedly arranged in the chip plane direction in the cell portion A, and these unit cells B are connected in parallel. Has been done. The cell portion A has a low-concentration one-conductivity type formed by epitaxial growth on the surface of an n ⁺ -type semiconductor substrate 32, which is a high-concentration one-conductivity type provided with a drain electrode 31 connected to the D terminal in electrical contact with the back surface. And the surface layer of the n ⁻ -type drain layer 33 and the drain layer 33
Is configured on.

Explaining the unit cell B, a p-type base region 34 is formed on the surface layer of the drain layer 33, and an n-type source region 35 is formed on the surface layer of the base region 34. Source region 35 and drain layer 3 of the base region 34
An n-type channel region 36 is formed in the surface layer between the layers 3 in order to be a normally-on type. A gate oxide film 37 made of a thin silicon oxide film is formed on the n-type channel region 36 and a thick silicon oxide film 3 is formed on the drain layer 33 so as to extend across the channel regions 36 of adjacent unit cells B.
And a gate electrode 39 made of polycrystalline silicon and connected to the G terminal. On the channel region 36, the gate electrode 39 is configured such that the dimension in the channel length direction is shorter than the channel length. Then, the base region 34 and the source region 35 are insulated from the gate electrode 39 by the interlayer insulating film 40 and are in electrical contact with each other in common.
A source electrode 41 connected to the terminal is formed.

The operation of the MOS field effect transistor having the above structure will be described. When a positive voltage is applied between the D terminal and the S terminal and no voltage is applied between the G terminal and the S terminal, no voltage is applied to the gate electrode 39 and carriers in the channel region 36 remain unchanged. , Drain layer 3
3 and the source region 35 are electrically connected, and the MOS field effect transistor is on. The on-resistance at this time does not increase due to the configuration of the gate electrode 39, and can be the same as that of the conventional gate electrode 9. When a negative voltage is applied between the G terminal and the S terminal while a positive voltage is applied between the D terminal and the S terminal,
Since a negative voltage is applied to the gate electrode 39 and the carriers are expelled from the channel region 36 immediately below the gate electrode 39, even if the carriers are not expelled from the entire channel region 36, the carriers are expelled from a part of the channel region 36. Only then, the drain layer 33 and the source region 35 become non-conductive, and the MOS field effect transistor is turned off. Note that the gate capacitance can be reduced as the dimension of the gate electrode 39 on the channel region 36 in the channel length direction is shorter. Can no longer be turned off,
It is necessary to set in the proper range, and the channel length is 50 to 7
0% is an appropriate range, and at this time, the gate capacitance is 20 to
It can be reduced by 30%.

Next, a method for manufacturing the above-mentioned MOS field effect transistor will be described with reference to FIGS. 2 (a) to 2 (c) and 3 (d).
This will be described with reference to (f). (A) In the first step, after the completion of this step, as shown in FIG. 2A, n ⁻ containing phosphorus or arsenic, which is an n-type impurity, at a low concentration on the surface of the n ⁺ -type semiconductor substrate 32. Type drain layer 33 is epitaxially grown, and a silicon oxide film 5 having a film thickness of, for example, 12000Å is formed on the surface thereof by a thermal oxidation method.
1 is formed. Then, the silicon oxide film 51 on the region where the base region 34 of each unit cell B is to be formed is removed by photolithography and etching, and the patterned silicon oxide film 51 is used as a mask to form a p-type impurity. Ion implantation and thermal diffusion of boron are performed to form the base region 34. (B) In the second step, after the completion of this step, as shown in FIG. 2B, after the completion of the first step, the silicon oxide film 51 and the resist pattern 52 formed by the photolithography method are used as a mask to form the base region. A source region 35 is formed by ion-implanting and thermally diffusing arsenic into a region of the surface layer where the source region 35 is to be formed. (C) In the third step, after the completion of this step, as shown in FIG. 2C, after the completion of the second step, the resist pattern 52 is removed, and then each unit cell is formed by photolithography and etching. The silicon oxide film 51 on the region where the channel region 36 of B is to be formed is removed, and the newly patterned silicon oxide film 38 and the resist pattern 53 formed by the photolithography method are used as a mask to ion-implant and thermally diffuse arsenic. The drain layer 33 of the base region 34
A channel region 36 is formed in the surface layer between the source region 35 and the source region 35. (D) In the fourth step, after the completion of this step, as shown in FIG. 3D, after the third step is completed, the resist pattern 53 is removed, and then a gate made of a thin silicon oxide film is formed by a thermal oxidation method. An oxide film 37 is formed, and then L is formed on the wafer surface.
A polysilicon film 54 is deposited by the PCVD method. (E) In the fifth step, after the completion of this step, as shown in FIG. 3 (e), after the completion of the fourth step, the polysilicon film 54 and the gate oxide film 37 are selectively removed by photolithography and etching. The channel regions 36 of the unit cells B adjacent to each other.
A gate electrode 39 is formed via a gate oxide film 37 on the top and a thick silicon oxide film 38 on the drain layer 33. At this time, the gate electrode 39 is formed on the channel region 36 so that the dimension in the channel length direction is shorter than the channel length. After that, the interlayer insulating film 40 is deposited on the wafer by the CVD method. (F) In the sixth step, after the completion of this step, as shown in FIG. 3 (f), after the completion of the fifth step, the interlayer insulating film 40 is selectively removed by photolithography and etching to form the source region. 35 and the surface of the base region 34 are exposed, and then an aluminum film is deposited on the wafer by vacuum vapor deposition, and the aluminum film is selectively removed by the photolithography method and the etching method to form the source region 35 and the base region 34. A source electrode 41 is formed in electrical contact with the source electrode 41. Then, metal is deposited on the back surface of the semiconductor substrate 32 to form the drain electrode 31.

As described above, the gate electrode 39 is not overlapped on the source region 35, and the dimension of the gate electrode 39 in the channel length direction on the channel region 36 is determined by the off-operation of the MOS field effect transistor. At this time, since the structure is shorter than the channel length so that the drain layer 33 and the source region 35 are not electrically connected, the gate capacitance can be reduced and the high frequency operation can be improved.

In the above embodiment, the n-type as one conductivity type and the p-type as another conductivity type have been described, but the p-type as one conductivity type and the n-type as another conductivity type may be used.

[0014]

According to the present invention, since the gate electrode does not overlap the source region and the dimension of the gate electrode in the channel length direction on the channel region is shorter than the channel length, the MOS electric field effect is obtained. The gate capacitance of the transistor can be reduced without increasing the on resistance.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a vertical MOS field effect transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a main portion showing the manufacturing process of the vertical MOS field effect transistor shown in FIG.

FIG. 3 is a cross-sectional view of main parts showing a step following FIG.

FIG. 4 is a sectional view of a main part of a conventional vertical MOS field effect transistor.

5 is a cross-sectional view of main parts showing a manufacturing process of the vertical MOS field effect transistor shown in FIG.

FIG. 6 is a sectional view of a main portion showing a step following the step of FIG.

[Explanation of symbols]

32 n ⁺ type semiconductor substrate 33 n ⁻ type drain layer 34 p type base region 35 n type source region 36 n type channel region 37 gate oxide film 38 gate electrode

Claims (2)

[Claims] 1. A one conductivity type drain layer formed on a semiconductor substrate, a plurality of other conductivity type base regions formed on the drain layer, one conductivity type source region formed on the base region, and a drain layer and a source of the base region. In a MOS field effect transistor having a one conductivity type channel region formed between regions and a gate electrode formed on the channel region via a gate oxide film, the gate electrode does not overlap the source region and the gate A MOS field effect transistor, wherein a dimension of an electrode on a channel region in a channel length direction is shorter than a channel length. 2. The MOS field effect transistor according to claim 1, wherein the dimension of the gate electrode in the channel length direction on the channel region is in the range of 50 to 70% of the channel length.