JP2003167558A5 - - Google Patents

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JP2003167558A5
JP2003167558A5 JP2001366774A JP2001366774A JP2003167558A5 JP 2003167558 A5 JP2003167558 A5 JP 2003167558A5 JP 2001366774 A JP2001366774 A JP 2001366774A JP 2001366774 A JP2001366774 A JP 2001366774A JP 2003167558 A5 JP2003167558 A5 JP 2003167558A5
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image data
processing circuit
display device
circuit
display
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JP2001366774A
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JP3913534B2 (en
JP2003167558A (en
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Priority claimed from JP2001366774A external-priority patent/JP3913534B2/en
Priority to JP2001366774A priority Critical patent/JP3913534B2/en
Priority to US10/299,796 priority patent/US7196709B2/en
Priority to KR1020020073010A priority patent/KR100916248B1/en
Priority to TW091134518A priority patent/TWI251190B/en
Priority to CNB021548234A priority patent/CN100367183C/en
Publication of JP2003167558A publication Critical patent/JP2003167558A/en
Publication of JP2003167558A5 publication Critical patent/JP2003167558A5/ja
Priority to US11/687,449 priority patent/US7791610B2/en
Publication of JP3913534B2 publication Critical patent/JP3913534B2/en
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Claims (18)

第１の記憶回路と、第２の記憶回路と、演算処理回路と、表示処理回路と、を有する画素を複数有する表示装置であって、前記第１の記憶回路は、第１の画像データを記憶し前記演算処理回路へ出力し、前記第２の記憶回路は、第２の画像データを記憶し前記演算処理回路へ出力し、前記演算処理回路は、前記第２の画像データが既定の画像データと一致する場合は前記第１の画像データを前記表示処理回路へ出力し、前記第２の画像データが前記既定の画像データと一致しない場合は前記第２の画像データを前記表示処理回路へ出力し、前記表示処理回路は、前記演算処理回路から出力された前記第１の画像データ又は前記第２の画像データから映像信号を形成することを特徴とする表示装置。A display device including a plurality of pixels each including a first storage circuit, a second storage circuit, an arithmetic processing circuit, and a display processing circuit, wherein the first storage circuit stores first image data The second storage circuit stores the second image data and outputs the second image data to the arithmetic processing circuit, and the arithmetic processing circuit stores the second image data as a predetermined image. When the data matches the data, the first image data is output to the display processing circuit. When the second image data does not match the predetermined image data, the second image data is output to the display processing circuit. The display processing circuit outputs the video signal from the first image data or the second image data output from the arithmetic processing circuit. 第１の記憶回路と、第２の記憶回路と、演算処理回路と、表示処理回路と、を有する画素を複数有する表示装置であって、前記第１の記憶回路は、第１の画像データを記憶し前記演算処理回路へ出力し、前記第２の記憶回路は、第２の画像データを記憶し前記演算処理回路へ出力し、前記演算処理回路は、前記第２の画像データが既定の画像データと一致する場合は前記第１の画像データを前記表示処理回路へ出力し、前記第２の画像データが前記既定の画像データと一致しない場合は前記第２の画像データを前記表示処理回路へ出力し、前記表示処理回路は、前記演算処理回路から出力された前記第１の画像データ又は前記第２の画像データから映像信号を形成し、前記第１の記憶回路は、１フレーム分の前記第１の画像データを格納する手段を有し、前記第２の記憶回路は、１フレーム分の前記第２の画像データを格納する手段を有することを特徴とする表示装置。A display device including a plurality of pixels each including a first storage circuit, a second storage circuit, an arithmetic processing circuit, and a display processing circuit, wherein the first storage circuit stores first image data The second storage circuit stores the second image data and outputs the second image data to the arithmetic processing circuit, and the arithmetic processing circuit stores the second image data as a predetermined image. When the data matches the data, the first image data is output to the display processing circuit. When the second image data does not match the predetermined image data, the second image data is output to the display processing circuit. And the display processing circuit forms a video signal from the first image data or the second image data output from the arithmetic processing circuit, and the first storage circuit includes the one-frame worth of the frame. storing the first image data Has a step, the second storage circuit, display device characterized by having a means for storing the second image data for one frame. 第１の記憶回路と、第２の記憶回路と、演算処理回路と、表示処理回路と、を有する画素を複数有する表示装置であって、前記第１の記憶回路は、第１の画像データを記憶し前記演算処理回路へ出力し、前記第２の記憶回路は、第２の画像データを記憶し前記演算処理回路へ出力し、前記演算処理回路は、前記第２の画像データが既定の画像データと一致する場合は前記第１の画像データを前記表示処理回路へ出力し、前記第２の画像データが前記既定の画像データと一致しない場合は前記第２の画像データを前記表示処理回路へ出力し、前記表示処理回路は、前記演算処理回路から出力された前記第１の画像データ又は前記第２の画像データからＤ／Ａ変換により映像信号を形成することを特徴とする表示装置。A display device including a plurality of pixels each including a first storage circuit, a second storage circuit, an arithmetic processing circuit, and a display processing circuit, wherein the first storage circuit stores first image data The second storage circuit stores the second image data and outputs the second image data to the arithmetic processing circuit, and the arithmetic processing circuit stores the second image data as a predetermined image. When the data matches the data, the first image data is output to the display processing circuit. When the second image data does not match the predetermined image data, the second image data is output to the display processing circuit. And a display processing circuit that forms a video signal by D / A conversion from the first image data or the second image data output from the arithmetic processing circuit. 第１の記憶回路と、第２の記憶回路と、演算処理回路と、表示処理回路と、を有する画素を複数有する表示装置であって、前記第１の記憶回路は、第１の画像データを記憶し前記演算処理回路へ出力し、前記第２の記憶回路は、第２の画像データを記憶し前記演算処理回路へ出力し、前記演算処理回路は、前記第２の画像データが既定の画像データと一致する場合は前記第１の画像データを前記表示処理回路へ出力し、前記第２の画像データが前記既定の画像データと一致しない場合は前記第２の画像データを前記表示処理回路へ出力し、前記表示処理回路は、前記演算処理回路から出力された前記第１の画像データ又は前記第２の画像データからＤ／Ａ変換により映像信号を形成し、前記第１の記憶回路は、１フレーム分の前記第１の画像データを格納する手段を有し、前記第２の記憶回路は、１フレーム分の前記第２の画像データを格納する手段を有することを特徴とする表示装置。A display device including a plurality of pixels each including a first storage circuit, a second storage circuit, an arithmetic processing circuit, and a display processing circuit, wherein the first storage circuit stores first image data The second storage circuit stores the second image data and outputs the second image data to the arithmetic processing circuit, and the arithmetic processing circuit stores the second image data as a predetermined image. When the data matches the data, the first image data is output to the display processing circuit. When the second image data does not match the predetermined image data, the second image data is output to the display processing circuit. The display processing circuit forms a video signal by D / A conversion from the first image data or the second image data output from the arithmetic processing circuit, and the first storage circuit one frame of said first image And means for storing a over data, the second storage circuit, display device characterized by having a means for storing the second image data for one frame. 請求項１乃至４のいずれか一項に記載の表示装置において、前記第１の画像データまたは前記第２の画像データの少なくとも一方は１ビットの画像データであることを特徴とする表示装置。5. The display device according to claim 1 , wherein at least one of the first image data and the second image data is 1-bit image data. 6. 請求項１乃至５のいずれか一項に記載の表示装置において、前記第１の画像データまたは前記第２の画像データの少なくとも一方は２ビット以上の画像データであることを特徴とする表示装置。6. The display device according to claim 1 , wherein at least one of the first image data and the second image data is image data of 2 bits or more. 請求項１乃至６のいずれか一項に記載の表示装置において、前記映像信号に従って、画素の階調を変化させる手段を有することを特徴とする表示装置。7. The display device according to claim 1, further comprising means for changing a gradation of a pixel in accordance with the video signal. 請求項１乃至７のいずれか一項に記載の表示装置において、前記記憶回路をビット毎に順次駆動する手段を有することを特徴とする表示装置。8. The display device according to claim 1, further comprising means for sequentially driving the memory circuit for each bit. 請求項１乃至８のいずれか一項に記載の表示装置において、前記記憶回路に前記画像データをビット毎に順次入力する手段を有することを特徴とする表示装置。9. The display device according to claim 1, further comprising means for sequentially inputting the image data bit by bit into the storage circuit. 請求項１乃至９のいずれか一項に記載の表示装置において、前記記憶回路はスタティック型メモリ（ＳＲＡＭ）から構成されることを特徴とする表示装置。10. The display device according to claim 1, wherein the storage circuit includes a static memory (SRAM). 11. 請求項１乃至請求項９のいずれか一項に記載の表示装置において、前記記憶回路はダイナミック型メモリ（ＤＲＡＭ）から構成されることを特徴とする表示装置。10. The display device according to claim 1, wherein the memory circuit includes a dynamic memory (DRAM). 11. 請求項１乃至１１のいずれか一項に記載の表示装置において、前記記憶回路と、前記演算処理回路と、前記表示処理回路とは、単結晶半導体基板、石英基板、ガラス基板、プラスチック基板、ステンレス基板、ＳＯＩ基板のいずれか一つの基板上に形成した半導体薄膜を活性層とする薄膜トランジスタにより構成されていることを特徴とする表示装置。12. The display device according to claim 1, wherein the memory circuit, the arithmetic processing circuit, and the display processing circuit include a single crystal semiconductor substrate, a quartz substrate, a glass substrate, a plastic substrate, and stainless steel. A display device comprising a thin film transistor having a semiconductor thin film formed on one of a substrate and an SOI substrate as an active layer. 請求項１乃至１２のいずれか一項に記載の表示装置において、前記記憶回路をビット毎に順次駆動する機能を有した回路が、前記画素部と同一基板上に形成されていることを特徴とする表示装置。13. The display device according to claim 1, wherein a circuit having a function of sequentially driving the memory circuit for each bit is formed over the same substrate as the pixel portion. Display device. 請求項１乃至１３のいずれか一項に記載の表示装置において、前記記憶回路に前記画像データをビット毎に順次入力する機能を有した回路が、前記画素部と同一基板上に形成されていることを特徴とする表示装置。14. The display device according to claim 1, wherein a circuit having a function of sequentially inputting the image data bit by bit to the memory circuit is formed over the same substrate as the pixel portion. A display device characterized by that. 請求項１乃至１４のいずれか一項に記載の表示装置において、前記半導体薄膜は、連続発振のレーザを用いた結晶化の方法により作製されることを特徴とする表示装置。15. The display device according to claim 1, wherein the semiconductor thin film is manufactured by a crystallization method using a continuous wave laser. 請求項１乃至１５のいずれか一項に記載の表示装置を用いていることを特徴とする電子機器。An electronic apparatus using the display device according to claim 1. 請求項１乃至１５のいずれか一項に記載の表示装置と、画像処理専用の演算処理装置とから構成される表示システム。Display system composed of a display device according an image processor dedicated processor to any one of claims 1 to 15. 請求項１７に記載の表示システムを用いていることを特徴とする電子機器。An electronic apparatus using the display system according to claim 17 .
JP2001366774A 2001-11-30 2001-11-30 Display device and display system using the same Expired - Fee Related JP3913534B2 (en)

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JP2001366774A JP3913534B2 (en) 2001-11-30 2001-11-30 Display device and display system using the same
US10/299,796 US7196709B2 (en) 2001-11-30 2002-11-20 Display device and display system using the same
KR1020020073010A KR100916248B1 (en) 2001-11-30 2002-11-22 Display device and display system using the same
TW091134518A TWI251190B (en) 2001-11-30 2002-11-27 Display device and display system using the same
CNB021548234A CN100367183C (en) 2001-11-30 2002-12-02 Display device and display system using the same
US11/687,449 US7791610B2 (en) 2001-11-30 2007-03-16 Display device and display system using the same

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