TWI636449B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a writing unit, a memory unit, and a liquid crystal unit. The writing unit is enabled according to the gate signal to receive the first data signal and the working voltage. The memory unit is coupled to the writing unit. The liquid crystal unit is coupled to the writing unit and the memory unit. When the working voltage is the first working voltage level, the liquid crystal cell receives the first data signal from the writing unit. When the working voltage is the second working voltage level, the memory unit stores the first data signal from the writing unit. According to the stored first data signal, the liquid crystal unit selectively receives the first data signal or the second data signal. The first working voltage level is different from the second working voltage level.

Description

Pixel circuit

This case relates to a pixel circuit, and more particularly to a pixel circuit having a storage function.

With the rapid development of display devices, people will use large and small display devices, such as mobile phones and computers, at any time and at any occasion. While using the display device, each time the screen of the display device changes, it will cause different power consumption, and the power consumption directly affects people's more concerns about using the display device. Many methods have been proposed to reduce the power consumption of the display device. For example, the voltage applied to the liquid crystal capacitor is maintained through the memory unit to reduce the frequency of writing signals to the pixel unit of the display device, thereby reducing the power consumption of the display device. the amount. However, due to process technology, the above method will cause the display device to fail to meet the requirements of high-end display quality.

Therefore, as people pay more and more attention to the issue of power saving and energy saving, how to reduce the power consumption of the display device without reducing the efficiency of the display device is one of the problems to be improved in this field.

One aspect of this case is to provide a pixel circuit. This pixel The circuit includes a writing unit, a memory unit, and a liquid crystal cell. The writing unit is enabled according to the gate signal to receive the first data signal and the working voltage. The memory unit is coupled to the writing unit. The liquid crystal unit is coupled to the writing unit and the memory unit. When the working voltage is the first working voltage level, the liquid crystal cell receives the first data signal from the writing unit. When the working voltage is the second working voltage level, the memory unit stores the first data signal from the writing unit. According to the stored first data signal, the liquid crystal unit selectively receives the first data signal or the second data signal. The first working voltage level of the working voltage is different from the second working voltage level.

Another aspect of this case is to provide a pixel circuit. The pixel circuit includes a writing unit, a memory unit, and a liquid crystal capacitor. The writing unit is used for receiving the first data signal and the working voltage according to the gate signal. The memory unit is coupled to the writing unit. One end of the liquid crystal capacitor is coupled to the writing unit and the memory unit, and the other end is used to receive a common voltage. The memory unit includes a latch, a first switch, and a second switch. The first end of the first switch is used to receive the first data signal, and the control end of the first switch is coupled to one end of the latch. The second end of the second switch is used to receive the second data signal, the control end of the second switch is coupled to the other end of the latch, and the second end of the first switch is coupled to the first end of the second switch. LCD capacitor. The writing unit includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is configured to receive a first data signal according to a gate signal. The control terminal of the second switch is used to receive the working voltage. The first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is coupled to the memory unit. The control terminal of the third switch is used to receive the gate signal, and the first terminal of the third switch is used to receive the first data signal. First The control terminals of the four switches receive the operating voltage, the first terminal of the fourth switch is coupled to the second terminal of the third switch, and the second terminal of the fourth switch is coupled to the liquid crystal cell.

Therefore, according to the technical aspect of this case, the embodiments of this case provide a pixel circuit, and in particular, a pixel circuit with a storage function, so as to reduce the performance of the display device without reducing the performance of the display device. Consuming.

100‧‧‧ display device

110‧‧‧active area

130‧‧‧Source driving circuit

150‧‧‧Gate driving circuit

D1-DN‧‧‧Data Line

G1-GM‧‧‧Gate line

P11-PMN, P‧‧‧Pixel Circuit

T1-T6‧‧‧ Switch

MNS‧‧‧Working voltage

G [n] ‧‧‧Gate signal

D [n], D [n + 1] ‧‧‧data signals

VCOM‧‧‧ Common Voltage

VSS‧‧‧Working voltage

I1, I2‧‧‧ Inverter

C‧‧‧Capacitor

210‧‧‧write unit

230‧‧‧memory unit

235‧‧‧bolt

250‧‧‧LCD unit

VCH, VCL‧‧‧ Common Voltage Level

VDH, VDL‧‧‧Data signal level

VH, VL‧‧‧ working voltage level

W1, W2, W3, W4‧‧‧

In order to make the above and other objects, features, advantages, and embodiments of the present invention more comprehensible, the description of the drawings is as follows: FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present invention; FIG. 3 is a schematic diagram of an operation waveform according to an embodiment of the present invention; and FIG. 4 is implemented according to one of the embodiments. Example is a schematic diagram of a pixel circuit operation; Figure 5 is a schematic diagram of a pixel circuit operation according to one embodiment of the present invention; Figure 6 is a schematic diagram of a pixel circuit according to one embodiment of the present invention Operation diagram of a pixel circuit; FIG. 7 is an operation diagram of a pixel circuit according to an embodiment of the present invention; and FIG. 8 is a schematic diagram of an operation waveform according to an embodiment of the present invention.

The following disclosure provides many different embodiments or illustrations to implement different features of the invention. The elements and configurations in the particular example are used in the following discussion to simplify the present disclosure. Any illustrations discussed are for illustrative purposes only and do not in any way limit the scope and meaning of the invention or its illustrations. In addition, the present disclosure may repeatedly refer to numerical symbols and / or letters in different examples, and these repetitions are for simplification and explanation, and do not themselves specify the relationship between different embodiments and / or configurations in the following discussion.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content. Certain terms used to describe this disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art on the description of this disclosure.

As used herein, "coupling" or "connection" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "coupling" or " "Connected" may also mean that two or more elements operate or act on each other.

In this article, the terms first, second, third, etc. are used to describe various elements, components, regions, layers, and / or blocks that are understandable. However, these elements, components, regions, layers and / or blocks should not be limited by these terms. These words are limited to identifying single components, groups Files, regions, layers, and / or blocks. Therefore, a first element, component, region, layer, and / or block in the following may also be referred to as a second element, component, region, layer, and / or block without departing from the intention of the present invention. As used herein, the term "and / or" includes any combination of one or more of the associated listed items. The "and / or" mentioned in this document refers to any, all or any combination of at least one of the listed elements.

See Figure 1. FIG. 1 is a schematic diagram of a display device 100 according to some embodiments of the present invention. As shown in FIG. 1, the display device 100 includes an active region 110, a gate driving circuit 150, and a source driving circuit 130. The gate driving circuit 150 is coupled to a plurality of gate lines G1-GM. The source driving circuit 130 is coupled to a plurality of data lines D1-DN. The active region 110 includes a plurality of pixel circuits P11-PMN. The plurality of pixel circuits P11-PMN are respectively coupled to one of the plurality of gate lines G1-GM and one of the plurality of data lines D1-DN.

See Figure 2. FIG. 2 is a schematic diagram of a pixel circuit P according to some embodiments of the present invention. The pixel circuit P is used to represent one of a plurality of pixel circuits P11-PMN in the first figure. The pixel circuit P includes a writing unit 210, a memory unit 230, and a liquid crystal unit 250. The memory unit 230 is coupled to the writing unit 210. The liquid crystal unit 250 is coupled to the writing unit 210 and the memory unit 230. The writing unit 210 receives a gate signal G [n], a data signal D [n], and an operating voltage MNS. The gate signal G [n] is transmitted from the gate driving circuit 150 to the pixel circuit P through one of a plurality of gate lines G1-GM coupled to the pixel circuit P. The data signal D [n] is transmitted from the source driving circuit 130 through a plurality of data lines D1-DN coupled to the pixel circuit P. One of them is transmitted to the pixel circuit P.

For example, please refer to Figure 1 and Figure 2 together. The pixel circuit P11 receives the data signal D [1] through the data line D1, and receives the gate signal G [1] through the gate line G1. The pixel circuit P21 receives the data signal D [1] through the data line D1, and receives the gate signal G [2] through the gate line G2, and so on.

The writing unit 210 is enabled according to the gate signal G [n] to receive the data signal D [n] and the working voltage MNS. That is, when the gate signal G [n] transmits a pulse wave signal to the writing unit 210, the writing unit 210 receives the data signal D [n] and the operating voltage MNS.

When the working voltage MNS is at the first working voltage level, the liquid crystal unit 250 receives the data signal D [n] from the writing unit 210. When the working voltage MNS is at the second working voltage level, the memory unit 230 stores the data from the writing The data signal D [n] of the unit 210, and according to the stored data signal D [n], the liquid crystal unit 250 selectively receives the data signal D [n] or the data signal D [n + 1]. The first working voltage level is different from the second working voltage level.

For example, see Figure 3. FIG. 3 is a schematic diagram of an operation waveform 300 according to some embodiments of the present invention. Please refer to Figure 2 and Figure 3 together. When the working voltage MNS is the working voltage level VL, the liquid crystal cell 250 receives the data signal D [n] from the writing unit 210. When the working voltage MNS is the working voltage level VH, the memory unit 230 stores the data from the writing unit 210. The liquid crystal unit 250 selectively receives the data signal D [n] or the data signal D [n + 1] according to the stored data signal D [n].

For another example, please refer to FIGS. 1 to 3 together. Taking the pixel circuit P11 as an example, when the operating voltage MNS is the operating voltage level VL, the liquid crystal cell 250 receives the data signal D [1] from the writing unit 210. The unit 230 stores the data signal D [1] from the writing unit 210, and according to the stored data signal D [1], the liquid crystal unit 250 selectively receives the data signal D [1] or the data signal D [2]. Taking the pixel circuit P12 as an example, when the operating voltage MNS is the operating voltage level VL, the liquid crystal cell 250 receives the data signal D [1] from the writing unit 210. When the operating voltage MNS is the operating voltage level VH, the memory The unit 230 stores the data signal D [2] from the writing unit 210, and according to the stored data signal D [2], the liquid crystal unit 250 selectively receives the data signal D [2] or the data signal D [3]. The rest of the pixel circuits operate in the same manner.

See Figure 3. In some embodiments, when the working voltage MNS is the working voltage level VL, the data signal D [n] and the data signal D [n + 1] are digital signals in the time interval W2, and the data signal is in the time interval W3. D [n] and the data signal D [n + 1] periodically switch between the data signal level VDL and the data signal level VDH.

In some embodiments, during the time interval W3, the data signal D [n] and the second data signal D [n + 1] have substantially opposite phases. That is, when the data signal D [n] is the data signal level VDL, the data signal D [n + 1] is the data signal level VDH. When the data signal D [n] is the data signal level VDH, the data signal D [n + 1] is the data signal level VDL.

In some embodiments, the common voltage VCOM is periodically switched between the common voltage level VCH and the common voltage level VCL.

In some embodiments, the period of the common voltage VCOM, the data signal D [n], and the data signal D [n + 1] are the same.

Please refer back to Figure 2. In some embodiments, the writing unit 210 further includes a switch T1, a switch T2, a switch T3, and a switch T4. The control terminal of the switch T1 is used to receive the gate signal G [n]. The first end of the switch T1 is used to receive a data signal D [n]. The control terminal of the switch T2 is used to receive the working voltage MNS. A first terminal of the switch T2 is coupled to a second terminal of the switch T1. The second terminal of the switch T2 is coupled to the memory unit 230. The control terminal of the switch T3 is used to receive the gate signal G [n]. The first end of the switch T3 is used to receive a data signal D [n]. The control terminal of the switch T4 receives the working voltage MNS. A first terminal of the switch T4 is coupled to a second terminal of the switch T3. The second terminal of the switch T4 is coupled to the liquid crystal cell 250.

In some embodiments, the switch T2 and the switch T4 are not turned on at the same time. The switches T2 and T4 can be made of different types of transistors, respectively.

In some embodiments, the first terminal of the liquid crystal cell 250 is coupled to the writing unit 210 and the memory unit 230, and the second terminal of the liquid crystal cell 230 receives a common voltage VCOM.

In some embodiments, the liquid crystal cell 250 includes a capacitor C. The first terminal of the capacitor C is coupled to the writing unit 210 and the memory unit 230, and the second terminal of the capacitor C receives a common voltage VCOM.

In some embodiments, the memory unit 230 includes a switch T5, a switch T6, and a latch 235. The control terminal of the switch T5 is coupled to the first terminal of the latch 235. The first terminal of the switch T5 receives the data signal D [n] through the writing unit 210, and the second terminal of the switch T5 is coupled to the first terminal of the switch T6. switch The control terminal of T6 is coupled to the second terminal of the latch 235. The second end of the switch T6 receives the data signal D [n + 1].

In some embodiments, the latch 235 includes an inverter I1 and an inverter I2. The inverters I1 and I2 receive the operating voltage MNS and the operating voltage VSS, respectively. The output terminal of the inverter I1 is coupled to the input terminal of the inverter I2, and the output terminal of the inverter I2 is coupled to the input terminal of the inverter I1.

FIG. 4 is a schematic diagram illustrating an operation of a pixel circuit P according to some embodiments of the present invention. Please refer to Figure 3 and Figure 4 together. In the time interval W1, the working voltage MNS is the working voltage level VL, so the switch T2 and the switch T5 are not turned on, and the switch T4 is turned on. When the pixel circuit P receives the pulse signal of the gate signal G [n] from one of the gate lines G1-GM, the switch T1 and the switch T3 are turned on. Since the switch T2 is not turned on, neither the inverter I1 nor the inverter I2 receives the voltage level. Since the control terminal of the switch T6 is coupled to the output terminal of the inverter I1, and the control terminal of the switch T6 does not receive the voltage level, the switch T6 is not turned on.

Therefore, in the time interval W1, the data signal D [n] is transmitted to the capacitor C of the liquid crystal cell 250 through the switch T1, the switch T3, and the switch T4. In some embodiments, the data signal D [n] is an 8-bit signal during the time interval W1. That is, in the time interval W1, the pixel circuit P can display 256 colors.

FIG. 5 is a schematic diagram illustrating an operation of a pixel circuit P according to some embodiments of the present invention. Please refer to Figure 3 and Figure 5 together. In the time interval W2, the working voltage MNS is the working voltage level VH, so the switch T4 is not conducting and switch T2 is conducting. When the pixel circuit P receives the pulse signal of the gate signal G [n] from one of the gate lines G1-GM, the switch T1 and the switch T3 are turned on.

Therefore, in the time interval W2, the data signal D [n] is transmitted to the memory unit 230 through the switch T1 and the switch T2. In some embodiments, the data signal D [n] is a 1-bit signal during the time interval W2. In some embodiments, the data signal D [n] is 1 or 0 during the time interval W2. In some embodiments, the latch 235 is stored in the data signal D [n] received in the time interval W2. In some embodiments, the time interval W2 will last one frame.

FIG. 6 is a schematic diagram illustrating an operation of a pixel circuit P according to some embodiments of the present invention. Please refer to Figure 3 and Figure 6 together. In the time interval W3, the working voltage MNS is the working voltage level VH, so the switch T4 is not turned on and the switch T2 is turned on. Since the pixel circuit P does not receive the pulse signal of the gate signal G [n] from one of the gate lines G1-GM, the switches T1 and T3 are not turned on. If the data signal D [n] stored in the latch 235 in the time interval W2 is 1, since the voltage at the node A is at a high voltage level, the switch T5 is turned on. After the high voltage of the node A passes the inverter I1, the voltage at the node B is a low voltage level, and the switch T6 is not turned on.

Therefore, in the time interval W3, the data signal D [n] is transmitted to the capacitor C of the liquid crystal cell 250 via the switch T5. When the data signal D [n] is the data signal level VDL, the common voltage VCOM is the common voltage level VCH, and when the data signal D [n] is the data signal level VDH, the common voltage VCOM is the common voltage level VCL . Since the data signal D [n] is The voltage VCOM is reversed, and the clamping pressure across the capacitor C is the maximum voltage difference.

FIG. 7 is a schematic diagram illustrating an operation of a pixel circuit P according to some embodiments of the present invention. Please refer to Figure 3 and Figure 7 together. In the time interval W3, the working voltage MNS is the working voltage level VH, so the switch T4 is not turned on and the switch T2 is turned on. Since the pixel circuit P does not receive the pulse signal of the gate signal G [n] from one of the gate lines G1-GM, the switches T1 and T3 are not turned on. If the data signal D [n] stored in the latch 235 in the time interval W2 is 0, since the voltage of the node A is at a low voltage level, the switch T5 is not turned on. After the low voltage at the node A passes the inverter I1, the voltage at the node B is at a high voltage level, and the switch T6 is turned on.

Therefore, in the time interval W3, the data signal D [n + 1] is transmitted to the capacitor C of the liquid crystal cell 250 via the switch T6. When the data signal D [n + 1] is the data signal level VDL, the common voltage VCOM is the common voltage level VCL, and when the data signal D [n] is the data signal level VDH, the common voltage VCOM is the common voltage level Bit VCH. Since the data signal D [n + 1] is in phase with the common voltage VCOM, the clamping voltage across the capacitor C is the minimum voltage difference.

In the time interval W4, the operation of the pixel circuit P is the same as that in the time interval W1. In some embodiments, the pixel circuit P repeatedly performs the operations in the time interval W1-W3.

As described above, if the data signal D [n] stored by the latch 235 in the time interval W2 is 0, the pressure between the two ends of the capacitor C in the time interval W3 is the minimum pressure difference. If the data signal D [n] stored in the latch 235 in the time interval W2 is 1, the clamping pressure between the two ends of the capacitor C in the time interval W3 is the maximum pressure difference. That is, in response to the storage of the latch 235 in the time interval W2, With the data signal D [n], the liquid crystal cell 250 displays two states of dark or bright in the time interval W3.

FIG. 8 is a schematic diagram of an operation waveform 800 according to some embodiments of the present invention. The data signal D [n], data signal D [n + 1], operating voltage MNS, and gate signal G [n] in the operating waveform 800 are the same as the operating waveform 300 in FIG. 3, and only the common voltage VCOM is the same as that in FIG. The operation waveform 300 is different. As shown in FIG. 8, when the working voltage MNS is the working voltage level VH, the common voltage VCOM is the common voltage level VCH, and when the working voltage MNS is the working voltage level VL, the common voltage VCOM is periodically at the common voltage. Switch between the voltage level VCH and the common voltage level VCL.

The data signal D [n], the data signal D [n + 1], the operating voltage MNS, and the gate signal G [n] in the operation waveform 800 are the same as the operation waveform 300 in FIG. As shown in FIG. 3, the operation under the operation waveform 300 is the same. In the time interval W1, the operation diagram of the pixel circuit P is shown in FIG. 4, and in the time interval W2, the operation diagram of the pixel circuit P is as shown in FIG. As shown in FIG. 5, the operation schematic diagram of the pixel circuit P in the time interval W3 is shown in FIG. 6 or FIG. 7, and the operation schematic diagram of the pixel circuit P in the time interval W4 is shown in FIG. 4.

In some embodiments, please refer to FIG. 2 and FIG. 8 together. When the working voltage MNS is the working voltage level VL, the liquid crystal cell 250 receives the data signal D [n] from the writing unit 210. When the working voltage MNS is the working voltage level VH, the memory unit 230 stores the data from the writing unit 210. The liquid crystal unit 250 selectively receives the data signal D [n] or the data signal D [n + 1] according to the stored data signal D [n].

From the above, in this case, in the time interval W1, the pixel circuit P operates in a normal mode. At this time, the liquid crystal unit 250 of the pixel circuit P receives the data signal D [n] and the data signal D [n ] Is an 8-bit signal so that the display device 100 can display 256 colors. In the time interval W2, the pixel circuit P operates in a pre-still mode. At this time, the memory unit 230 of the pixel circuit P stores a 1-bit signal transmitted by the data signal D [n]. In the time interval W3, the pixel circuit P operates in a still mode. At this time, the liquid crystal cell 250 of the pixel circuit P displays dark or bright according to the data signal D [n] stored in the memory unit 230.

It can be known from the implementation of the present invention that the embodiments of the present invention provide a pixel circuit, and in particular, a pixel circuit having a storage function, so as to reduce the power consumption of the display device without reducing the performance of the display device. .

In addition, the above-mentioned illustration includes sequential exemplary steps, but the steps need not be performed in the order shown. It is within the scope of this disclosure to perform these steps in different orders. Within the spirit and scope of the embodiments of the present disclosure, these steps may be added, replaced, changed, and / or omitted as appropriate.

Although this case has been disclosed as above in the form of implementation, it is not intended to limit the case. Any person skilled in this art can make various modifications and retouches without departing from the spirit and scope of the case. Therefore, the scope of protection of this case should be considered after The attached application patent shall prevail.

Claims (11)

A pixel circuit includes: a writing unit, which is enabled according to a gate signal to receive a first data signal and an operating voltage; a memory unit coupled to the writing unit; and a liquid crystal unit, Coupled to the writing unit and the memory unit; when the working voltage is a first working voltage level, the liquid crystal cell receives the first data signal from the writing unit, and when the working voltage is a second When the working voltage is at a level, the memory unit stores the first data signal from the writing unit, and the liquid crystal unit selectively receives the first data signal or a second data signal according to the stored first data signal. The first working voltage level of the working voltage is different from the second working voltage level. The pixel circuit according to claim 1, wherein when the operating voltage is the second operating voltage level, the first data signal and the second data signal are digital signals in a first time interval, respectively. In a second time interval, the first data signal and the second data signal are periodically switched between a first data signal level and a second data signal level. The pixel circuit according to claim 2, wherein the first data signal and the second data signal have a substantially opposite phase during the second time interval. The pixel circuit according to claim 1, wherein the memory unit further includes: a first switch; and a second switch; wherein when the first data signal stored in the memory unit is a first value , Turning on the first switch, and when the first data signal stored in the memory unit is a second value, turning on the second switch for selectively transmitting the first data signal to the liquid crystal unit. The pixel circuit according to claim 1, wherein the memory unit further includes: a first switch; a second switch; and a latch; wherein a control terminal of the first switch and the latch A first end of the first switch is coupled, a first end of the first switch receives the first data signal, a second end of the first switch is coupled to a first end of the second switch; A control end of the second switch is coupled to a second end of the latch, and a second end of the second switch receives the second data signal. The pixel circuit according to claim 1, wherein a first terminal of the liquid crystal cell is coupled to the writing unit and the memory cell, and a second terminal of the liquid crystal cell receives a common voltage. The pixel circuit according to claim 6, wherein the common voltage is periodically switched between a first common voltage level and a second common voltage level. The pixel circuit according to claim 7, wherein when the working voltage is the first working voltage level, the common voltage is a first common voltage level, and when the working voltage is the second working voltage During the level, the common voltage is periodically switched between the first common voltage level and a second common voltage level. The pixel circuit according to claim 1, wherein the writing unit further comprises: a first switch, a control end of the first switch is used to receive a gate signal, and a first of the first switch Terminal is used to receive the first data signal; a second switch, a control terminal of the second switch is used to receive the working voltage, a first terminal of the second switch is in phase with a second terminal of the first switch Coupled, a second end of the second switch is coupled to the memory unit; a third switch, a control end of the third switch is used to receive the gate signal, and a first end of the third switch For receiving the first data signal; and a fourth switch, a control end of the fourth switch receives the working voltage, a first end of the fourth switch is coupled to a second end of the third switch A second end of the fourth switch is coupled to the liquid crystal cell. A pixel circuit includes: a writing unit for receiving a first data signal and an operating voltage according to a gate signal; a memory unit coupled to the writing unit; and a liquid crystal capacitor, the liquid crystal One end of the capacitor is coupled to the writing unit and the memory unit, and the other end is used to receive a common voltage. The memory unit includes a latch, a first switch, and a first end of the first switch. To receive the first data signal, a control end of the first switch is coupled to one end of the latch and a second switch, and a second end of the second switch is used to receive a second data signal. A control end of the second switch is coupled to the other end of the latch, and a second end of the first switch and a first end of the second switch are coupled to the liquid crystal capacitor; wherein the write The unit includes: a first switch, according to the gate signal, a first end of the first switch is used to receive the first data signal; a second switch, a control end of the second switch is used to receive the work Voltage, a first end of the second switch and A second end of the first switch is coupled, a second end of the second switch is coupled to the memory unit; a third switch, a control end of the third switch is used to receive the gate signal, A first terminal of the third switch is used to receive the first data signal; and a fourth switch, a control terminal of the fourth switch receives the working voltage, a first terminal of the fourth switch and the third switch A second terminal of the switch is coupled, and a second terminal of the fourth switch is coupled to the liquid crystal cell. The pixel circuit according to claim 10, wherein the second switch of the writing unit and the fourth switch of the writing unit are not turned on at the same time.