JP2003158096A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor deviceInfo
- Publication number
- JP2003158096A JP2003158096A JP2001359095A JP2001359095A JP2003158096A JP 2003158096 A JP2003158096 A JP 2003158096A JP 2001359095 A JP2001359095 A JP 2001359095A JP 2001359095 A JP2001359095 A JP 2001359095A JP 2003158096 A JP2003158096 A JP 2003158096A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- adhesive film
- semiconductor wafer
- insulating adhesive
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、特に、半導体ウェハのダイシング技術に適
用して半導体装置の信頼性及び製造歩留を向上する技術
に関するものである。
【０００２】
【従来の技術】スタックドパッケージでもＣＳＰ（Ｃhi
p Ｓize Ｐackage）構造で半導体チップを積層する方
法、及び表面に所望の回路が形成されたウェハの裏面に
熱圧着シートを貼り付け、ダイシング（切断分離）する
ことにより形成された半導体チップの複数個を配線基板
に積層実装する技術が、例えば、特開平１１−２０４７
２０号公報に開示されている。
【０００３】また、表面に所望の回路が形成された半導
体ウェハの裏面に絶縁性接着フィルム（ダイボンドフィ
ルム）を貼り付け、該絶縁性接着フィルムの上にダイシ
ング用フィルムを貼り付けた半導体ウェハを準備し、前
記準備された半導体ウェハをダイヤモンドブレードで切
断して個々の半導体チップに分離する技術が、特許２６
８０３６４号の明細書に開示されている。
【０００４】
【発明が解決しようとする課題】本発明者は、前記従来
技術を検討した結果、以下の問題点を見いだした。
【０００５】前記従来の半導体ウェハをダイヤモンドブ
レードで切断して個々の半導体チップに分離する特許２
６８０３６４号の技術では、前記準備された半導体ウェ
ハ（ダイボンドフィルム付ウェハ）をダイヤモンドブレ
ードで切断した場合、絶縁性接着フィルム（ダイボンド
フィルム）が完全に切断（カット）されず、ヒゲ状のも
のが残り異物となり、ワイヤボンディング不良を起こ
し、半導体装置の信頼性及び製造歩留を低下させるとい
う問題があった。
【０００６】本発明の目的は、半導体装置の信頼性を向
上することが可能な技術を提供することにある。
【０００７】本発明の他の目的は、半導体装置の製造歩
留を向上することが可能な技術を提供することにある。
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
【０００９】
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。
【００１０】表面に複数の回路が形成された半導体ウェ
ハの裏面に絶縁性接着フィルムを貼り付け、該絶縁性接
着フィルムの上にダイシング用フィルムを貼り付けた半
導体ウェハを準備し、前記準備された半導体ウェハをダ
イヤモンドブレードで切断し、その後前記絶縁性接着フ
ィルムを薄型金属カッタで切断して前記半導体ウェハを
個々の半導体チップに分離し、前記絶縁性接着フィルム
の接着力を低下させ、前記半導体チップを取り出して配
線基板に実装し、前記半導体チップの電極と前記配線基
板の電極とをワイヤで電気的に接続し、前記半導体チッ
プとワイヤを樹脂で封止する半導体装置の製造方法であ
る。
【００１１】このように半導体ウェハをダイヤモンドブ
レードで切断し、その後絶縁性接着フィルムを薄型カッ
タで切断することにより、絶縁性接着フィルム（ダイボ
ンドフィルム）のバリ発生を低減することができるの
で、半導体ウェハを個々の半導体チップに完全に分離す
ることができる。これにより、半導体装置の信頼性を向
上することができる。また、半導体装置の製造歩留を向
上することができる。
【００１２】以下、本発明について、図面を参照して実
施の形態（実施例）とともに詳細に説明する。
【００１３】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。
【００１４】
【発明の実施の形態】（実施例１）図１は本発明の実施
例１のＣＳＰ構造の半導体装置の概要構成を示す断面図
であり、（ａ）はサイズの異なる半導体チップを３個積
層実装した半導体装置の断面図、（ｂ）は同じサイズの
半導体チップを３個積層した半導体装置の断面図であ
る。
【００１５】図１において、１、２、３は半導体チッ
プ、４は配線基板、５は絶縁性接着フィルム（ダイボン
ドフィルム）、６はＡｕワイヤ、７は封止樹脂、８は実
装用外部端子（金属ボール）である。
【００１６】本実施例１のＣＳＰ構造の半導体装置は、
図１（ａ）に示すように、サイズの異なる半導体チップ
１、２、３のうち最も大きいサイズの半導体チップ１が
配線基板４の上に絶縁性接着フィルム（絶縁性接着層）
５を介在して実装され、前記半導体チップ１の上に２番
目に大きいさサイズの半導体チップ２が絶縁性接着フィ
ルム５を介在して積層搭載され、前記半導体チップ２の
上に１番小さいサイズの半導体チップ３が絶縁性接着フ
ィルム５を介在して積層搭載されている。前記半導体チ
ップ１、２、３の電極と前記配線基板４の電極とがＡｕ
ワイヤ６で電気的に接続され、前記半導体チップ１、
２、３とＡｕワイヤ６が封止樹脂７で封止されている。
前記配線基板４の裏面には実装用外部端子（金属ボー
ル）８が設けられている。
【００１７】また、本実施例１のＣＳＰ構造の半導体装
置は、同じサイズの半導体チップ１、２、３の場合に
は、図１（ｂ）に示すように、半導体チップ１が前記配
線基板４に実装され、半導体チップ２が前記半導体チッ
プ１より少しずつずらせて積層搭載され、半導体チップ
３が前記半導体チップ２より少しずつずらせて積層搭載
され、前記半導体チップ１、２、３の各々の左片側の電
極と前記配線基板４の左片側の電極とがＡｕワイヤ６で
電気的に接続されている。
【００１８】次に、前記本実施例１のＣＳＰ構造の半導
体装置の半導体チップ１の製造方法について説明する。
【００１９】図２は表面に複数の回路が形成された半導
体ウェハの裏面に絶縁性接着フィルムを貼り付けた状態
の半導体ウェハをダイシング枠に取り付けたときの平面
図、図３は図２のＡ−Ａ’線で切った断面図及びダイヤ
モンドブレードと薄型金属カッタとの位置関係を示す
図、図４は本実施例１のダイシング方法を説明するため
の図であり、（ａ）はダイヤモンドブレードの半導体ウ
ェハ切断時の断面図、（ｂ）は薄型金属カッタの絶縁性
接着フィルム切断時の断面図である。
【００２０】まず、図２及び図３に示すように、表面に
複数の回路が形成された半導体ウェハ１０の裏面に絶縁
性接着フィルム１１を貼り付け、該絶縁性接着フィルム
１１の上にダイシング用フィルム１２を貼り付けた半導
体ウェハ１０Ａを準備する。該準備された半導体ウェハ
１０Ａをダイシング枠１３に取り付け、図３に示すよう
に、前記半導体ウェハ１０Ａの半導体ウェハ１０部分を
ダイヤモンドブレード１４で切断し（図４（ａ））、そ
の後前記絶縁性接着フィルム１１を薄型金属カッタ１５
（例えば、鋼、ステンレース等の薄型金属カッタを用い
る）で切断して前記半導体ウェハ１０Ａを個々の半導体
チップ１、２、３・・・に分離する（図４（ｂ））。こ
の分離された半導体チップ１、２、３・・・を前記半導
体ウェハ１０Ａから取り出す時には、前記絶縁性接着フ
ィルム１１に紫外線（ＵＶ）を照射して接着力を低下さ
せて、ニードル等の突き上げ治具（図示していない）に
より突き上げ、コレット等の真空吸着治具（図示してい
ない）により真空吸着させて取り出す。
【００２１】図５は本実施例１のＣＳＰ型半導体装置の
組立工程の手順を示すフローチャートである。
【００２２】本実施例１のＣＳＰ構造の半導体装置の組
立工程は、図５に示すように、半導体ウェハ１０の裏面
に絶縁性接着フィルム１１を貼り付け、該絶縁性接着フ
ィルム１１の上にダイシング用フィルム１２を貼り付け
た半導体ウェハ１０Ａを準備する。該準備された半導体
ウェハ１０Ａをダイシング枠１３に取り付ける。次に、
前記図３及び図４に示す手段で前記半導体ウェハ１０Ａ
をダイヤモンドブレード１４及び鋼、ステンレース等の
薄型金属カッタ１５でダイシングして、個々の半導体チ
ップ１、２、３に分離する。
【００２３】次に、この半導体チップ１、２、３に分離
された状態の半導体ウェハ１０Ａに紫外線（ＵＶ）を照
射して前記絶縁性接着フィルム１１の接着力を低下させ
る。次に、半導体チップ１をニードル等の突き上げ治具
（図示していない）により突き上げ、コレット等の真空
吸着治具（図示していない）により真空吸着させて取り
出し、前記配線基板４の上に載置し、前記絶縁性接着フ
ィルム１１を介在して実装する。
【００２４】同様にして前記半導体チップ１の上に２番
目に大きいさサイズの半導体チップ２を絶縁性接着フィ
ルム５を介在して積層搭載し、最後に前記半導体チップ
２の上に１番小さいサイズの半導体チップ３を絶縁性接
着フィルム５を介在して積層搭載し、キュアして前記半
導体チップ１、２、３を配線基板４の上に接着して積層
実装する。
【００２５】次に、前記半導体チップ１、２、３の電極
と前記配線基板４の電極とをＡｕワイヤ６で電気的に接
続し、前記半導体チップ１、２、３とＡｕワイヤ６を封
止樹脂７で封止する。この樹脂封止された半導体装置の
前記配線基板３の裏面に実装用外部端子（金属ボール）
８を設けて図１に示すＣＳＰ型半導体装置の組立を完了
する。
【００２６】前記実施例１によれば、前記半導体ウェハ
１０Ａをダイヤモンドブレード１４で切断し、その後絶
縁性接着フィルム１１の絶縁性接着層を鋼、ステンレー
ス等の薄型金属カッタ１５で切断することにより、絶縁
性接着フィルム（ダイボンドフィルム）のバリ発生をな
くすることができるので、半導体ウェハ１０Ａを個々の
半導体チップ１、２、３に完全に分離することができ
る。これにより、半導体装置の信頼性を向上することが
できる。また、半導体装置の製造歩留を向上することが
できる。
【００２７】（実施例２）図６は本発明の実施例２のＣ
ＳＰ構造の半導体装置の概要構成を示す断面図、図７は
本実施例２のＣＳＰ構造の半導体装置の組立工程の手順
を示すフローチャートである。
【００２８】本実施例２は、前記実施例１のＣＳＰ構造
の半導体装置における同じサイズの半導体チップ１、
２、３のうち２個をずらさないで積層した場合の例であ
る。すなわち、図６に示すように、半導体チップ１が配
線基板４の上に絶縁性接着フィルム５を介在して搭載さ
れ、前記半導体チップ１の上にスペーサチップ１６が絶
縁性接着フィルム５を介在して搭載され、前記スペーサ
チップ９の上に半導体チップ３が絶縁性接着フィルム５
を介在して搭載されている。
【００２９】前記半導体チップ１、２、３の電極と前記
配線基板４の電極とがＡｕワイヤ６で電気的に接続さ
れ、前記半導体チップ１、２、３とＡｕワイヤ６が封止
樹脂７で封止されている。この樹脂封止された半導体装
置の前記配線基板４の裏面に実装用外部端子（金属ボー
ル）８が設けられている。
【００３０】本実施例２のＣＳＰ構造の半導体装置の組
立工程は、図７に示すように、基本的に同じであり、前
記実施例１と異なる点は、前記実施例１ではダイボンド
を３回行うに対して本実施例２では２回行うことであ
る。このようにすることにより、前記実施例１のＣＳＰ
構造の半導体装置の組立工程と同様の作用効果を奏す
る。
【００３１】以上、本発明を、前記実施例に基づき具体
的に説明したが、本発明は、前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲において種々変
更可能であることは勿論である。
【００３２】
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、以
下のとおりである。
【００３３】本発明によれば、絶縁性接着フィルム（ダ
イボンドフィルム）のバリ発生を低減することができる
ので、半導体ウェハを個々の半導体チップに完全に分離
することができる。これにより、半導体装置の信頼性を
向上することができる。また、半導体装置の製造歩留を
向上することができる。Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor wafer dicing technique for improving the reliability and manufacturing yield of a semiconductor device. It is related to the technology to do. 2. Description of the Related Art Even a stacked package has a CSP (Chi
A method of stacking semiconductor chips in a pSize Package) structure, and a plurality of semiconductor chips formed by sticking a thermocompression bonding sheet to the back surface of a wafer having a desired circuit formed on its surface and dicing (cutting and separating). The technology for laminating and mounting on a wiring board is disclosed in, for example,
No. 20 discloses this. Also, an insulating adhesive film (die bond film) is attached to the back surface of a semiconductor wafer having a desired circuit formed on the surface, and a semiconductor wafer having a dicing film attached to the insulating adhesive film is prepared. A technique of cutting the prepared semiconductor wafer with a diamond blade to separate individual semiconductor chips is disclosed in Japanese Patent No.
80364. The present inventor has found the following problems as a result of studying the above prior art. [0005] Patent 2 which separates the above-mentioned conventional semiconductor wafer into individual semiconductor chips by cutting with a diamond blade.
In the technique of No. 680364, when the prepared semiconductor wafer (wafer with a die-bonding film) is cut with a diamond blade, the insulating adhesive film (die-bonding film) is not completely cut (cut), and a whisker-like one remains. There is a problem that foreign matter is generated and wire bonding failure occurs, thereby lowering the reliability and manufacturing yield of the semiconductor device. An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device. Another object of the present invention is to provide a technique capable of improving the production yield of a semiconductor device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. [0010] An insulating adhesive film is attached to the back surface of a semiconductor wafer having a plurality of circuits formed on its surface, and a semiconductor wafer having a dicing film attached to the insulating adhesive film is prepared. Cutting the semiconductor wafer with a diamond blade, then cutting the insulating adhesive film with a thin metal cutter to separate the semiconductor wafer into individual semiconductor chips, reducing the adhesive force of the insulating adhesive film, And mounting the semiconductor chip on a wiring board, electrically connecting the electrodes of the semiconductor chip and the electrodes of the wiring board with wires, and sealing the semiconductor chip and the wires with a resin. By cutting the semiconductor wafer with a diamond blade and then cutting the insulating adhesive film with a thin cutter, the occurrence of burrs on the insulating adhesive film (die bond film) can be reduced. Can be completely separated into individual semiconductor chips. Thereby, the reliability of the semiconductor device can be improved. Further, the manufacturing yield of the semiconductor device can be improved. Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings. In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. (Embodiment 1) FIG. 1 is a sectional view showing a schematic structure of a semiconductor device having a CSP structure according to Embodiment 1 of the present invention. FIG. 4B is a cross-sectional view of a semiconductor device in which three semiconductor chips are stacked and mounted, and FIG. 7B is a cross-sectional view of a semiconductor device in which three semiconductor chips of the same size are stacked. In FIG. 1, 1, 2 and 3 are semiconductor chips, 4 is a wiring board, 5 is an insulating adhesive film (die bond film), 6 is an Au wire, 7 is a sealing resin, and 8 is an external mounting terminal ( Metal ball). The semiconductor device having the CSP structure according to the first embodiment is as follows.
As shown in FIG. 1A, a semiconductor chip 1 having the largest size among semiconductor chips 1, 2, and 3 having different sizes is placed on a wiring board 4 with an insulating adhesive film (insulating adhesive layer).
The semiconductor chip 2 having the second largest size is mounted on the semiconductor chip 1 with the insulating adhesive film 5 interposed therebetween, and is mounted on the semiconductor chip 1 with the smallest size. Are stacked and mounted with an insulating adhesive film 5 interposed therebetween. The electrodes of the semiconductor chips 1, 2, 3 and the electrodes of the wiring board 4 are Au
Electrically connected by wires 6, the semiconductor chip 1,
2 and 3 and the Au wire 6 are sealed with a sealing resin 7.
External terminals (metal balls) 8 for mounting are provided on the back surface of the wiring board 4. In the semiconductor device having the CSP structure according to the first embodiment, when the semiconductor chips 1, 2, and 3 have the same size, as shown in FIG. The semiconductor chip 2 is stacked and mounted with a slight shift from the semiconductor chip 1, and the semiconductor chip 3 is stacked and mounted with a slight shift from the semiconductor chip 2, and the left of each of the semiconductor chips 1, 2 and 3 is mounted. One electrode and one electrode on the left side of the wiring board 4 are electrically connected by an Au wire 6. Next, a method of manufacturing the semiconductor chip 1 of the semiconductor device having the CSP structure according to the first embodiment will be described. FIG. 2 is a plan view of a semiconductor wafer having a plurality of circuits formed on its front surface, and a semiconductor wafer in a state where an insulating adhesive film is attached to the back surface of the semiconductor wafer, which is mounted on a dicing frame. FIG. FIG. 4 is a cross-sectional view taken along the line A-A ′ and a view showing a positional relationship between the diamond blade and the thin metal cutter. FIG. 4 is a view for explaining the dicing method according to the first embodiment. FIG. 4B is a cross-sectional view when cutting a semiconductor wafer, and FIG. 4B is a cross-sectional view when cutting an insulating adhesive film of a thin metal cutter. First, as shown in FIGS. 2 and 3, an insulating adhesive film 11 is attached to the back surface of a semiconductor wafer 10 having a plurality of circuits formed on the front surface, and a dicing die is placed on the insulating adhesive film 11. A semiconductor wafer 10A to which the film 12 is attached is prepared. The prepared semiconductor wafer 10A is mounted on a dicing frame 13, and as shown in FIG. 3, a portion of the semiconductor wafer 10A of the semiconductor wafer 10A is cut with a diamond blade 14 (FIG. 4 (a)), and then the insulating bonding is performed. Film 11 is thin metal cutter 15
The semiconductor wafer 10A is cut into individual semiconductor chips 1, 2, 3,... By using a thin metal cutter such as steel or stainless steel (FIG. 4B). When the separated semiconductor chips 1, 2, 3,... Are taken out from the semiconductor wafer 10A, the insulating adhesive film 11 is irradiated with ultraviolet rays (UV) to reduce the adhesive force and to push up a needle or the like. It is pushed up by a tool (not shown), and is taken out by vacuum suction using a vacuum suction jig (not shown) such as a collet. FIG. 5 is a flowchart showing a procedure of an assembling process of the CSP type semiconductor device of the first embodiment. In the assembling process of the semiconductor device having the CSP structure according to the first embodiment, as shown in FIG. 5, an insulating adhesive film 11 is attached to the back surface of the semiconductor wafer 10 and dicing is performed on the insulating adhesive film 11. A semiconductor wafer 10A to which the film 12 is attached. The prepared semiconductor wafer 10A is mounted on the dicing frame 13. next,
The semiconductor wafer 10A is provided by the means shown in FIGS.
Is diced with a diamond blade 14 and a thin metal cutter 15 such as steel or stainless steel to separate the semiconductor chips 1, 2 and 3. Next, the semiconductor wafer 10A separated into the semiconductor chips 1, 2, and 3 is irradiated with ultraviolet rays (UV) to reduce the adhesive strength of the insulating adhesive film 11. Next, the semiconductor chip 1 is pushed up by a push-up jig (not shown) such as a needle, is taken out by vacuum suction using a vacuum suction jig (not shown) such as a collet, and is mounted on the wiring board 4. And mounting with the insulating adhesive film 11 interposed. Similarly, the semiconductor chip 2 having the second largest size is stacked and mounted on the semiconductor chip 1 with the insulating adhesive film 5 interposed therebetween. The semiconductor chips 3 are stacked and mounted with an insulating adhesive film 5 interposed therebetween, cured, and the semiconductor chips 1, 2 and 3 are bonded and stacked on a wiring board 4. Next, the electrodes of the semiconductor chips 1, 2, 3 and the electrodes of the wiring board 4 are electrically connected by Au wires 6, and the semiconductor chips 1, 2, 3 and the Au wires 6 are sealed. Seal with resin 7. Mounting external terminals (metal balls) on the back surface of the wiring board 3 of the resin-sealed semiconductor device.
8 to complete the assembly of the CSP type semiconductor device shown in FIG. According to the first embodiment, the semiconductor wafer 10A is cut with a diamond blade 14, and then the insulating adhesive layer of the insulating adhesive film 11 is cut with a thin metal cutter 15 such as steel or stainless steel. Since the occurrence of burrs on the insulating adhesive film (die bond film) can be eliminated, the semiconductor wafer 10A can be completely separated into the individual semiconductor chips 1, 2, and 3. Thereby, the reliability of the semiconductor device can be improved. Further, the manufacturing yield of the semiconductor device can be improved. (Embodiment 2) FIG. 6 is a view showing C of Embodiment 2 of the present invention.
FIG. 7 is a cross-sectional view illustrating a schematic configuration of a semiconductor device having an SP structure. FIG. 7 is a flowchart illustrating a procedure of an assembling process of the semiconductor device having a CSP structure according to the second embodiment. In the second embodiment, a semiconductor chip 1 of the same size in the semiconductor device having the CSP structure of the first embodiment,
This is an example of a case where two of 2, 3 are stacked without shifting. That is, as shown in FIG. 6, the semiconductor chip 1 is mounted on the wiring substrate 4 with the insulating adhesive film 5 interposed therebetween, and the spacer chip 16 is mounted on the semiconductor chip 1 with the insulating adhesive film 5 interposed therebetween. The semiconductor chip 3 is mounted on the spacer chip 9 with the insulating adhesive film 5.
Is interposed. The electrodes of the semiconductor chips 1, 2, 3 and the electrodes of the wiring board 4 are electrically connected by Au wires 6, and the semiconductor chips 1, 2, 3 and the Au wires 6 are connected by a sealing resin 7. It is sealed. Mounting external terminals (metal balls) 8 are provided on the back surface of the wiring board 4 of the resin-sealed semiconductor device. As shown in FIG. 7, the assembling process of the semiconductor device having the CSP structure according to the second embodiment is basically the same as that of the first embodiment, except that the die bonding is performed three times in the first embodiment. In contrast to this, in the second embodiment, this is performed twice. By doing so, the CSP of the first embodiment
The same operation and effect as those of the assembling process of the semiconductor device having the structure can be obtained. As described above, the present invention has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and may be variously modified without departing from the gist thereof. Of course. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. According to the present invention, the occurrence of burrs on the insulating adhesive film (die bond film) can be reduced, so that the semiconductor wafer can be completely separated into individual semiconductor chips. Thereby, the reliability of the semiconductor device can be improved. Further, the manufacturing yield of the semiconductor device can be improved.
【図面の簡単な説明】
【図１】本発明の実施例１のＣＳＰ構造の半導体装置の
概要構成を示す断面図である。
【図２】表面に複数の回路が形成された半導体ウェハの
裏面に絶縁性接着フィルムを貼り付けた状態の半導体ウ
ェハをダイシング枠に取り付けたときの平面図である。
【図３】図２のＡ−Ａ’線で切った断面及びダイヤモン
ドカッタと薄型カッタとの位置関係を示す図である。
【図４】本実施例１のダイシング方法を説明するための
図である。
【図５】本実施例１のＣＳＰ構造の半導体装置の組立工
程の手順を示すフローチャートとその説明するための各
工程における断面である。
【図６】本発明の実施例２のＣＳＰ貨造の半導体装置の
概要構成を示す断面図である。
【図７】本実施例２のＣＳＰ構造の半導体装置の製造手
順を示すフローチャートである。
【符号の説明】
１、２、３…半導体チップ ４…配線基板
５…絶縁性接着フィルム ６…Ａｕワイヤ
７…封止樹脂 ８…実装用外部
端子（金属ボール）
９…スペーサチップ １０…半導体ウ
ェハ
１０Ａ…半導体ウェハ裏面に絶縁性接着フィルムとダイ
シング用フィルムを貼り付けた半導体ウェハ
１１…絶縁性接着フィルム １２…ダイシン
グ用フィルム
１３…ダイシング枠 １４…ダイヤモ
ンドブレード
１５…薄型金属カッタ １６…スペーサ
チップBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device having a CSP structure according to a first embodiment of the present invention. FIG. 2 is a plan view showing a state where a semiconductor wafer having a plurality of circuits formed on a front surface and an insulating adhesive film adhered to a back surface is mounted on a dicing frame. FIG. 3 is a diagram showing a cross section taken along line AA ′ of FIG. 2 and a positional relationship between a diamond cutter and a thin cutter. FIG. 4 is a diagram for explaining a dicing method according to the first embodiment. FIGS. 5A and 5B are a flowchart showing a procedure of an assembling process of the semiconductor device having the CSP structure according to the first embodiment and a cross section in each process for explaining the flowchart. FIG. 6 is a cross-sectional view illustrating a schematic configuration of a semiconductor device manufactured by a CSP coin according to a second embodiment of the present invention. FIG. 7 is a flowchart illustrating a manufacturing procedure of the semiconductor device having the CSP structure according to the second embodiment; [Description of Signs] 1, 2, 3 ... semiconductor chip 4 ... wiring board 5 ... insulating adhesive film 6 ... Au wire 7 ... sealing resin 8 ... mounting external terminals (metal balls) 9 ... spacer chip 10 ... semiconductor wafer 10A: Semiconductor wafer having an insulating adhesive film and a dicing film adhered to the back surface of the semiconductor wafer 11: Insulating adhesive film 12: Dicing film 13: Dicing frame 14: Diamond blade 15: Thin metal cutter 16: Spacer chip
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat ゛ (Reference)
Claims (1)
ェハの裏面に絶縁性接着フィルムを貼り付け、該絶縁性
接着フィルムの上にダイシング用フィルムを貼り付けた
半導体ウェハを準備する工程と、 前記準備された半導体ウェハをダイヤモンドブレードで
切断し、その後前記絶縁性接着フィルムを薄型金属カッ
タで切断して前記半導体ウェハを個々の半導体チップに
分離する工程と、前記絶縁性接着フィルムの接着力を低
下させ、前記半導体チップを取り出して配線基板に実装
する工程と、前記半導体チップの電極と前記配線基板の
電極とをワイヤで電気的に接続する工程と、前記半導体
チップとワイヤを樹脂で封止する工程とを有することを
特徴とする半導体装置の製造方法。Claims: 1. A semiconductor wafer having an insulating adhesive film attached to a back surface of a semiconductor wafer having a plurality of circuits formed on a front surface, and a dicing film attached to the insulating adhesive film. Preparing the semiconductor wafer, cutting the prepared semiconductor wafer with a diamond blade, and then cutting the insulating adhesive film with a thin metal cutter to separate the semiconductor wafer into individual semiconductor chips; Lowering the adhesive force of the adhesive film, taking out the semiconductor chip and mounting it on a wiring board, electrically connecting the electrode of the semiconductor chip and the electrode of the wiring board with a wire, Sealing the wire with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001359095A JP2003158096A (en) | 2001-11-26 | 2001-11-26 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001359095A JP2003158096A (en) | 2001-11-26 | 2001-11-26 | Manufacturing method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003158096A true JP2003158096A (en) | 2003-05-30 |
Family
ID=19170166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001359095A Pending JP2003158096A (en) | 2001-11-26 | 2001-11-26 | Manufacturing method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003158096A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378921C (en) * | 2004-01-30 | 2008-04-02 | 株式会社电装 | Method of manufacturing a semiconductor device including electrodes on main and reverse sides of a semiconductor chip |
| US7736999B2 (en) | 2006-03-16 | 2010-06-15 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
-
2001
- 2001-11-26 JP JP2001359095A patent/JP2003158096A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378921C (en) * | 2004-01-30 | 2008-04-02 | 株式会社电装 | Method of manufacturing a semiconductor device including electrodes on main and reverse sides of a semiconductor chip |
| US7736999B2 (en) | 2006-03-16 | 2010-06-15 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
| US8039364B2 (en) | 2006-03-16 | 2011-10-18 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
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