JP2003152570A - Noise-removing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise-removing circuit which can be integrally formed on a semiconductor substrate. SOLUTION: The noise-educing circuit 30 is provided with an HPF 32, an amplifier 34, a full-wave rectifier circuit 36, a time constant circuit 100, a voltage comparator 40, single-shot circuit 42, an amplifier 50, a delay circuit 52, an FET 54, a capacitor 56, and a buffer 58. The time constant circuit 100 is provided with a charging circuit for intermittently charging a capacitor and a discharging circuit for intermittently discharging the capacitor, and the intermittent charging/discharging operation is conducted on the capacitor whose electrostatic capacity is small, so that a large time constant can be set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise removing circuit for removing a noise component included in a signal in a receiver or the like.

[0002]

2. Description of the Related Art Noise generated by other on-vehicle equipment is likely to be mixed in a signal input / output in an in-vehicle AM receiver or FM receiver. Therefore, various types of noise removal circuits have been conventionally used. For example, in one of them,
There is a method of removing noise by extracting a noise component from a signal, masking a part of the signal corresponding to this noise component, and holding the voltage of the signal input immediately before that. This noise removal circuit can remove only this noise from scattered noise, but if you perform the same removal operation for white noise that occurs when the received electric field strength decreases, you want to pass it. Since most of the signals are removed by the noise removal circuit, a mechanism for stopping the removal operation is required when the level of white noise rises.
For example, by controlling the gain of an amplifier that amplifies the extracted noise component according to the smoothed voltage level of the noise component, a method of suppressing the noise component output from this amplifier when white noise occurs is adopted. There is.

[0003]

By the way, in the above-mentioned conventional noise removing circuit, it is necessary to smooth the noise component, and a low pass filter having a large time constant is used.
That is, it is necessary to set the element constant of the capacitor or resistor that configures the low-pass filter to a large value so that the smoothed voltage by the low-pass filter does not rise when the noise to be removed is input. Considering the increase in the noise, there is a problem that the noise removing circuit cannot be integrally formed with the other circuits on the semiconductor substrate.

The present invention has been made in view of the above points, and an object thereof is to provide a noise elimination circuit which can be integrally formed on a semiconductor substrate.

[0005]

In order to solve the above-mentioned problems, the noise removing circuit of the present invention uses a high-pass filter for detecting a noise component included in an input signal and a noise component output from the high-pass filter. An amplifier that amplifies with a gain according to the control voltage, a time constant circuit that generates a control voltage by smoothing the noise component amplified by this amplifier with a predetermined time constant, and a voltage level of the noise component amplified by the amplifier A pulse generation circuit that generates a pulse of a predetermined width at a timing when it becomes equal to or higher than a predetermined reference voltage,
A delay circuit that delays the input signal for a predetermined time and outputs it, and when the pulse generated by the pulse generation circuit is input, holds the signal output from the delay circuit at the timing immediately before that, and at other times. And an output circuit for directly outputting the signal output from the delay circuit. The time constant circuit is composed of a capacitor, a voltage comparator for comparing the terminal voltage of the capacitor with the input voltage, and a charging for intermittently charging the capacitor when the input voltage is relatively higher than the terminal voltage. A circuit and a discharge circuit that intermittently discharges a discharge current from the capacitor when the terminal voltage is relatively lower than the input voltage. Since the capacitor is intermittently charged and discharged, the terminal voltage changes gently even when the capacitance of the capacitor is reduced, and an equivalently large time constant can be set. Therefore, even when a capacitor having a small capacitance is used, a large time constant can be set in the time constant circuit in the noise removing circuit, and the noise removing circuit can be integrally formed on the semiconductor substrate. Become.

Further, the charging circuit is configured to include a current supply unit that supplies a predetermined charging current to the capacitor and a first timing control unit that controls the timing of the intermittent supply operation of the charging current by the current supply unit. In addition, the discharge circuit is configured to include a current emission unit that emits a predetermined discharge current from the capacitor and a second timing control unit that controls the timing of the intermittent discharge operation of the discharge current by the current emission unit. Is desirable. By controlling the timing of the charging current supply operation by the current supply unit and the timing of the discharge current discharge operation by the current discharge unit, the intermittent discharge operation of the capacitor can be easily controlled.

Further, the above-mentioned time constant circuit has a charging / discharging speed setting means for differentiating the intermittent supply time of the charging current and the intermittent discharging time of the discharging current controlled by the first and second timing control units. It is desirable to further include By providing the charging / discharging speed setting means, the charging speed and the discharging speed for the capacitor in the time constant circuit can be made different, so the detection time when the white noise included in the signal increases and the detection time when the white noise included in the signal decreases. Can be different.

Further, when each of the first and second timing control units has a switch for controlling the timing based on a pulse signal having a predetermined duty ratio, the above-mentioned charge / discharge speed setting means. It is desirable that the duty ratio of the charging pulse signal be different from the duty ratio of the discharging pulse signal. This facilitates the control of differentiating the charging time and the discharging time.

Further, it is desirable that the above-mentioned time constant circuit further comprises a charge / discharge speed setting means for differentiating the charging current supplied by the current supply unit and the discharging current discharged by the current discharging unit. As a result, the detection time when the white noise included in the signal increases and the detection time when the white noise decreases can be made different.

Further, when each of the current supply unit and the current emission unit is composed of a transistor to which a predetermined reference voltage is applied to the gate, the above-mentioned charge / discharge speed setting means is provided with a charging transistor and a discharging transistor. It is desirable to have different transistor gate dimensions. This facilitates control to make the charging current value and the discharging current value different.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A noise removing circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an FM receiver including a noise removing circuit according to an embodiment. As shown in Figure 1,
The FM receiver of this embodiment includes an intermediate frequency amplification circuit 10, a detection circuit 20, and a noise removal circuit 30.

The intermediate frequency amplifier circuit 10 amplifies the intermediate frequency signal which has been frequency-converted by the mixing circuit (not shown) in the preceding stage. The detection circuit 20 includes the intermediate frequency amplification circuit 10
FM detection processing is performed on the intermediate frequency signal amplified by to output a stereo composite signal.

The noise removing circuit 30 removes the noise component contained in the detected stereo composite signal output from the detecting circuit 20. Therefore, the noise removing circuit 30
High-pass filter (HPF) 32, amplifier 34, full-wave rectifier circuit 36, time constant circuit 100, voltage comparator 40, 1-shot circuit 42, amplifier 50, delay circuit 52, FET 5
4, a capacitor 56, and a buffer 58.

The high-pass filter 32 passes only the high frequency component including the noise component contained in the stereo composite signal output from the detection circuit 20. The amplifier 34 has a gain corresponding to the applied control voltage and has a high pass filter 32.
The noise component that has passed through is amplified. Full wave rectifier circuit 36
Performs full-wave rectification on the amplified noise component output from the amplifier 34. In general, noise mixed in a signal having a predetermined voltage level has negative polarity as well as positive polarity. Therefore, in the full-wave rectifier circuit 36, two types of noise components having different polarities are rectified to be the same. A polar noise component is generated. The time constant circuit 100 includes the full-wave rectifier circuit 3
A control voltage applied to the amplifier 34 is generated by smoothing the noise component rectified by 6 with a predetermined time constant. Details of the configuration and operation of the time constant circuit 100 will be described later.

The voltage comparator 40 compares the noise component rectified by the full-wave rectification circuit 36 with a predetermined reference voltage Vref, and sets the output to a high level in response to the noise whose peak value exceeds the reference voltage Vref. . The one-shot circuit 42 is
When the output of the voltage comparator 40 becomes high level, that is, when noise is detected, a single pulse having a predetermined pulse width is generated.

The amplifier 50 amplifies the detected stereo composite signal output from the detection circuit 20. Delay circuit 52
Outputs the input stereo composite signal after delaying it by a predetermined time. This delay time is set corresponding to the processing time of each circuit from the high pass filter 32 to the one-shot circuit 42 described above. The FET 54 is a delay circuit 52
Is a switching element for passing or blocking a stereo composite signal output from the one-shot circuit 42, the stereo composite signal is blocked when the pulse output from the one-shot circuit 42 is input to the gate, and the stereo composite signal otherwise. Pass through. The capacitor 56 holds the signal level immediately before the stereo composite signal is cut off by the FET 54. The buffer 58 has a high input impedance, and the stereo composite signal that has passed through the FET 54 or the holding voltage of the capacitor 56 immediately before being cut off is taken out via the buffer 58 to the outside.

FIG. 2 is a timing chart showing the operating state of the noise removal circuit of this embodiment. In FIG.
Each of (A) to (F) shows an input / output signal waveform of each part denoted by the same reference numeral in FIG. 1. When the stereo composite signal mixed with noise is output from the detection circuit 20 (FIG. 2 (A)), the noise component contained in this stereo composite signal is extracted by the high-pass filter 32 (FIG. 2 (B)). The full-wave rectifier circuit 36 rectifies this noise component (FIG. 2C), and the one-shot circuit 42 generates a pulse signal corresponding to each noise (FIG. 2).
(D)).

The delay circuit 52 delays and outputs the stereo composite signal output from the detection circuit 20 for the time required to generate this pulse signal (FIG. 2 (E)).
As a result, the timing at which the noise included in the stereo composite signal is output coincides with the timing at which the pulse corresponding to this noise is output from the one-shot circuit 42. FET 54 is a one-shot circuit 4
When a pulse is output from 2, the input stereo composite signal is cut off. At the time of this cutoff, the voltage held in the capacitor 56 immediately before that is taken out by the buffer 58, so that in the stereo composite signal output from the buffer 58, the portion corresponding to the noise component is replaced with the voltage level immediately before that.

By the way, the time constant of the time constant circuit 100 is
A value that does not respond to sporadic noise as shown in FIG. 2C is set. However, particularly in the case of FM broadcasting, when the reception electric field strength of the broadcast wave decreases, white noise tends to increase overall. In such a case, the control voltage generated by the time constant circuit 100 increases. As a result, the gain of the amplifier 34 decreases. Therefore, the output voltage of the full-wave rectification circuit 36 becomes low, the output voltage of the voltage comparator 40 maintains a low level, and the 1-shot circuit 42 does not generate a pulse. As a result, the stereo composite signal output from the delay circuit 52 is
The data is output via the buffer 58 without being blocked by. When the white noise included in the stereo composite signal increases, it is necessary to stop the signal cutoff by the FET 54 promptly, so that the control voltage generated by the time constant circuit 100 increases and the gain of the amplifier 34 increases. It is necessary to set the lowering time (attack time) short. On the other hand, it is desirable to set the time for the gain of the amplifier 34 to rise (release time) to some extent in consideration of operational stability and the like.

FIG. 3 is a diagram showing a principle block of the time constant circuit 100. As shown in FIG. 3, the time constant circuit 100 of the present embodiment includes a capacitor 110, a voltage comparator 11
2. A charging circuit 114, a discharging circuit 116, and a charging / discharging speed setting unit 118 are provided. The voltage comparator 112 compares the terminal voltage of the capacitor 110 with the input voltage and validates the operation of the charging circuit 114 or the discharging circuit 116 according to the comparison result. The charging circuit 114 charges the capacitor 110 by intermittently supplying a charging current. For example, the charging circuit 114 is configured to include a constant current circuit and a switch, and the charging current is supplied from the constant current circuit to the capacitor 110 when the switch is turned on. In addition, the discharge circuit 116 discharges the capacitor 110 by intermittently supplying a discharge current.
For example, the discharging circuit 116 includes a constant current circuit and a switch, and a constant current is discharged from the capacitor 110 when the switch is turned on. The charging / discharging speed setting unit 118 sets the charging speed of the capacitor 110 by the charging circuit 114 and the discharging speed of the capacitor 110 by the discharging circuit 116 to be different.
The charging / discharging speed setting unit 118 corresponds to charging / discharging speed setting means, and the specific contents will be described later.

As described above, the time constant circuit 10 of the present embodiment.
0 is performing intermittent charging / discharging operation with respect to the capacitor 110. Therefore, even when the capacitance of the capacitor 110 is set to be small, a circuit having a large time constant in which the voltage across the capacitor gradually changes, that is, a capacitor having a large capacitance or a resistor having a large resistance value is used. The same charge / discharge characteristics as the case can be obtained. In the charging circuit 114 and the discharging circuit 116, a predetermined current is supplied to the capacitor 110 or the capacitor 110
However, since the supply and discharge operations are intermittently performed, the current value at that time can be set to a relatively large value suitable for IC implementation. Therefore, it becomes possible to form the noise removal circuit 30 including the time constant circuit 100 on a semiconductor substrate to form an IC. Further, since external parts such as a capacitor are not required, the noise removing circuit 30 as a whole can be significantly downsized.

Further, the time constant circuit 100 of this embodiment is
The charge / discharge speed setting unit 118 is set so that the charge speed and the discharge speed for the capacitor 110 are different. Therefore, it is possible to make the time when the gain of the amplifier 34 decreases with the increase of the control voltage and the time when the gain of the amplifier 34 increases with the decrease of the control voltage.

FIG. 4 is a circuit diagram showing a specific configuration of the time constant circuit 100. As shown in FIG. 4, the time constant circuit 1
00 is a capacitor 110, a constant current circuit 140, an FET
142, 144, 150, 154, 156, switch 1
46, 152, voltage comparator 160, AND circuit 162,
164 and a frequency divider 170 are included.

A current mirror circuit is formed by the two FETs 142 and 144, and the same charging current as the constant current output from the constant current circuit 140 is generated. Further, the switch 146 determines the generation timing of this charging current. The switch 146 is composed of the inverter circuit 1, the analog switch 2, and the FET 3. The analog switch 2 is configured by connecting the source and drain of a p-channel FET and an n-channel FET in parallel. The output signal of the AND circuit 162 is directly input to the gate of the n-channel FET, and a signal obtained by inverting the logic of this output signal by the inverter circuit 1 is input to the gate of the p-channel FET. Therefore, the analog switch 2 is turned on when the output signal of the AND circuit 162 is at high level, and is turned off when it is at low level. Further, the FET 3 is for surely stopping the current supply operation by the FET 144 by connecting the gate and drain of the FET 144 with low resistance when the analog switch 2 is in the off state.

When the switch 146 is turned on, the gate of one FET 142 to which the constant current circuit 140 is connected is connected to the gate of the other FET 144, so that the constant current circuit connected to one FET 142 is connected. 1
Almost the same current as the constant current generated by 40 also flows between the source and drain of the other FET 144. This current is supplied to the capacitor 110 as a charging current.
On the contrary, when the switch 146 is turned off, the FET1
Since the gate of 44 is connected to the drain,
The supply of this charging current is stopped.

The constant current circuit 140 and two F's described above
The ETs 142 and 144 correspond to the current supply unit. The switch 146 and the AND circuit 162 correspond to the first timing control unit. Further, the above-mentioned FET 142 and constant current circuit 1
A current mirror circuit that sets the discharge current of the capacitor 110 is configured by combining the FET 150 with the FET 40, and the operating state thereof is determined by the switch 152. The switch 152 has the same configuration as the switch 146. The on / off state of the switch 152 is controlled according to the logic of the output signal of the AND circuit 164, and the switch 152 is turned on when the output signal has a high level and turned off when the output signal has a low level.

When the switch 152 is turned on, the gate of one FET 142 to which the constant current circuit 140 is connected and the gate of the other FET 150 are connected to each other, so that a constant current generated by the constant current circuit 140 is generated. A current substantially the same as the current also flows between the source and drain of the other FET 150. This current becomes a discharge current for discharging the electric charge accumulated in the capacitor 110.

However, since the current flowing in the FET 150 cannot be directly taken out from the capacitor 110, in the present embodiment, the FET 154,
Another current mirror circuit constituted by 156 is connected. The gates of the two FETs 154 and 156 are connected to each other, and when the above-described discharge current flows through the FET 154, the same current also flows between the source and drain of the other FET 156. This FE
The drain of T156 is connected to the terminal on the high potential side of the capacitor 110, and the current flowing through the FET 156 is
It is generated by discharging the electric charge accumulated in the capacitor 110.

The constant current circuit 140 and four F's described above
The ETs 142, 150, 154, 156 correspond to the current emitting portion. The switch 152 and the AND circuit 164 correspond to the second timing control unit. In addition, the voltage comparator 160
Compares the terminal voltage of the capacitor 110 applied to the positive terminal with the input voltage of the time constant circuit 100 applied to the negative terminal. This voltage comparator 160 is
It has a non-inverting output terminal and an inverting output terminal, and when the terminal voltage of the capacitor 110 applied to the plus terminal is higher than the input voltage applied to the minus terminal, a high level is output from the non-inverting output terminal. A signal is output, and a low level signal is output from the inverting output terminal. On the contrary, when the terminal voltage of the capacitor 110 applied to the positive terminal is smaller than the input voltage applied to the negative terminal, a low level signal is output from the non-inverting output terminal,
A high level signal is output from the inverting output terminal.

A predetermined pulse signal is input to one input terminal of the AND circuit 162, and the non-inverting output terminal of the voltage comparator 160 is connected to the other input terminal. Therefore, the terminal voltage of the capacitor 110 is better than the time constant circuit 10
When the input voltage is greater than 0, the AND circuit 162 outputs a predetermined pulse signal.

The AND circuit 164 has one input terminal to which a predetermined pulse signal output from the frequency divider 170 is input, and the other input terminal to which the inverting output terminal of the voltage comparator 160 is connected. Therefore, the capacitor 110
When the terminal voltage of is smaller than the input voltage of the time constant circuit 100, the AND circuit 164 outputs a predetermined pulse signal. The frequency divider 170 described above corresponds to the charge / discharge speed setting means.

The frequency divider 170 divides the pulse signal input to one input terminal of the AND circuit 162 by a predetermined frequency division ratio and outputs it. As described above, the pulse signal after the frequency division is input to one input terminal of the AND circuit 164. The time constant circuit 100 has such a configuration,
Next, the operation will be described.

When the capacitor 110 is not charged at the start of the operation of the time constant circuit 100, or when the time constant circuit 100
If the input voltage of the
The terminal voltage of 0 is lower than the input voltage of the time constant circuit 100. At this time, the AND circuit 162 outputs a pulse signal, and the AND circuit 164 does not output a pulse signal. Therefore, only the switch 146 is intermittently turned on, and a predetermined charging current is supplied to the capacitor 110 at the timing when this switch is turned on. This charging operation is continued until the terminal voltage of the capacitor 110 becomes relatively higher than the input voltage of the time constant circuit 100.

Also, the capacitor 1 is charged by this charging operation.
When the terminal voltage of 10 exceeds the input voltage of the time constant circuit 100, or when this input voltage tends to decrease, the capacitor 1
If this input voltage is lower than the terminal voltage of 10,
The AND circuit 164 outputs a pulse signal, and the AND circuit 162 does not output a pulse signal. Therefore, only the switch 152 is intermittently turned on, and a predetermined discharge current is discharged from the capacitor 110 at the timing when this switch is turned on. This discharging operation is continued until the terminal voltage of the capacitor 110 becomes relatively lower than the input voltage of the time constant circuit 100.

Further, the two AND circuits 162,
Comparing the two types of pulse signals output from the AND circuit 164, the duty ratio of the pulse signal output from the AND circuit 162 is larger than the duty ratio of the pulse signal output from the AND circuit 164. Considering the case where the pulse signals are output from each of 162, 164 for the same time, the charging rate per unit time is faster than the discharging rate.

In the time constant circuit 100 described above, 2
The frequency divider 170 is used to output the pulse signals having different duty ratios from the one AND circuit 162 and 164, but the pulse signals having different duty ratios are separately generated and input to the two AND circuits 162 and 164, respectively. You may do it. Alternatively, by removing the frequency divider 170, the charging time and the discharging time of the capacitor 110 can be made the same.

Further, in the above-mentioned time constant circuit 100, in order to make the charging speed and the discharging speed for the capacitor 110 different, the ratios of the FETs 144 and 150 in the ON state per unit time are made different. The charge current and the discharge current themselves may be made different by making the gate size of the FET different.

FIG. 5 is a circuit diagram showing a modification of the time constant circuit. The time constant circuit 100A shown in FIG. 5 is different from the time constant circuit 100 shown in FIG. 4 in that the frequency divider 170 is deleted and the two FETs 144 and 150 are changed to two FETs 144A and 150A whose gate dimensions are changed. The difference is that you did.

FIG. 6 is a diagram showing the gate dimensions of a MOS type FET (FET). Even if the gate voltage is the same, by changing the gate width W and the gate length L, the channel resistance changes, so the current flowing between the source and drain changes. In this embodiment, in order to increase the charging current and shorten the attack time, the gate width W of the FET 144A is set to a large value and the gate length L is set to a small value. On the other hand, to reduce the discharge current and lengthen the release time, the gate width W of the FET 150A is set to a small value.
The gate length L is set to a large value. In this way, FET
The attack time and the release time can be easily made different by making the gate sizes of 144A and 150A different. In this case, the FET 144
Each of A and 150A constitutes a part of the charging circuit 114 and the discharging circuit 116 and has a function as a charge / discharge speed setting means.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in the embodiment described above,
The case where the noise included in the stereo composite signal output from the detection circuit 20 included in the FM receiver is reduced has been described, but the noise included in the audio signal output from the detection circuit included in the AM receiver is reduced. The present invention can be applied to the case where noise included in another signal is reduced as in the case.

[0041]

As described above, according to the present invention, since the capacitor is intermittently charged and discharged, the terminal voltage changes gently even when the capacitance of the capacitor is reduced. , A large time constant can be set equivalently. Therefore, even when a capacitor having a small capacitance is used, a large time constant can be set in the time constant circuit in the noise removing circuit, and the noise removing circuit can be integrally formed on the semiconductor substrate. Become.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an FM receiver including a noise removing circuit according to an embodiment.

FIG. 2 is a timing diagram showing an operating state of the noise removal circuit of the present embodiment.

FIG. 3 is a diagram showing a principle block of a time constant circuit.

FIG. 4 is a circuit diagram showing a specific configuration of a time constant circuit.

FIG. 5 is a circuit diagram showing a modified example of a time constant circuit.

FIG. 6 is a diagram showing a gate size of a MOS type FET.

[Explanation of symbols]

10 Intermediate frequency amplifier circuit 20 Detection circuit 30 noise removal circuit 32 High-pass filter (HPF) 34, 50 amplifier 36 Full-wave rectifier circuit 40, 112 voltage comparator 42 1-shot circuit 52 Delay circuit 54 FET 56,110 condenser 58 buffer 100 time constant circuit 114 charging circuit 116 discharge circuit 118 Charge / discharge speed setting unit

Claims (7)

[Claims] 1. A high-pass filter for detecting a noise component included in an input signal, an amplifier for amplifying the noise component output from the high-pass filter with a gain according to a control voltage, and the noise amplified by the amplifier. A time constant circuit that smoothes components with a predetermined time constant to generate the control voltage, and generates a pulse with a predetermined width at the timing when the voltage level of the noise component amplified by the amplifier becomes equal to or higher than a predetermined reference voltage. A pulse generation circuit that outputs the input signal after delaying the input signal for a predetermined time, and a signal that is output from the delay circuit at the timing immediately before the pulse generated by the pulse generation circuit is input. And an output circuit that holds the signal output from the delay circuit as it is at other times. In the noise removal circuit, the time constant circuit includes a capacitor, a voltage comparator that compares a terminal voltage of the capacitor with an input voltage, and if the input voltage is relatively higher than the terminal voltage, A charging circuit that intermittently charges the capacitor; and a discharging circuit that intermittently discharges a discharging current from the capacitor when the terminal voltage is relatively lower than the input voltage. Noise removal circuit to be. 2. The noise elimination circuit according to claim 1, wherein a full-wave rectification circuit for full-wave rectifying the noise component output from the amplifier is inserted after the amplifier. 3. The charging circuit according to claim 1, wherein the charging circuit controls a timing of a current supply section that supplies a predetermined charging current to the capacitor, and an intermittent supply operation of the charging current by the current supply section. The discharge circuit includes a first timing control unit, the discharge circuit discharges a predetermined discharge current from the capacitor, and the discharge discharge timing of the discharge current by the current discharge unit is intermittent. And a second timing control section for controlling the noise reduction circuit. 4. The time constant circuit according to claim 3, wherein the intermittent supply time of the charge current and the intermittent discharge time of the discharge current controlled by the first and second timing control units are different. A noise removing circuit further comprising a charge / discharge speed setting means. 5. The device according to claim 4, wherein each of the first and second timing control units is
The charging / discharging speed setting means has a switch for controlling the timing based on a pulse signal having a predetermined duty ratio, and the charging / discharging speed setting unit has a duty ratio of the pulse signal for charging and a duty of the pulse signal for discharging. A noise removal circuit characterized by having different ratios. 6. The charging / discharging speed setting means according to claim 3, wherein the time constant circuit further comprises a charging / discharging speed setting means for differentiating a charging current supplied by the current supply unit and a discharging current discharged by the current discharging unit. Characteristic noise removal circuit. 7. The charging / discharging speed setting unit according to claim 6, wherein each of the current supply unit and the current emission unit is formed of a transistor having a gate to which a predetermined reference voltage is applied. 2. The noise removing circuit, wherein the transistor and the discharging transistor have different gate dimensions.