JP3910828B2 - Signal detection circuit and muting circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal detection circuit and a muting circuit that detect a signal having a specific frequency.
[0002]
[Prior art]
In the FM receiver, a large noise is generated when there is no broadcast wave. A muting circuit checks the presence or absence of a carrier wave in order to suppress the generation of this noise. This muting circuit is provided in the subsequent stage of the FM detection circuit. In principle, it is possible to determine the presence or absence of a carrier wave by smoothing the signal after FM detection and detecting the DC voltage level. Become.
[0003]
[Problems to be solved by the invention]
In the conventional muting circuit, a low-pass filter having a large time constant is used to smooth the signal. In other words, it is necessary to set the element constant of the capacitor or resistor that constitutes the low-pass filter to a large value, and considering the increase in the area occupied by these elements, the entire muting circuit is integrally formed on the semiconductor substrate together with other circuits. There was a problem that could not be done. Further, not only the muting circuit but also a signal detection circuit that detects a carrier wave when performing a so-called auto-scan process that detects a broadcast wave while sweeping the reception frequency has the same problem.
[0004]
The present invention has been made in view of such a point, and an object thereof is to provide a signal detection circuit and a muting circuit that can be integrally formed on a semiconductor substrate.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problems, a signal detection circuit according to the present invention includes a time constant circuit for extracting a center voltage of a signal after FM detection by smoothing an input signal with a predetermined time constant, and a time constant circuit. And a voltage detection circuit for detecting that the output voltage is included in a predetermined range. The time constant circuit also includes a capacitor, a voltage comparator that compares the terminal voltage of the capacitor with the input voltage, and the capacitor intermittently when the input voltage is relatively higher than the terminal voltage. Charging circuit for charging, a discharging circuit for intermittently discharging a discharging current from the capacitor when the terminal voltage is relatively higher than the input voltage , and intermittent charging current by the charging circuit Charging / discharging rate setting means for differentiating the general supply time and the intermittent discharge time of the discharge current by the discharge circuit . Since the capacitor is intermittently charged and discharged, even when the capacitance of the capacitor is reduced, the terminal voltage changes gently, and an equivalently large time constant can be set. Therefore, even when a capacitor with a small capacitance is used, a large time constant can be set in the time constant circuit in the signal detection circuit, and the entire signal detection circuit can be integrally formed on the semiconductor substrate. It becomes.
[0006]
In addition, the charging circuit includes a current supply unit that supplies a predetermined charging current to the capacitor, and a first timing control unit that controls the timing of the intermittent supply operation of the charging current by the current supply unit. It is desirable to configure the discharge circuit including a current discharge unit that discharges a predetermined discharge current from the capacitor and a second timing control unit that controls the timing of the intermittent discharge operation of the discharge current by the current discharge unit. The intermittent discharge operation of the capacitor can be easily controlled by controlling the timing of the charging current supply operation by the current supply unit and the timing of the discharge current discharge operation by the current discharge unit.
[0007]
The time constant circuit described above further includes charge / discharge rate setting means for making the charge current intermittent supply time and the discharge current intermittent discharge time controlled by the first and second timing control units different. It is desirable. By providing the charge / discharge rate setting means, the charge rate and the discharge rate for the capacitor in the time constant circuit can be made different, so the time from when the signal to be detected is detected until it is detected, It is possible to vary the time until it is detected that input is no longer being performed.
[0008]
In addition, when each of the first and second timing control units has a switch that performs timing control based on a pulse signal having a predetermined duty ratio, the charge / discharge speed setting unit described above is charged It is desirable to make the duty ratio of the pulse signal for use different from the duty ratio of the pulse signal for discharge. Thereby, the control which makes charge time and discharge time different becomes easy.
[0009]
The time constant circuit described above preferably further includes charge / discharge rate setting means for differentiating the charging current supplied by the current supply unit and the discharging current released by the current emission unit. As a result, the time from when the signal to be detected is input until it is detected can be easily made different from the time until it is detected that this signal is no longer input.
[0010]
In addition, when each of the current supply unit and the current discharge unit is configured by a transistor to which a predetermined reference voltage is applied to the gate, the charge / discharge speed setting unit described above includes a charge transistor and a discharge transistor. It is desirable to have different gate dimensions. Thereby, the control which makes a charging current value and a discharging current value different becomes easy.
[0011]
The muting circuit of the present invention has switching means for controlling the intermittentness of the input signal when the carrier signal component of the input signal is detected by the signal detection circuit described above. Since the entire signal detection circuit including the time constant circuit can be integrally formed on the semiconductor substrate, the entire muting circuit can also be integrally formed on the semiconductor substrate.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a muting circuit according to an embodiment to which the present invention is applied will be described in detail.
FIG. 1 is a diagram showing a partial configuration of an FM receiver including a muting circuit according to the present embodiment. The FM receiver shown in FIG. 1 includes an intermediate frequency amplifier circuit 11, a π / 2 phase shifter 12, a multiplier 13, a low-pass filter (LPF) 14, and a muting circuit 15.
[0013]
The intermediate frequency amplifier circuit 11 amplifies the intermediate frequency signal after passing through an intermediate frequency filter (not shown). The π / 2 phase shifter 12 includes a capacitor 20, a parallel resonance circuit including a capacitor 21 and one end connected to the rear end of the capacitor 20, and a coil 22. The phase of the input signal is π / 2. shift. The multiplier 13 multiplies the intermediate frequency signal output from the intermediate frequency amplifier 11 and a signal obtained by shifting the phase of the intermediate frequency signal by π / 2 phase shifter 12 by π / 2. The low-pass filter 14 removes unnecessary high frequency components contained in the output signal of the multiplier 13. These π / 2 phase shifter 12, multiplier 13 and low-pass filter 14 constitute a quadrature detection circuit.
[0014]
The muting circuit 15 has a function of a signal detection circuit that detects the presence / absence of a carrier wave component included in the input signal, and cuts off the signal after FM detection output from the low-pass filter 14 according to the detection result. Or let it pass. For this purpose, the muting circuit 15 includes a time constant circuit 100, a window comparator (WC) 30, an FET 40, and a load resistor 41.
[0015]
The time constant circuit 100 smoothes the signal input from the multiplier 13 with a predetermined time constant. The window comparator 30 is a voltage detection circuit that detects that the output voltage of the time constant circuit 100 is included in a predetermined voltage range. The window comparator 30 includes resistors 31, 32 and 33, voltage comparators 34 and 35, and a NOR circuit 36. A voltage dividing circuit is configured by the three resistors 31, 32, and 33 connected in series. The voltage comparator 34 compares the voltage V1 at the connection point of the resistors 31 and 32 with the output voltage V of the time constant circuit 100, and sets the output to a high level when the output voltage V is higher. The voltage comparator 35 compares the voltage V2 at the connection point of the resistors 32 and 33 with the output voltage V of the time constant circuit 100, and sets the output to the high level when the output voltage is lower. The NOR circuit 36 receives the respective output signals of the two voltage comparators 34 and 35, and when these two output signals are both at the low level, that is, the output voltage V of the time constant circuit 100 is the voltages V1 to V1. The output goes high when included in the range of V2.
[0016]
FIG. 2 is a diagram showing the relationship between the frequency of the intermediate frequency signal output from the intermediate frequency amplifier circuit 11 and the voltage after detecting the frequency. Assuming that the frequency of the carrier wave included in the intermediate frequency signal is f0, when there is a carrier wave component corresponding to the broadcast wave, the frequency f of the intermediate frequency signal changes around the frequency f0 of the carrier wave. Therefore, when a broadcast wave exists, the output voltage of the time constant circuit 100 is included in a predetermined range centered on a predetermined voltage corresponding to the frequency f0 of the carrier wave. For example, this output voltage is included in a range of ± ΔV centered on Vdd / 2, that is, a range from Vdd / 2−ΔV (= V2) to Vdd / 2 + ΔV.
[0017]
The FET 40 is a switching element that is turned on when the output of the NOR circuit 36 in the window comparator 30 is at a high level and is turned off when the output is at a low level, and passes the signal after detection output from the low-pass filter 14. Or shut off.
[0018]
FIG. 3 is a diagram illustrating a principle block of the time constant circuit 100. As shown in FIG. 3, the time constant circuit 100 of this embodiment includes a capacitor 110, a voltage comparator 112, a charging circuit 114, a discharging circuit 116, and a charge / discharge rate setting unit 118. The voltage comparator 112 compares the terminal voltage of the capacitor 110 with the input voltage, and validates the operation of the charging circuit 114 or the discharging circuit 116 according to the comparison result. The charging circuit 114 charges the capacitor 110 by intermittently supplying a charging current. For example, the charging circuit 114 includes a constant current circuit and a switch, and a charging current is supplied from the constant current circuit to the capacitor 110 when the switch is turned on. In addition, the discharge circuit 116 discharges the capacitor 110 by passing a discharge current intermittently. For example, the discharge circuit 116 includes a constant current circuit and a switch, and a constant current is discharged from the capacitor 110 when the switch is turned on. The charging / discharging speed setting unit 118 sets the charging speed of the capacitor 110 by the charging circuit 114 and the discharging speed of the capacitor 110 by the discharging circuit 116. The charging / discharging speed setting unit 118 corresponds to charging / discharging speed setting means, and specific contents will be described later.
[0019]
As described above, the time constant circuit 100 of the present embodiment performs an intermittent charge / discharge operation on the capacitor 110. For this reason, even when the capacitance of the capacitor 110 is set to be small, the voltage at both ends thereof gradually changes, and the charge / discharge characteristics equivalent to those when a circuit having a large time constant, that is, a capacitor having a large capacitance is used. Can be obtained. Further, the charging circuit 114 and the discharging circuit 116 perform control to supply a predetermined current to the capacitor 110 or release it from the capacitor 110. Since these supply and discharge operations are performed intermittently, the current value at that time Can be set to a somewhat large value suitable for IC implementation. Therefore, the entire muting circuit 15 including the time constant circuit 100 can be formed into a semiconductor substrate to be integrated into an IC. Further, since no external parts such as capacitors are required, the entire muting circuit 15 can be greatly reduced in size.
[0020]
Further, the time constant circuit 100 of the present embodiment is set by the charge / discharge rate setting unit 118 so that the charge rate and the discharge rate for the capacitor 110 are different. Therefore, by varying the time constant of the time constant circuit 100 in this way, the time from detecting the carrier component of the broadcast wave to canceling the muting of the detection output is set short, and the broadcast wave It is possible to set a long time from the detection of the absence of the carrier wave component to the start of muting for the detection output.
[0021]
FIG. 4 is a circuit diagram showing a specific configuration of the time constant circuit 100. As shown in FIG. 4, the time constant circuit 100 includes a capacitor 110, a constant current circuit 140, FETs 142, 144, 150, 154, 156, switches 146, 152, a voltage comparator 160, AND circuits 162, 164, and a frequency divider. 170 is comprised.
[0022]
A current mirror circuit is configured by the two FETs 142 and 144, and the same charging current as the constant current output from the constant current circuit 140 is generated. In addition, the generation timing of this charging current is determined by the switch 146.
The switch 146 includes an inverter circuit 1, an analog switch 2, and an FET 3. The analog switch 2 is configured by connecting the source and drain of a p-channel FET and an n-channel FET in parallel. The output signal of the AND circuit 162 is directly input to the gate of the n-channel FET, and a signal obtained by inverting the logic of this output signal by the inverter circuit 1 is input to the gate of the p-channel FET. Therefore, the analog switch 2 is turned on when the output signal of the AND circuit 162 is at a high level, and is turned off when it is at a low level. The FET 3 is for reliably stopping the current supply operation by the FET 144 by connecting the gate and drain of the FET 144 with a low resistance when the analog switch 2 is in the OFF state.
[0023]
When the switch 146 is turned on, the gate of one FET 142 to which the constant current circuit 140 is connected and the gate of the other FET 144 are connected to each other. Therefore, the switch 146 is generated by the constant current circuit 140 connected to the one FET 142. The same current as the constant current that flows is also passed between the source and drain of the other FET 144. This current is supplied to the capacitor 110 as a charging current. On the other hand, when the switch 146 is turned off, the gate of the FET 144 is connected to the drain, and the supply of the charging current is stopped.
[0024]
The constant current circuit 140 and the two FETs 142 and 144 described above correspond to the current supply unit. The switch 146 and the AND circuit 162 correspond to the first timing control unit.
In addition, by combining the FET 150 with the FET 142 and the constant current circuit 140 described above, a current mirror circuit for setting the discharge current of the capacitor 110 is configured, and the operation state is determined by the switch 152. The switch 152 has the same configuration as the switch 146. The switch 152 is controlled to be turned on and off according to the logic of the output signal of the AND circuit 164. The switch 152 is turned on when the output signal is at a high level, and turned off when the output signal is at a low level.
[0025]
When the switch 152 is turned on, the gate of one FET 142 to which the constant current circuit 140 is connected and the gate of the other FET 150 are connected, so that the constant current generated by the constant current circuit 140 is almost the same. Current also flows between the source and drain of the other FET 150. This current becomes a discharge current that releases the charge accumulated in the capacitor 110.
[0026]
However, since the current flowing through the FET 150 cannot be directly taken out from the capacitor 110, in this embodiment, another current mirror circuit constituted by the FETs 154 and 156 is connected to the source side of the FET 150.
The gates of the two FETs 154 and 156 are connected to each other, and the same current flows between the source and drain of the other FET 156 when the above-described discharge current flows to the FET 154. The FET 156 has a drain connected to the terminal on the high potential side of the capacitor 110, and a current flowing through the FET 156 is generated by discharging the charge accumulated in the capacitor 110.
[0027]
The constant current circuit 140 and the four FETs 142, 150, 154, and 156 described above correspond to the current emission unit. The switch 152 and the AND circuit 164 correspond to the second timing control unit.
The voltage comparator 160 compares the terminal voltage of the capacitor 110 applied to the plus terminal with the input voltage of the time constant circuit 100 applied to the minus terminal. The voltage comparator 160 includes a non-inverting output terminal has an inverting output terminal, inversion is higher than the input voltage towards the terminal voltage of the capacitor 110 which is applied to the plus terminal is applied to the negative terminal A high level signal is output from the output terminal, and a low level signal is output from the non-inverting output terminal . Conversely, the signal from the inverting output terminal of a low level is output when lower than the input voltage towards the terminal voltage of the capacitor 110 which is applied to the plus terminal is applied to the minus terminal, a high level from the non-inverting output terminal Is output.
[0028]
In the AND circuit 162, a predetermined pulse signal is input to one input terminal, and the non-inverting output terminal of the voltage comparator 160 is connected to the other input terminal. Therefore, when the terminal voltage of the capacitor 110 is lower than the input voltage of the time constant circuit 100, a predetermined pulse signal is output from the AND circuit 162.
[0029]
In the AND circuit 164, a predetermined pulse signal output from the frequency divider 170 is input to one input terminal, and the inverting output terminal of the voltage comparator 160 is connected to the other input terminal. Therefore, when the terminal voltage of the capacitor 110 is higher than the input voltage of the time constant circuit 100, a predetermined pulse signal is output from the AND circuit 164. The frequency divider 170 described above corresponds to the charge / discharge rate setting means.
[0030]
The frequency divider 170 divides the pulse signal input to one input terminal of the AND circuit 162 by a predetermined frequency dividing ratio and outputs the result. As described above, the divided pulse signal is input to one input terminal of the AND circuit 164.
The time constant circuit 100 has such a configuration, and the operation thereof will be described next.
[0031]
When the capacitor 110 is not charged at the start of the operation of the time constant circuit 100, or when the input voltage of the time constant circuit 100 tends to increase, the terminal voltage of the capacitor 110 is higher than the input voltage of the time constant circuit 100. Is also low. At this time, a pulse signal is output from the AND circuit 162, and no pulse signal is output from the AND circuit 164. Accordingly, only the switch 146 is intermittently turned on, and a predetermined charging current is supplied to the capacitor 110 at the timing when the switch 146 is turned on. This charging operation is continued until the terminal voltage of the capacitor 110 becomes relatively higher than the input voltage of the time constant circuit 100.
[0032]
Further, when the terminal voltage of the capacitor 110 exceeds the input voltage of the time constant circuit 100 due to this charging operation, or when the input voltage tends to decrease and the input voltage is lower than the terminal voltage of the capacitor 110. A pulse signal is output from the AND circuit 164, and no pulse signal is output from the AND circuit 162. Accordingly, only the switch 152 is intermittently turned on, and a predetermined discharge current is discharged from the capacitor 110 at the timing when the switch 152 is turned on. This discharging operation is continued until the terminal voltage of the capacitor 110 becomes relatively lower than the input voltage of the time constant circuit 100.
[0033]
Further, when the two types of pulse signals output from the two AND circuits 162 and 164 described above are compared, the duty ratio of the pulse signal output from the AND circuit 162 is greater than the duty ratio of the pulse signal output from the AND circuit 164. When the pulse signal is output from each of the two AND circuits 162 and 164 for the same time because the ratio is larger than the ratio, the charge rate per unit time is faster than the discharge rate. For this reason, the attack time is shorter than the release time.
[0034]
In the time constant circuit 100 described above, the frequency divider 170 is used to output pulse signals having different duty ratios from the two AND circuits 162 and 164. However, pulse signals having different duty ratios are generated separately. You may make it input into each of two AND circuit 162,164. In addition, by inserting the frequency divider 170 on one input end side of the AND circuit 164, the discharge time is set to be slower than the charge time of the capacitor 110. In order to delay the charging time, the frequency divider 170 may be inserted on one input end side of the AND circuit 162. Alternatively, by removing the frequency divider 170, the charging time and discharging time of the capacitor 110 can be made the same.
[0035]
In the time constant circuit 100 described above, in order to make the charging speed and discharging speed for the capacitor 110 different, the ratios per unit time at which the FETs 144 and 150 are turned on are made different. By changing the dimensions, the charging current and the discharging current may be made different.
[0036]
FIG. 5 is a circuit diagram showing a modification of the time constant circuit. The time constant circuit 100A shown in FIG. 5 is different from the time constant circuit 100 shown in FIG. 4 in that the frequency divider 170 is deleted and the two FETs 144 and 150 are changed to two FETs 144A and 150A whose gate dimensions are changed. The point I did is different.
[0037]
FIG. 6 is a diagram showing gate dimensions of a MOS type FET (FET). Even if the gate voltage is the same, changing the gate width W and the gate length L changes the channel resistance, so that the current flowing between the source and the drain changes. In this embodiment, in order to increase the charging current and shorten the attack time, the gate width W of the FET 144A is set to a large value and the gate length L is set to a small value. On the other hand, in order to reduce the discharge current and increase the release time, the gate width W of the FET 150A is set to a small value and the gate length L is set to a large value. As described above, the charging time and discharging time of the capacitor 110 can be easily changed by changing the gate dimensions of the FETs 144A and 150A. In this case, the FETs 144A and 150A constitute a part of the charging circuit 114 and the discharging circuit 116 and have a function as charge / discharge rate setting means.
[0038]
【The invention's effect】
As described above, according to the present invention, since the capacitor is intermittently charged / discharged, the terminal voltage gradually changes even when the capacitance of the capacitor is reduced, and is equivalently large. A time constant can be set. Therefore, even when a capacitor with a small capacitance is used, a large time constant can be set for the signal detection circuit and the time constant circuit in the muting circuit. It can be integrally formed on the top.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a partial configuration of an FM receiver including a muting circuit according to an embodiment.
FIG. 2 is a diagram illustrating a relationship between a frequency of an intermediate frequency signal and a detection output voltage.
FIG. 3 is a diagram showing a principle block of a time constant circuit.
FIG. 4 is a circuit diagram showing a specific configuration of a time constant circuit.
FIG. 5 is a circuit diagram showing a modification of the time constant circuit.
FIG. 6 is a diagram showing gate dimensions of a MOS type FET.
[Explanation of symbols]
11 Intermediate Frequency Amplifier 12 π / 2 Phase Shifter 13 Multiplier 14 Low Pass Filter (LPF)
15 Muting circuit 30 Window comparator (WC)
31, 32, 33 Resistance 34, 35 Voltage comparator 36 NOR circuit 40 FET
100 Time constant circuit 112, 160 Voltage comparator 114 Charging circuit 116 Discharging circuit 140 Constant current circuit 142, 144, 150, 154, 156 FET
146, 152 Switch 162, 164 AND circuit 170 Frequency divider

Claims (5)

A time constant circuit that extracts the center voltage of the signal after FM detection by smoothing the input signal with a predetermined time constant, and a voltage that detects that the output voltage of the time constant circuit is included in a predetermined range In a signal detection circuit having a detection circuit,
The time constant circuit is:
A capacitor,
A voltage comparator for comparing the terminal voltage of the capacitor and the input voltage;
A charging circuit that intermittently charges the capacitor when the input voltage is maintained at a relatively higher state than the terminal voltage;
A discharge circuit that intermittently discharges a discharge current from the capacitor when the terminal voltage is maintained relatively higher than the input voltage; and
Charging / discharging speed setting means for differentiating the intermittent supply time of the charging current by the charging circuit and the intermittent discharge time of the discharging current by the discharge circuit;
A signal detection circuit comprising: In claim 1,
The charging circuit includes a current supply unit that supplies a predetermined charging current to the capacitor, and a first timing control unit that controls the timing of an intermittent supply operation of the charging current by the current supply unit. And
The discharge circuit includes a current discharge unit that discharges a predetermined discharge current from the capacitor, and a second timing control unit that controls the timing of the intermittent discharge operation of the discharge current by the current discharge unit. A signal detection circuit. In claim 2,
The charge / discharge speed setting means makes the charge current intermittent supply time controlled by the first and second timing control sections different from the discharge current intermittent discharge time. . In claim 3,
Each of the first and second timing control units has a switch for controlling the timing based on a pulse signal having a predetermined duty ratio,
The signal detection circuit, wherein the charge / discharge speed setting means makes the duty ratio of the pulse signal for charging different from the duty ratio of the pulse signal for discharge. 5. A muting circuit, further comprising switching means for blocking or passing the input signal based on a detection result of the voltage detection circuit, following the signal detection circuit according to claim 1 .

Images