JP2003141501A - Image processing apparatus, method for controlling display part thereof, program, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an initial display or an appropriate error display in a display part even if a main CPU has difficulty in controlling the display of the display part, as when the main CPU is being started or when it is malfunctioning, by displaying a complicated screen at high speed on an operating part by means of the main CPU when the main CPU is operating normally. SOLUTION: When the main CPU 101 running a principal program has difficulty in directly controlling an LCD 111 for plotting a sub CPU 108 operating independently of the operating state of the main CPU 101 directly controls the LCD 111 for slotting on a predetermined screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a copying machine, a printer or a facsimile having an operation section capable of displaying a complicated image, a display section control method, a program and a recording medium for the image processing apparatus. is there.

[0002]

2. Description of the Related Art Conventionally, in copying machines, printers, and facsimiles, a liquid crystal display (L
A display unit using a CD) is provided, and various messages are displayed on the display unit.

FIG. 8 is a block diagram showing a configuration of a conventional image processing apparatus, and shows a circuit configuration of a printer as an example.

In the figure, 701 is a high-speed main CPU
(MAIN CPU) controls the entire apparatus based on a program stored in the ROM 702 or other storage medium. A RAM 703 is used as a work area of the main CPU 701 and stores data and image signals. 705 is an accelerator (ACCELERATO
R) improves a predetermined function (for example, a graphic function). 706 is a host interface (HOST
The I / F) controls communication with the host computer (HOST PC). A printer interface (PRINTER I / F) 704 is a printer (PRINT I / F).
ER) 708 to control communication. A serial communication controller (UART) 707 controls serial communication with the sub control unit 709.

In the sub control unit 709, a low speed sub CPU (SUB CPU) 709-4 is a ROM 709-
2 or the entire sub-control unit 709 is controlled based on a program stored in another storage medium. 709-3 is RA
M, which is used as a work area of the sub CPU 709-4. Further, the sub CPU 709-4 is used for displaying the LCD 710 capable of displaying a character message of two lines and detecting the key input of the key (KEY) 711.

Further, the sub CPU 709 section is an I / O 70
9-6, an LCD controller 709-5, and a serial communication controller (UART) 709-1. The LCD controller 709-sets the settings according to the contents instructed by the command sent from the main CPU 701 through the serial communication. 5 to display a predetermined message on the LCD 710 and press the key (KEY) 71
The key input from the main CPU 7 by serial communication
Send to 01. Further, in this configuration, the main CPU 7
When communication between 01 and the sub CPU 709 is interrupted, an error message can be displayed on the LCD 710.

Further, in an image processing apparatus (another conventional example) having a configuration different from that of the above-mentioned conventional example, the LCD has 640 dots × 4.
In some cases, a high-speed main CPU directly controls the LCD controller by itself in order to display a complicated screen at high speed by using a color display device of 80 dots (that is, a large screen).

[0008]

In the conventional image processing apparatus shown in FIG. 8, the sub CPU 709-4 for drawing is a low-speed one and communication between CPUs (serial communication) is performed.
Although it is suitable for drawing a relatively simple screen due to the limitation of speed, etc., it is not suitable for drawing a complicated figure on a large display screen.

On the other hand, as in the image processing apparatus shown in another conventional example, in the system in which the high-speed main CPU directly controls the LCD controller, complicated drawing can be performed on a large screen at high speed. There has been a problem that it is difficult to display an appropriate operation unit screen when a display of a program in the main CPU is being activated or when an abnormality occurs in the main CPU or other components.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a direct drawing control to a display unit by a main CPU executing a main program when it is difficult. The sub CPU that operates independently of the operating state of the main CPU directly controls the drawing of the display unit, so that a complicated screen can be displayed at high speed on the operation unit during normal operation when the main CPU is operating.
When it is difficult to control the display unit by the main CPU, such as when the main CPU is starting up or malfunctions, the sub CPU can display an appropriate error and the image processing device and the display of the image processing device. A part control method, a program, and a storage medium are provided.

[0011]

A first invention according to the present invention is a first control means for executing a main program (see FIG. 1).
CPU core 201 in MAIN CPU 101 shown in FIG.
(FIG. 2)) and second control means (SUBCPU1 shown in FIG. 1) that operates independently of the operating state of the first control means.
08 CPU core (FIG. 3)) and display means (L shown in FIG. 1) capable of direct drawing control from the first and second control means.
CD111), and the second control means controls the display of a predetermined screen on the display means when it is difficult for the first control means to control the display means. .

A second invention according to the present invention is characterized in that the case where it is difficult for the first control means to control the display means is before the completion of activation of the first control means. To do.

A third invention according to the present invention is characterized in that the second control means completes activation in a shorter time than the first control means when power is turned on.

According to a fourth aspect of the present invention, the case where it is difficult for the first control means to control the display means is a case where an abnormality occurs in the first control means. Characterize.

According to a fifth aspect of the present invention, there is provided first control means for executing a main program, second control means for operating independently of an operating state of the first control means, and the second control means. A display unit control method for an image processing apparatus, comprising: a display unit capable of direct drawing control from the first and second control units,
When it is difficult for the first control unit to control the display unit, the second control unit displays a predetermined screen on the display unit (steps S401 to S401 in FIG. 4).
403, S405 to S407 and step S50 of FIG.
2, step S404 in FIG. 4 and step S50 in FIG.
3 to S504, when there are other errors (not shown) and steps S603 to S604 in FIG. 6).

In a sixth aspect of the present invention, the case where it is difficult for the first control means to control the display means is before the completion of the activation of the first control means (see FIG. 4). It is characterized in that steps S401 to S403, S405 to S407 and step S502 in FIG. 5).

A seventh aspect of the present invention is characterized in that the second control means completes activation in a shorter time than the first control means when the power is turned on.

In an eighth aspect of the present invention, the case where it is difficult for the first control means to control the display means is a case where an abnormality occurs in the first control means (FIG. 4 step S404 and FIG. 5 step S50.
3 to S504, when another error (not shown) occurs and steps S603 to S604 in FIG. 6).

The ninth invention according to the present invention is defined by claims 5 to 8.
It is a program that realizes the display unit control method of the image processing apparatus described in any one of the above.

The tenth invention according to the present invention is defined by claims 5 to 5.
A program for executing the display unit control method of the image processing apparatus described in any one of 8 is stored in a storage medium in a computer-readable manner.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an image processing apparatus showing an embodiment of the present invention.

In the figure, 100 is a main controller, 101 is a main processor (main CPU (MAIN CP).
U)), 102 is a memory (RAM), 103 is a non-volatile memory (ROM), 104 is a hard disk, 105 is an image processing circuit, 106 is a scanner, and 107 is a printer unit (printer).

Further, 120 is a sub-control unit, 108 is a sub-processor (sub-CPU (SUB CPU)), the internal bus of this sub-CPU 108 is connected to the main CPU 101, as shown in FIG. Sub CPU1
It is possible to directly control each device that is connected to the 08 from the main CPU 101. 109 is a RAM for the sub CPU (RA
M), 110 is a sub CPU ROM (ROM), 111
Is a liquid crystal display (LCD), 112 is an operation key (Ke
y) and 113 are power supply units (power supplies).

The operation will be described below.

The main CPU 101 mainly controls the image processing apparatus. When the main CPU 101 is in a normal program execution state, it controls each part according to the program read into the RAM 102. In accordance with an instruction from the user through the operation keys 112, the scanner unit 106 reads a document image, the image processing circuit 105 performs predetermined image processing, and the printer unit 107 performs an image forming operation to copy the document. To do.

The main CPU 101 has a RAM 10
A predetermined operation is performed by writing image data in a predetermined area (area used as a video memory by an LCD controller (LCD controller 303 shown in FIG. 3 described later) incorporated in the sub CPU 108) The partial screen can be displayed on the LCD 111.

The sub CPU 108 also includes a network controller (LAN I / F shown in FIG. 3 which will be described later).
305) is built in, and the main CPU 101 can perform communication via a local area network (LAN) by using this network controller.

The main CPU 101 is a sub CPU.
The power supply unit 113 can be controlled via 108 to turn itself off (main control unit 100).

FIG. 2 shows the main CPU 101 shown in FIG.
3 is a block diagram showing in more detail the internal configuration of FIG.

In the figure, 201 is a CPU core, and 202
Is a bus bridge, 203 is a memory controller, and 204
Is an image input / output interface circuit (VIDEO I /
F), 205 is a PCI interface circuit (PCI I / F) which is a peripheral circuit interface, 2
Reference numeral 06 is a hard disk controller.

The CPU core 201 is the core of the main CPU 101 that executes programs, and
It is a high-speed 64-bit CPU operating at MHz. Further, the CPU core 201 can access other constituent elements via the bus bridge 202.

The bus bridge 202 is the main CPU 10
It is a crossbar switch that mediates the transfer of data between the other constituent elements within 1, and when data transfer occurs, it arbitrates the right to use the bus and transfers the data to the target constituent element. The memory controller 203 is a circuit for generating signals such as an address bus / data bus and READ / WRITE at a predetermined timing so that the RAM 102 and the ROM 103 can be accessed by the main CPU 101 and others, and is composed of a SYNCRONOUS DRAM.
The refresh operation of the AM 102 is also executed.

Image input / output interface circuit (VID
An EO I / F) 204 is a circuit for transferring image data to and from the image processing circuit 105, and stores data input by a built-in DMA controller (not shown) in the RAM 102 via the memory controller 203. Conversely, the image data on the RAM 102 is read by the DMA controller via the memory controller 203 and output to the image processing circuit 105.

PCI interface circuit (PCI I
The / F) 205 is a circuit for generating various signals specified in the PCI bus standard and transferring data to and from the PCI bus when the main CPU 101 accesses the PCI bus.

The hard disk controller 206 generates a signal relating to access to the hard disk 104, and uses a built-in DMA (not shown) for the hard disk 10.
Data is input and output between the RAM 4 and the RAM 102.

FIG. 3 is a block diagram showing a more detailed internal structure of the sub CPU 108 shown in FIG.

In the figure, 301 is a CPU core, and 302 is
Is a memory controller, 303 is an LCD controller,
Reference numeral 304 is an I / O controller, 305 is a LAN controller (LAN I / F), and 306 is a PCI interface (PCI I / F).

The CPU core 301 is a low-speed 16-bit CPU operating at 10 MHz, and executes the program stored in the ROM 110 connected via the memory controller 302.

The memory controller 302 is a sub CPU
The signal necessary for accessing the RAM 109 and the ROM 110 from the internal bus of 108 is generated. L
The CD controller 303 is a DMA controller (not shown) that incorporates the display image written on the RAM 109.
Is read out and output to the LCD 111 to display the operation unit screen. The data representing the screen of the operation unit of the LCD 111 is normally written by the main CPU 101, but the CPU core 301 of the sub CPU 108 can also write the data.

The I / O controller (I / O) 304 is
It is an input / output port for detecting a key input of the operation key (KEY) 112 and controlling the operation of the power supply unit 113.

The LAN controller 305 is a circuit that mediates data transfer to the LAN. The PCI interface (PCI I / F) 306 has a function of transmitting an access from the PCI bus side to the internal bus of the sub CPU 108, and accesses each unit inside the sub CPU 108 from the main CPU 101 via the PCI bus. be able to. Using this function, the main CPU 101 can directly control the function of each part of the sub CPU 108 during normal operation, and the CPU core 3 of the sub CPU 108 can be controlled.
01 is in a standby state unless particularly necessary. That is, the LCD is displayed from both the main CPU 101 and the sub CPU 108.
It is possible to directly control the drawing of 111.

Hereinafter, with reference to the flowchart of FIG.
The operation when the power is turned on will be described.

FIG. 4 is a flow chart showing an example of the first control processing procedure of the present invention, and corresponds to the flow of processing when the main CPU 101 is activated.

When the power of the apparatus is turned on, the CPU 101
The execution of the boot program stored in the OM 103 is started.

This startup program is executed in step S401.
Then, the bus bridge 202, the memory controller 203, the hard disk controller 206, etc. in the main CPU 101 are initialized, and the initial diagnosis of the device is performed in step S402.

In step S403, the diagnosis result is normal (O
K), and if it is not normal (OK), the program execution is stopped in step S404.

On the other hand, if it is determined in step S403 that the diagnosis result is normal (OK), step S405.
Then, the operation of reading the program file stored in the hard disk 104 into the RAM 102 is performed. This program file is the execution program main body that describes the operation of the image processing apparatus, and the startup program normally read on the RAM 102 jumps to the start address of the execution program in step S406 and shifts to normal program execution. To do.

After the main CPU 101 starts executing the normal program and the initialization operation of the program is completed in step S407, the sub-CP is executed in step S408.
The U108 is notified of the completion of activation. After this, the LCD 11
The entity that writes the data to be displayed in 1 to the RAM 109 is
From the CPU core 301 of the sub CPU 108 to the main CPU
It is replaced by the CPU core 201 of 101, and the program of the main CPU 101 takes charge of displaying an image.

Hereinafter, with reference to the flowchart of FIG.
The flow of the startup processing of the sub CPU 108 that is executed in parallel with the startup operation of the main CPU 101 shown in FIG. 4 will be described.

FIG. 5 is a flow chart showing an example of the second control processing procedure of the present invention, which corresponds to the flow of processing when the sub CPU 108 is activated.

The execution program of the sub CPU 108 is RO
Since it is stored in M110, the execution of the normal program is started immediately when the reset is released after the power is turned on. The sub CPU 108 is the main CPU 1 after the power is turned on.
Start-up is completed in a shorter time than 01.

In step S501, the I / O controller (I / O) 304 and the memory controller 302 are initialized, and in step S502, the LC on the RAM 109 is initialized.
Write the initial screen data to be displayed in D111
The CD controller 303 is initialized and the display of the initial screen on the LCD 111 is started. At this point, it's still main C
PU101 is starting up and L from main CPU101
This is because it is difficult to control the display of the CD 111.

Subsequently, the sub CPU 108
The state of waiting for the reception of the activation completion notification from the main CPU 101 is entered. In steps S503 and S505, the main CP
When it is determined whether or not the predetermined time has passed without the start completion notification from U101 and the predetermined time has passed without the start completion notification from the main CPU 101 (some abnormality (error) in the main CPU 101) Is determined to have occurred, the LCD from the main CPU 101
When it is determined that the display control of 111 is difficult),
An error screen is displayed on the LCD 111 (S504), and the program execution is stopped in step S506.

On the other hand, in steps S503 and S505, it can be determined that the activation completion notification has been sent from the main CPU 101 within a predetermined time (when it is determined that the display control of the LCD 111 can be performed from the main CPU 101). ), The CPU core 301 of the sub CPU 108 shifts to the standby mode.

Hereinafter, with reference to the flowchart of FIG.
A process flow of the sub CPU 108 shown in FIG. 3 in the standby mode will be described.

FIG. 6 is a flowchart showing an example of the third control processing procedure of the present invention, which corresponds to the processing flow of the sub CPU 108 in the standby mode.

When the sub CPU 108 enters the standby mode,
After waiting for a certain time (WAIT) in step S601, a communication command is issued to the main CPU 101 in step S602, and the main C is issued in step S603.
Check if there is a response from the PU 101. When it is determined that there is no response, it is determined that a problem has occurred in the program execution of the main CPU 101, an error screen is displayed on the LCD 111 in step S604, and the program execution is stopped in step S605.

On the other hand, in step S603, the main CPU 1
If it is determined that there is a response from 01, the process returns to step S601.

As described above, the sub CPU 108 is activated and the LCD 111 is activated in a shorter time than when the main CPU 101, which takes a long time to activate the normal program, reaches the normal state.
By displaying the initial screen on the screen, the screen can be displayed without the user being aware of the waiting time.

Further, even when the main CPU 101 has some abnormality and cannot start normally, it is possible to notify the user of the abnormality by displaying an error.

Further, even if the operation becomes abnormal after the main CPU 101 is activated, the sub CPU 108 can display an error screen.

When the image processing apparatus enters the sleep state, power is supplied only to the minimum necessary unit in order to minimize power consumption. The main CPU 101 has a main CPU 101 and a RAM 1 for the power supply unit 113.
02, the ROM 103, the hard disk 104, the image processing circuit 105, the scanner unit 106, the printer unit 107, etc. are turned off to enter the sleep mode.

During sleep, the sub CPU 108 monitors the network (LAN) and operates the operation keys (KEY) 112.
When it is detected that a predetermined event has occurred, the main CPU 1
01 or the like is instructed to restart the power supply, and the recovery from the sleep state is executed. Even when returning from the sleep mode, the sub CPU 108 operates to display a predetermined message on the LCD 111 before the main CPU 101 returns to the normal state.

As described above, the main CPU 101 that executes a main program, the sub CPU 108 that operates independently of the operating state of the main CPU 101, and the LCD 111 that can draw directly from the main CPU 101 and the sub CPU 108 are included. , The main CPU 101 is LC
When it is difficult to control D111 (when the main CPU 101 is being activated (before the completion of activation) when the power is turned on or when returning from sleep, when the operation of the main CPU 101 is abnormal (error occurs)), the sub CPU 108 causes the LCD 1 to operate.
By displaying a predetermined screen (initial screen, error screen) on 11, a complicated screen can be displayed at high speed on the display unit (LCD 111) of the operation unit during normal operation when the main CPU 101 is operating, and CPU1
Appropriate error display can be performed when 01 is in the process of starting up or when an operation error occurs.

The printer unit 10 shown in FIG.
7 may be a laser beam system, an electrophotographic system other than the laser beam system (for example, an LED system), a liquid crystal shutter system, an inkjet system, a thermal transfer system, a sublimation system, or any other printing system.

Further, according to the present invention, the scanner unit 106 is used.
It may be a printer device not including.

Furthermore, the present invention is not limited to the image processing apparatus, but can be applied to all electronic equipment having a display device in the operation section or the like.

The structure of the data processing program readable by the image processing apparatus according to the present invention will be described below with reference to the memory map shown in FIG.

FIG. 7 is a diagram for explaining a memory map of a storage medium that stores various data processing programs that can be read by the image processing apparatus according to the present invention.

Although not particularly shown, information for managing the program group stored in the storage medium, such as version information and creator, is also stored, and information depending on the OS or the like on the program reading side, such as the program, is stored. In some cases, an icon or the like for identification and display is also stored.

Further, data dependent on various programs is also managed in the above directory. Also, if the program or data to be installed is compressed,
A program for decompressing may be stored.

The functions shown in FIGS. 4, 5, and 6 in this embodiment may be executed by the host computer by a program installed from the outside.
In that case, the present invention is applied even when the information group including the program is supplied to the output device from a storage medium such as a CD-ROM, a flash memory, or an FD, or from an external storage medium via a network. It is a thing.

As described above, the storage medium recording the program code of the software that realizes the functions of the above-described embodiments is supplied to the system or apparatus, and the computer (or CPU or MP of the system or apparatus is supplied.
It goes without saying that the object of the present invention can also be achieved by U) reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, C
D-ROM, CD-R, DVD-ROM, magnetic tape,
A non-volatile memory card, ROM, EEPROM, silicon disk or the like can be used.

Further, not only the functions of the above-described embodiments are realized by executing the program code read by the computer, but also the OS (operating system) running on the computer based on the instructions of the program code. It goes without saying that this also includes the case where the above) performs a part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code, The CPU or the like provided in the function expansion board or function expansion unit performs a part or all of the actual processing,
It goes without saying that the processing includes the case where the functions of the above-described embodiments are realized.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus. In this case, by reading a storage medium storing a program represented by software for achieving the present invention into the system or apparatus, the system or apparatus can enjoy the effects of the present invention. .

Furthermore, by downloading and reading a program represented by software for achieving the present invention from a database on a network by a communication program, the system or apparatus can be
It is possible to enjoy the effects of the present invention.

[0080]

As described above, the first aspect of the present invention
According to the invention of 10 to 10, the display means capable of direct drawing control from the first control means for executing a main program and the second control means operating independently of the operating state of the first control means, When it is difficult for the first control unit to control, the second control unit controls the display unit to display a predetermined screen, so that the first control unit, which is the main CPU, operates. A complex screen can be displayed at a high speed on a large operation screen during normal operation, and the sub-CPU, which is a sub-CPU, is activated until the first control means, which is the main CPU, is activated or even if an operation abnormality occurs. With the control means, it is possible to perform an initial display and an appropriate error display.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image processing apparatus showing an embodiment of the present invention.

FIG. 2 is a block diagram showing the internal configuration of the main CPU shown in FIG. 1 in more detail.

3 is a block diagram showing a more detailed internal configuration of a sub CPU shown in FIG.

FIG. 4 is a flowchart showing an example of a first control processing procedure of the present invention.

FIG. 5 is a flowchart showing an example of a second control processing procedure of the present invention.

FIG. 6 is a flowchart showing an example of a third control processing procedure of the present invention.

FIG. 7 is a diagram illustrating a memory map of a storage medium that stores various data processing programs that can be read by the image processing apparatus according to the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional image processing apparatus.

[Explanation of symbols]

101 Main CPU 102 RAM 103 ROM 104 hard disk 105 image processing circuit 106 Scanner unit 107 printer unit 108 Sub CPU 109 RAM 110 ROM 111 liquid crystal display 112 Input key 113 power supply unit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 5/00 530 G09G 5/00 555D F term (reference) 5B045 AA01 GG09 HH01 JJ01 JJ41 5B050 AA10 CA09 CA10 FA02 5B069 AA20 BA01 BA04 BB15 KA01 5C082 AA27 AA32 BA12 BB53 BD02 BD09 CA76 DA22 DA73 DA86 MM02 MM05 MM09

Claims (10)

[Claims] 1. A first control unit that executes a main program, and a second control unit that operates independently of the operating state of the first control unit.
And a display means capable of direct drawing control from the first and second control means, wherein the second control means controls the display means by the first control means. An image processing apparatus, wherein display control of a predetermined screen is performed on the display means when it is difficult. 2. The image processing according to claim 1, wherein the case where it is difficult for the first control unit to control the display unit is before the completion of activation of the first control unit. apparatus. 3. The image processing apparatus according to claim 2, wherein the second control means completes activation in a shorter time than the first control means when power is turned on. 4. The case where it is difficult for the first control means to control the display means is a case where an abnormality occurs in the first control means.
The image processing device described. 5. A first control means for executing a main program, a second control means that operates independently of an operating state of the first control means, and the first and second control means. In a display unit control method of an image processing apparatus having a display unit capable of direct drawing control, when the first control unit has difficulty controlling the display unit, the second control unit causes the display unit A method of controlling a display unit of an image processing apparatus, comprising: a display step of displaying a predetermined screen on the display. 6. The image processing according to claim 5, wherein the case where it is difficult for the first control unit to control the display unit is before the completion of the activation of the first control unit. Method for controlling display unit of device. 7. The display unit control method for an image processing apparatus according to claim 5, wherein the second control means completes activation in a shorter time than the first control means when the power is turned on. 8. The case where it is difficult for the first control means to control the display means is a case where an abnormality occurs in the first control means.
A method for controlling a display unit of the described image processing apparatus. 9. A program for realizing a display unit control method for an image processing apparatus according to claim 5. Description: 10. A computer-readable storage medium that stores a program for executing the method for controlling a display unit of an image processing apparatus according to claim 5.