JP2003330793A - Information processor and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in conventional equipment that a DRAM to be checked is used, prior to the check of the DRAM to be checked, to execute a check program therefor, and this contradicts the purpose of operation test of the DRAM. <P>SOLUTION: This information processor has a CPU, an IRAM 3002a connected to the local bus of the CPU, and a ROM and RAM connected to the external bus of the CPU. This processor further has a cache controller 3101 for varying the memory capacity to be used as cache memory according to the operation mode of the device of the memory capacity of the IRAM 3002a to make the IRAM 3002a usable as cache memory. Programs or data are stored in the memory area other than that used as the cache memory in the IRAM 3002a, and the check program stored in the IRAM 3002a is executed to perform a memory check. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which uses a built-in memory of a CPU as a cache memory and a control method thereof.

[0002]

2. Description of the Related Art In recent years, in an information processing apparatus having a plurality of functional modules, programs and data are stored in a ROM, and the CPU sequentially reads out the programs and data from the ROM to execute the desired control. Is going. In addition, today, the functions of these devices have become diverse. For example, a conventional printer device is provided with a memory card slot, the image information stored in the memory card inserted in the slot is read out, and the printer itself performs color processing on the image information to record the image. There is a photo direct printer device. It is desired to increase the processing speed of such equipment, and the drive frequency of the CPU controlling the equipment is R
Often used is faster than the access speed to the external memory such as OM and DRAM. Such high speed C
A device that uses PU has a cache memory,
The number of accesses to the external memory is reduced as much as possible, and C is used for reading programs and reading and writing data.
PU wait time is reduced.

[0003]

In such a conventional device, the CPU sequentially reads and executes the program written in the ROM (hereinafter, referred to as the conventional example 1),
Alternatively, in a device having a cache memory, when the power of the device is turned on, a program or data written in the ROM is once copied or expanded from the ROM to the DRAM and stored in the DRAM together with the cache memory. There is a format in which the CPU executes the created program (hereinafter referred to as Conventional Example 2).

In such a device, the operation test of the control board is carried out for the purpose of improving the reliability of the product, and for example, the DR is used as a work memory of the CPU.
AM read / write check is also required. In the case of such a check, in the case of the conventional example 1, a program for checking the read / write to the DRAM may be stored in the ROM, and the program written in the ROM may be executed to perform the read / write test of the DRAM. Although conceivable, this method has a problem that the CPU sequentially reads out the program from the ROM and executes it, and the time required for this check becomes long.

Further, in the method of the conventional example 2, it is necessary to once expand the program of the ROM to the DRAM, and before the DRAM of the check target is checked, the DRAM of the check target is used to execute the check program. This is a contradiction for the purpose of DRAM operation test. Therefore, if the DRAM cannot operate normally due to manufacturing problems or defective DRAM components, the read / write check itself cannot be performed normally.

The present invention has been made in view of the above-mentioned conventional example, and provides an information processing apparatus and a control method therefor, which efficiently use a CPU built-in memory, which is a high-speed memory, to speed up the processing. To aim.

[0007]

In order to achieve the above object, the information processing apparatus of the present invention has the following configuration.
That is, the CPU, the built-in memory connected to the local bus of the CPU, and the R connected to the external bus of the CPU.
An information processing device including an OM and a RAM, wherein the memory capacity used as a cache memory among the memory capacities of the built-in memory can be changed according to an operation mode of the device, and the built-in memory can be used as a cache memory. And a data storage control means for storing data in a memory area of the built-in memory other than that used as the cache memory.

In order to achieve the above object, the control method in the information processing apparatus of the present invention comprises the following steps.
That is, the CPU, the built-in memory connected to the local bus of the CPU, and the R connected to the external bus of the CPU.
A control method in an information processing device including an OM and a RAM, wherein the memory capacity used as a cache memory among the memory capacities of the built-in memory is made variable according to an operation mode of the device, and the built-in memory is a cache memory. And a data storage control step of storing data in a memory area of the built-in memory other than that used as the cache memory.

[0009]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[Schematic Description of Apparatus Main Body] FIG. 1 shows a photodirect printer apparatus 100 according to an embodiment of the present invention.
It is a general | schematic perspective view of 0. The photo-direct printer apparatus 1000 has a function as a general PC printer that receives and prints data from a host computer (PC), and directly reads and prints image data stored in a storage medium such as a memory card. Or has a function of directly receiving and printing image data from a digital camera.

In FIG. 1, the main body forming the outer shell of the photodirect printer 1000 according to the present embodiment is
It has exterior members for the lower case 1001, the upper case 1002, the access cover 1003, and the discharge tray 1004. Further, the lower case 1001 corresponds to the printer device 10.
00 and the upper case 1002 form a substantially upper half of the main body. The combination of both cases forms a hollow body structure having a storage space for storing each mechanism described later. Openings are formed in the upper surface portion and the front surface portion, respectively. Further, one end of the discharge tray 1004 is rotatably held by the lower case 1001, and the opening formed in the front surface of the lower case 1001 can be opened and closed by the rotation thereof. Therefore, when the recording operation is performed, by rotating the discharge tray 1004 to the front side to open the opening, the recording sheets can be discharged from here, and the discharged recording sheets are sequentially stacked. Is ready to go. Further, the discharge tray 1004 includes two auxiliary trays 1004a, 1004a.
A storage area 004b is accommodated, and the support area of the sheet can be expanded or reduced in three steps by pulling out each tray as needed.

One end of the access cover 1003 is rotatably held by the upper case 1002 so that an opening formed on the upper surface can be opened and closed. By opening the access cover 1003, the inside of the main body is opened. The recording head cartridge (not shown) or the ink tank (not shown) housed therein can be replaced. Although not particularly shown here, when the access cover 1003 is opened and closed, a protrusion formed on the back surface of the access cover 1003 rotates the cover opening / closing lever, and the rotation position of the lever can be detected by a micro switch or the like. Thus, the open / closed state of the access cover can be detected.

On the right side of the upper case 1002, an operation panel 1010 including a liquid crystal display unit 1006 and various key switches is provided. This operation panel 1010
The structure will be described later in detail with reference to FIG. An automatic feeding unit 1007 automatically feeds the recording sheet into the apparatus main body. A paper interval selection lever 1008 is a lever for adjusting the distance between the recording head and the recording sheet. 10
Reference numeral 09 denotes a card slot into which an adapter to which a memory card can be attached is inserted, and the image data stored in the memory card can be directly fetched and printed via this adapter. As this memory card (PC), for example, CompactFlash (registered trademark) memory,
There are smart media and memory sticks. 101
Reference numeral 1 denotes a viewer (a liquid crystal display unit) that can be attached to and detached from the main body of the device. When searching for an image to be printed from the images stored in the PC card, an image for each frame or an index image is displayed. Used to display.
Reference numeral 1012 denotes a terminal for connecting a digital camera described later, and 1013 denotes a USB bus connector for connecting a personal computer (PC).

FIG. 2 shows an operation panel 1 according to this embodiment.
It is a general-view figure of 010.

In the figure, the liquid crystal display unit 1006 displays menu items for variously setting data relating to the items printed on the left and right sides thereof. The items displayed here are the first photo number of the range you want to print, the specified frame number (start / -designate), the last photo number of the range you want to finish printing (end), the number of copies (copies), and the print number. Type of paper (recording sheet) to be used (paper type), number of photos to print on one sheet (layout), specification of print quality (quality), whether to print the date taken (date) Print), designation of whether to correct and print a photo (image correction), display of the number of sheets required for printing (number of sheets), and the like. Each of these items is displayed with the cursor key 20.
It is selected or designated by using 01. Reference numeral 2002 denotes a mode key, and each time the key 2002 is pressed, the type of printing (index printing, all-frame printing, one-frame printing, etc.) can be switched, and the corresponding LED of the LED 2003 is turned on accordingly. . Reference numeral 2004 denotes a maintenance key, which is used for maintenance of the printer such as cleaning of the recording head 1301 and entering a print area designation mode. A print start key 2005 is pressed to instruct the start of printing or to establish maintenance settings. Reference numeral 2006 denotes a print stop key, which is pressed to stop printing or to give an instruction to stop maintenance.

Further, on the upper part of the operation panel 1010, a power switch 200 that can be pushed down.
8 and Resume switch (Resume switch) 200
7 and two-color LEDs 2009 indicating the operating state of the printer engine 3004 (FIG. 3). Input signals from the resume switch 2007 and the power switch 2008 are input to an ASIC 3001 (FIG. 3) described later.
It is also output to the printer engine 3004 under the control of the switch I / F module.

Next, with reference to FIG. 3, the configuration of the main part relating to the control of the photodirect printer apparatus 1000 according to the present embodiment will be described. In FIG. 3, portions common to those in the above-mentioned drawings are given the same symbols and their explanations are omitted.

In FIG. 3, reference numeral 3000 denotes a control section (control board). Reference numeral 3001 denotes an ASIC (dedicated custom LSI). Reference numeral 3002 denotes a CPU, which is in charge of various control processes of the entire apparatus, which will be described later, and image processing. In addition, the CPU 3002 has an internal RAM (IRA) of 64 kbytes that can also operate as a secondary cache.
M) 3002a is also included. A memory 3003 is a 2M-byte flash ROM (FlashROM) 3003a for storing a control program of the CPU 3002, and an 8-Mbyte SD that functions as a work memory for storing a program at the time of execution and storing image data and the like.
It has a RAM 3003b. A printer engine 3004 is equipped with a printer engine of an inkjet printer that prints a color image using a plurality of color inks. A USB bus connector 3005 serves as a port for connecting the digital camera 3012. Reference numeral 3006 is a connector for connecting the viewer 1011. 3008 is a USB bus hub (USB
HUB), when the printer 1000 prints based on the image data from the PC 3010,
The data from 10 is passed through as it is, and the USB bus 30
21 to the printer engine 3004. As a result, the connected PC 3010 can directly perform printing by exchanging data and signals with the printer engine 3004 (functioning as a general PC printer). 3009 is a power supply connector, and a power supply 3
By 013, the DC voltage converted from the commercial AC is input. The PC 3010 is a general personal computer, 3011 is the above-mentioned memory card (PC card), and 3012 is a digital camera.

Signals are exchanged between the control unit 3000 and the printer engine 3004 by using the above-mentioned USB.
This is performed via the bus 3021 or the IEEE1284 bus 3022.

Further, between the control unit 3000 and the printer engine 3004, two switch signal lines 3023 indicating signal states from the power switch 2008 and the resume switch 2007, and a control module (CPU or CPU) inside the printer engine 3004. An engine reset signal line 3024 for resetting the ASIC) is connected. Each of the two switch signal lines 3023 is connected to the resume switch 20 arranged on the operation panel 1010.
07, the signals corresponding to the pressed states of the power switch 2008 are transmitted, and the pressed states of the switches 2007 and 2008 are directly transmitted to the printer engine 3004 according to the setting of the switch I / F function unit in the ASIC 3001 described later. It is possible to select whether to perform (through mode) or to transmit to the printer engine 3004 as a signal emulated by the control unit 3000 (CPU mode).

FIG. 4 is a block diagram showing the functional arrangement of the CPU 3002.

Inside the CPU 3002, there is a C including an instruction code fetch circuit, an arithmetic unit, a register and the like.
PU core unit 3100, cache controller 3101 for controlling cache memory, and flash ROM 3
An external memory controller 3103 including a bus control circuit for accessing an external memory space such as 003a, an ASIC 3001, an SRAM 3003b, and an IRAM 3002a composed of a high-speed memory of 64 kbytes that can also operate as a secondary cache memory. There is.

In the cache controller 3101 according to this embodiment, 16 caches are stored in the IRAM 3002a.
The area to be used as the secondary cache memory in units of k bytes can be arbitrarily set by the CPU core 3100 by program processing. The cache controller 3101 according to the present embodiment has four primary cache memories, one for the instruction code cache and one for the data cache.
It has a so-called Harvard architecture configuration having a k-byte memory. Cache controller 3101
Reads the instruction code from the CPU core 3100,
In response to a data read / write request, if the instruction code or data is in the primary cache (hit), the instruction code or data can be read or the data can be written at high speed from the primary cache. If the instruction code or data does not exist in the primary cache (miss hit) and the instruction code or data exists in the secondary cache (IRAM) (hit), the instruction or data is read from the secondary cache or the data Writing is performed, and when there is a mishit, the external memory space is accessed via the external memory controller 3103.

At this time, for example, access to the SDRAM 3003b is performed by reading and writing at a high speed in burst mode in units of a predetermined number of words. Along with this, the secondary cache (IRA
If M) is valid, the instruction code and data are stored in the secondary cache, and at the same time, the instruction code and data are stored in the primary cache.
The instruction code and the data read / write operation requested from 0 are performed. Since the primary cache area and the secondary cache area are finite, when the primary cache overflows due to a request from the CPU core 3100, the overflowing instruction code and data are transferred from the primary cache to the secondary cache area.
Move to next cache (IRAM). When the secondary cache further overflows, S is added to the overflowed data.
When there is unwritten data in the DRAM 3003b, a cache flush operation is performed to write data to the SDRAM 3003b at a high speed in a burst mode in units of a predetermined number of words. Further, an area other than the secondary cache area in the IRAM 3002a can also be used as a high speed memory. By adopting the above-mentioned configuration, the control processing speed in this device is increased.

FIG. 5 is a block diagram showing the structure of the ASIC 3001. In FIG. 5 as well, portions common to those in the previous drawings are given the same symbols and their explanations are omitted.

A PC card interface (I / F) unit 4001 reads image data stored in the attached PC card 3011 or writes data to the PC card 3011. 4002 is I
The EEE1284 interface unit exchanges data with the printer engine 3004. This IE
The EE1284 I / F unit 4002 is the digital camera 30.
12 or a bus used when printing the image data stored in the PC card 3011. 4003
Is a USB interface unit for exchanging data with the PC 3010. A USB host interface unit 4004 exchanges data with the digital camera 3012. An operation panel / interface unit 4005 inputs various operation signals from the operation panel 1010 and outputs display data to the display unit 1006. A viewer interface unit 4006 controls the display of image data on the viewer 1011. Reference numerals 4007a and 4007b are switch interface units that control interfaces with various switches and the LEDs 4009 and the like.

Reference numeral 4011 is a register for controlling the reset of the printer engine 3004. This engine reset register 4011 is not automatically initialized by the ASIC 3001 after each module in another ASIC is reset-started (started by a reset signal), but is automatically initialized by a reset-start. It is not initialized and is initialized only when the power supply is completely cut off. That is, by referring to the set value of the register 4011, it is possible to determine whether the reset start is a simple one or a pure hard reset by disconnecting the power supply 3013 from the AC power supply (power supply cut). .

In this embodiment, when the power switch 2008 is pressed (power off instruction) while the power is on, the printer engine unit 3004 starts the power off operation.
Then, when the power-off operation ends, the fact is detected, and the power-off process (PowerDown) in step S19 of FIG.
Then, as the setting for resetting the CPU 3002 by pressing the power switch 2008 through the switch I / F (4007a, b), unnecessary clock operation is stopped and the power saving mode is entered. When the power switch 2008 is pressed again in this state, the reset is applied,
The system is ready to boot. 4008 is C
The PU interface unit controls exchange of data with the CPU 3002. An internal bus (ASIC bus) 4010 connects these units.

As described above, in the photo-direct printer apparatus 1000 according to this embodiment, the CPU 3002
However, according to the control program stored in the memory 3003 of FIG. 3, in addition to image processing, control of each unit of the apparatus is also executed.

This control program is constructed in a multitask format in which each functional module is tasked.
The main task configuration is shown in FIG.

FIG. 6 is a block diagram showing the configuration of tasks in the photodirect printer apparatus 1000 according to this embodiment.

In FIG. 6, reference numeral 8000 denotes a system control task, which performs arbitration of the entire system such as issuing events between tasks, sequence control associated with the end of events, and exclusive processing. Reference numeral 8001 denotes a key event task, which is based on the key operation on the operation panel 1010.
Analyzes the pressed key. Reference numeral 8002 denotes a display task on the LCD display unit 1006. This display task is activated at the time when UI control or a message display request on the display unit 1006 occurs, and executes display control on the display unit 1006. Reference numeral 8003 denotes a task activated by inputting / outputting data by reading / writing the PC card 3011. 8004 is a P connected via a USB bus
A USB printer task that controls data transfer from the C3010 and is activated by a USB printer interrupt.
Executes the function as a C printer. 8005 is a US started by the system control task 8000
PC30 via USB I / F in B storage task
Command and data are exchanged with PC3
In response to the request of 010, read / write control to / from the PC card 3011 is performed in cooperation with the PC card unit 8003. In addition, in response to a message from the system control task 8000, a USB control task, which is a subordinate task,
It starts and ends the USB bulk task. Reference numeral 8006 denotes a pseudo host task, which reads data from the digital camera 3012 connected via the USB and executes various communication controls. A file task 8007 controls input / output such as file opening, closing, reading, and writing.

Reference numeral 8008 denotes a Centronics task for controlling communication of the Centronics interface connected to the printer engine 3004, which executes DMA transmission of print data, status response and the like. Reference numeral 8009 denotes an image processing task, which receives RGB data, creates YMCK data by 3D processing, tetrahedral interpolation, color conversion, scaling, error diffusion processing, etc., and finally the printer engine 3
Raster image data to be output to 004 is created. 8
A page create task 010 expands JPEG data and converts it into image data, or creates image data from BMP format data, or HTML.
In addition to creating image data from a document, image processing such as correction of photo data and gradation correction and creation of RGB data are performed. Reference numeral 8011 denotes a viewer task, which is connected to the viewer 1011
The display control to 1 is executed.

Next, the arrangement of control codes including instruction codes and data on the memory map will be described with reference to FIGS.
This will be described with reference to the memory map shown in FIG.

FIG. 7 is a view for explaining the memory map of the IRAM 3002a, and the usage in each operation mode is indicated by IM1 to IM4.

FIG. 8 is a diagram for explaining the memory map (ROM) of the flash ROM 3003a and the memory map (SDRAM) of the SDRAM 3003b.

The control code is stored in the electrically rewritable 2M-byte flash ROM 3003a, and as shown in the memory up (ROM) of FIG. 64 kbytes, that is, a special code necessary for reset start is arranged in P1, and a normal code, that is, a control code for processing shown in steps S3 to S19 in FIG. 9 described later is arranged in the remaining portion (P2). is doing.

The special code portion (P1) has a structure shown in FIG.
The programs shown in the control flow of 0 (loader) and FIG. 11 (startup) are stored, and a 1 kbyte loader (Loader) unit (A1), a 7 kbyte startup (StartUP) unit (A2), and 56 k There is a byte update section (A3).

The normal code section (P2) includes a system vector section (A4), which is a program section for CPU interrupt vector processing, and a power-off state (described below with reference to FIG. 11) stored in P2. PowerDown) Go to processing P
The jump table (JTBL) (A5) in which addresses for jumping from 1 are stored, the PowerDown (A6) in which the control code for power-off processing is stored, and the above-described FIG. 6 have been described. A normal program section (A7) storing the control code of each task and a data section (A8)
And a checker unit (A9) that stores a control code for RAM check processing, which will be described later with reference to FIG. 11.

Next, the relationship between the special code (P1) and the normal code (P2) will be described with reference to the flow charts of FIG.

FIG. 9 is a flow chart showing the overall processing flow of the photodirect printer apparatus 1000 according to this embodiment.

This processing is started when the reset of the control unit 3000 is released. First, in step S1, the hardware automatically executes the flash ROM 3003.
The loader unit (A1 in FIG. 8) of 1 kbytes from the beginning of a is
The IRAM 3002a of the CPU 3002 is loaded from the beginning of the IRAM 3002a to 1 kbyte (B1 in FIG. 7).
The control code of the loader unit starting from the first address of is executed.
At this time, the IRAM 3002a is mapped as indicated by IM1 in FIG. 7, and the secondary cache is in a disabled state. In this way, the execution of the control program is started from step S1.

FIG. 10 is a flowchart showing the processing based on the control code of the loader section.

In FIG. 10, first, step S100.
Then, the CPU built-in register is initialized, and then the process proceeds to step S101, where the B5 portion indicated by IM2 in FIG.
A 2-kbyte secondary cache memory (L2Cache) is allocated. Next, in Step S102, the flash ROM
The startup control code stored in A2 of FIG. 8 of 3003a is loaded into B4 of FIG. 7 of IRAM 3002a. Then, the process proceeds to step S103, and the stack pointer and the like are set so that the stack memory area necessary for the operation of a startup program to be described later is located at B2 in FIG. 7, and the processing of the loader unit is finished (IM2 ).

Next, in this way, in step S102, the IRA
The control code of the startup unit loaded in M3002a is executed in step S2 of FIG.

FIG. 11 is a flow chart showing the startup control process of step S2 of FIG.

In the processing of this startup unit,
First, in step S200, the contents of the engine reset register 4011 are read to check whether the engine reset has been canceled. If it has not been released, the power is turned on by connecting the AC plug to the AC power source.
It is determined whether any one of "mode 1" to "mode 5". Here, any one of “mode 1” to “mode 5” is selected according to the combination of the pressed states of the switches of the operation panel 1010 that are pressed when the power is turned on.
For example, the resume switch 2007 and the power switch 2
008, and when all of the predetermined switches are in the off state, when the “mode 1” is set, the normal A
The process at the time of C ON is started, and JTBL (A5) to PowerDown of the flash ROM 3003a is started in step S210.
Only (A6) is copied to SDRAM 3003b and PI
The mode of NF (B3) is set to the "power-on standby mode", and the process jumps to step S19 of FIG. 9 via JTBL (A5) to execute the power-off process.

In the power-off process of step S19, the engine reset register 4011 is operated to release the reset of the printer engine 3004, and the switch I / F
(4007a, b) is switched to the through mode and the power switch 2008 is pressed to cause the CPU 3002
As a setting for resetting, the unnecessary clock operation is stopped and the power saving mode is entered. After that, the power switch 2008 is pressed again to cause the CPU 300
2 is reset, and at the same time, the printer engine 3004 is activated. When the CPU 3002 is activated by resetting the CPU 3002 in step S1, the engine reset is released this time in the determination in step S200 of FIG. 11, so the process proceeds to step S260 and shifts to the "normal mode" processing.

"Mode 2" is an inspection mode for a substrate check process in a manufacturing process or the like. In this inspection mode, the read / write check of the SDRAM 3003b is performed. First, in step S220, the secondary cache is prohibited, and preparations are made to switch from the IM2 map to the IM3 map in FIG. Next, proceeding to step S221, the Checker control code (A9 in FIG. 8) stored in the flash ROM 3003a is loaded into B6 of the IRAM 3002a (IM3). Next, proceeding to step S222, the Checker process is executed to check the read / write of the SDRAM 3003b. In this step S222, S
The result of testing the DRAM 3003b is PINF (B
It is stored in 3). If, for example, there is an error, the program is further operated and the SDRAM 30
Since there is a danger of runaway when using 03b, ASI
This is output to a special port of C3001 and the operation is stopped. On the other hand, if normal, step S22
3, the memory map of the IRAM 3002a is set to I again.
32k secondary cache to switch to M2 map
The byte is set and the mode is set to “inspection mode 1”.

"Mode 3" and "mode 4" are inspection modes in the manufacturing process and the like. In this inspection mode, the mode is set to "inspection mode 2" in step S230 or "inspection mode 3" in step S240.

In "mode 5", the flash ROM 300 is used.
This is an update mode for rewriting 3b. In this case, first, in step S250, the flash ROM 300
The update control code (A3 in FIG. 8) stored in 3a is copied to the work 2 (C1) of the SDRAM 3003b. Next, in Step S251, the flash R
The update process of the OM3003a is executed. In this step S251, in order to write the control code stored in the PC card 3011 into the flash ROM 3003b, the update data of a predetermined format stored in the PC card 3011 is read out, and the SDRAM 3 is temporarily stored.
2 in the work 3 (WOrk3) area (C3 in FIG. 8) of 003b.
It is expanded as M-byte flash ROM image data (corresponding to P3 in FIG. 8).

Flash ROM is included in this update.
There are a partial update method of changing only P2 without changing P1 of 3003a and a full update method of changing the entire flash ROM 3003a (P3). Such update method is identified by a predetermined control code of this update data. You can do it.
In the former case (partial update), the P2 portion of the flash ROM 3003a is erased and the SDRAM 30
Only the portion corresponding to the P2 portion developed in the work area (C3) of 03b is written in P2 of the flash ROM 3003a. In the latter case (whole update), the entire area (P3) of the flash ROM 3003a is erased,
All the data expanded in the work area (C3) of the SDRAM 3003b is written in the flash ROM 3003a. When the update of the flash ROM 3003a is completed normally in this way, the process advances to step S252 to set the mode to the "update mode".

In step S200, the switch I / F (40
07a, b) CP by pressing the power switch 2008
As a setting for resetting U3002, unnecessary clock operation is stopped and the power saving mode is entered. After that, when the power switch 2008 is pressed again to be reset, the engine reset of the printer engine 3004 has already been canceled, so that it is determined as "mode 0", and the process proceeds to step S260 to set the mode to "normal mode".

When the various modes are determined as described above, the process proceeds to step S270, and the various modes are set to the IRAM 300.
It is stored in the PINF area (B3) of 2a. Next, proceeding to step S271, the secondary cache is set to 48 kbytes in order to switch to the IM4 map shown in FIG. 7 so that the subsequent processing is executed as fast as possible.
Then, in step S272, the flash ROM 30
03a of JTBL (A5) to normal program (A7) is the normal program area (C of SDRAM 3003b).
Copy to 2). Then jump to C_INT. As a result, the process proceeds to step S3 of FIG.
The system vector part (A4) stored in 003a is copied to the head area (B9) of the IRAM 3002a and C
The PU 3002 is made to be able to execute interrupt processing and the like.

Next, in step S4, the OS is operated to operate the tasks shown in steps S5 to S18.
To start. When the OS is started in this way, an initialization task (Initializer) is started in step S5 according to the configuration information of the OS.

Next, referring to FIGS. 12 and 13, FIG.
The initialization task process of step S5 will be described.

FIG. 12 is a flow chart for explaining the initialization processing (Initializer) of step S5 of FIG.

First, in step S300, the ASIC 300
Registers other than the No. 1 engine reset register (4011) and the switch I / F (4007a, b) are initialized as necessary. Next, in step S301, O
A timer is started to operate the time management function of S. Then, in step S302, the reset of the printer engine 3004 is released and the printer engine 3004 is activated if necessary.

FIG. 13 is a flowchart for explaining the engine signal initialization processing in step S302.

First, in step S400, the PINF area (B3) of the IRAM 3002a is searched in step S270.
The mode information stored in is checked to see if it is the “inspection mode 1” or the “inspection mode 2”, and if so, this process ends. That is, "inspection mode 1"
(“Mode 2”) or “Inspection Mode 2” (“Mode 3”) does not release the engine reset.

On the other hand, in step S400, "normal mode", "inspection mode 3" or "update mode"
If the switch I / F (4
007a, b) is switched to the through mode. Next, in step S402, the engine reset register 4011
Is checked to see if the engine reset has been canceled, that is, whether the engine is in the “normal mode”. If so, the process proceeds to step S410. In step S410, it is checked whether or not the mode is the "update mode", and if not, this process ends.

If it is determined in step S402 that the engine reset has not been released, that is, in the case of "inspection mode 3" or "update mode", the process proceeds to step S403, the engine reset is released, and then step S40.
In step 4, the process of resetting the printer engine 3004 is completed, and it is waited for about 2 seconds until the printer engine 3004 can be turned on by detecting that the power switch 2008 is turned on. Then, the process proceeds to step S410, and it is determined whether or not it is the "update mode". If not, that is, if it is the “normal mode” or the “inspection mode 3”, this processing ends.

On the other hand, if the "update mode" is selected in step S410, the printer engine 3004 is automatically powered on in steps S411 to S416. That is, in step S411, the switch I / F (4
007a, b) in CPU mode (switch signal to CPU
To emulate), then step S
At 412, the power switch signal (signal line 3023) to the printer engine 3004 is output in the ON state. Then, in step S413, the printer engine 3004 waits for about 50 milliseconds so that the printer switch 3004 can fully recognize the ON state of the power switch 2008. Then, the process proceeds to step S414, and the power switch signal (signal line 3023) is turned off. Then, the process proceeds to step S415, and the switch I / F
After switching (4007a, b) to the through mode, the process proceeds to step S416, waits for the printer engine 3004 to shift to the power-on state, and ends this processing.

When the engine signal initialization processing of step S302 is completed as described above, step S303
Proceeding to FIG. 12, the mode information stored in the PINF area (B3) of the IRAM 3002a is referred to. If "inspection mode 1" or "inspection mode 2" is stored here, the process advances to step S305 to activate the checker task (S18 in FIG. 9). This checker task (S
18) is a tester and USBI /
By connecting F4003, this interface
By receiving a special command and sending a status, the board is checked. For example, in the “inspection mode 1”, a command for returning the result of the check of the SDRAM 3003b executed in step S222 and a status return are prepared.

On the other hand, in step S303, "normal mode", "inspection mode 3" or "update mode"
In this case, the process proceeds to step S304, and the system control task (S6) is started to start various normal tasks, that is, the various tasks shown in steps S7 to S17 of FIG.

Steps S6 to S17 are the control program described with reference to FIG. 6, and are configured in a multi-task format in which each functional module is tasked. IRAM300
2a work area (B8 in FIG. 7) and SDRAM 300
The work 2 area (C1 in FIG. 8) and the work 3 area (C3 in FIG. 8) of 3b are used as a work memory area for executing the program, and the program executed here is the normal program area of the SDRAM 3003b. (Fig. 8
C2), and the processing speed of the entire device is increased by targeting the operation of the primary cache and the secondary cache with respect to the entire SDRAM 3003b.

Step S6 in FIG. 9 is the system control task indicated by reference numeral 8000 in FIG. 6, and performs arbitration for the entire system such as issuing events between tasks, sequence control associated with the end of events, and exclusive processing. . In the case of "normal mode", all the tasks shown in steps S7 to S17 are activated to execute the normal operation mode. In the case of "inspection mode 3" or "update mode", only the key event task (S7) and the LCD display task (S8) are activated in the special mode to display the version information of the flash ROM 3003a and the like on the display unit 10.
It is displayed at 06 and waits for the pressing of the power switch 2008.

Step S7 of FIG. 9 shows the key event task described in 8001 of FIG.
The key pressed by the 0 key operation is analyzed.

Step S8 of FIG. 9 shows the display task on the LCD display unit 1006 described in 8002 of FIG.
The display unit 1006 is activated when UI control or a message display request is issued, and the LCD display unit 1006 is activated.
Display control is executed.

In step S9 of FIG. 9, the viewer task described in 8011 of FIG. 6 executes display control on the viewer 1011 while the viewer 1011 is connected. Step S10 represents a task activated by inputting / outputting data by reading / writing to / from the PC card 3011 described in 8003 of FIG. In addition, step S11
Is a file task described with reference to 8007 in FIG. 6, and performs input / output control such as file open, close, read, and write. Step S12 is a USB printer task started by data transfer from the PC 3010 connected via the USB bus described in 8004 of FIG.
It is activated by a USB printer interrupt and executes the function as a PC printer. Step S13 is the pseudo USB host task described in 8006 of FIG.
The reading of data from the digital camera 3012 connected via the SB and various communication controls are executed.

Step S14 in FIG. 9 is 8005 in FIG.
In the USB storage task described above, the USB control task and the USB bulk task, which are subordinate tasks, are activated and terminated in response to a message from the system control task 8000. Step S15 is the page create task described in 8010 of FIG.
JPEG data is decompressed and converted into image data, or image data is created from BMP format data, or image data is created from an HTML document, and images such as photo data correction and gradation correction are created. Processing and creation of RGB data are performed. Step S1
6 is an image processing task described in 8009 of FIG.
The GB data is received, YMCK data is created by 3D processing, tetrahedral interpolation, color conversion, scaling, error diffusion processing, etc., and finally raster image data to be output to the printer engine 3004 is created. Further, here, the work 1 area (B8 in FIG. 7) of the IRAM 3002a is used to increase the image processing speed. Further, in step S17, the Centronics interface connected to the printer engine 3004 is controlled by the centro task described in 8008 of FIG.
Execute transmission, status response, etc.

Further, when the power switch is pressed and the printer engine 3004 transits to the power off state, the key event task (S7) detects that fact and sends a power off request to the system control task (S6). (S6) is the above step S
19 power-off processing is executed, and the switch I / F (4007
a, b) is pressed by the CPU 3 by pressing the power switch 2008
As a setting for resetting 002, unnecessary clock operation is stopped and the power saving mode is entered.

As described above, the photodirect printer apparatus 1000 according to this embodiment can be operated at high speed as a whole.

(Other Embodiments) As described above, the object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the embodiment to a system or apparatus, and the system or apparatus. This can also be achieved by the computer (or CPU or MPU) of (1) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention. As a storage medium for supplying such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, non-volatile memory card, ROM, etc. may be used. You can

Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the OS (operating system) operating on the computer is operated based on the instruction of the program code. This also includes the case where the system) performs a part or all of the actual processing and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code. It also includes a case where the CPU or the like provided in the function expansion board or the function expansion unit performs a part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

As described above, according to the present embodiment, for example, in the case of a DRAM operation test, the cache memory is set to the use-disabled state, and the DRAM is set in the high-speed memory.
The operation test of the DRAM can be speeded up by reading and operating the check program.

By storing various mode states at the time of reset in a part of the high speed cache memory, various modes can be determined at high speed.

Further, by utilizing a part of the high-speed cache memory for image processing, high-speed image processing can be performed without increasing the cost of the device.

[0080]

As described above, according to the present invention, the CPU built-in memory, which is a high speed memory, can be efficiently used.
The processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of a photo-direct printer device according to an embodiment of the present invention.

FIG. 2 is a schematic view of an operation panel of the photodirect printer apparatus according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a main part relating to control of the photodirect printer device according to the present embodiment.

FIG. 4 is a block diagram showing a configuration of a main part of the CPU shown in FIG.

5 is a block diagram showing a configuration of the ASIC shown in FIG.

FIG. 6 is a diagram illustrating a multitask configuration in which a task is made into each functional module in the control program of the photodirect printer apparatus according to the present embodiment.

FIG. 7 is a diagram illustrating a memory map of a RAM (IRAM) with a built-in CPU of the photo-direct printer apparatus according to the present embodiment.

FIG. 8 is a diagram illustrating a memory map of a flash ROM and an SDRAM of the photo direct printer device according to the present embodiment.

FIG. 9 is a flowchart illustrating a control operation of the photodirect printer apparatus according to the present embodiment.

FIG. 10 is a flowchart illustrating processing of a loader unit in step S1 of FIG.

FIG. 11 is a flowchart illustrating processing of a startup unit in step S2 of FIG.

FIG. 12 is a flowchart illustrating processing of an initialization unit in step S5 of FIG.

FIG. 13 is a flowchart illustrating a process of an engine signal initialization unit in step S302 of FIG.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuyuki Masumoto             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Tetsuya Suwa             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Akihiko Hamamoto             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Shin Hibi             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Masato Oshima             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Fumihiro Goto             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation (72) Inventor Mitsuhiro Ono             3-30-2 Shimomaruko, Ota-ku, Tokyo             Non non corporation F-term (reference) 5B005 JJ01 JJ11 KK12 MM04 UU42                       VV22 WW02                 5B018 GA03 MA01 MA03 NA02                 5B060 MM03

Claims (6)

[Claims] 1. An information processing apparatus comprising a CPU, a built-in memory connected to a local bus of the CPU, and a ROM and a RAM connected to an external bus of the CPU, wherein the memory capacity of the built-in memory is A cache controller for changing the memory capacity used as a cache memory according to an operation mode of the device to enable the internal memory to be used as a cache memory; and a memory other than the cache memory in the internal memory. An information processing apparatus, comprising: a data storage control unit that stores data in an area. 2. The information processing apparatus according to claim 1, wherein the data storage control unit stores information on the operation mode in the memory area. 3. When the memory check of the RAM is instructed, there is provided means for copying the check program stored in the ROM to the built-in memory, and the CP
The information processing apparatus according to claim 1, wherein U executes a memory check of the RAM based on the check program copied to the built-in memory. 4. A control method in an information processing device comprising a CPU, a built-in memory connected to a local bus of the CPU, and a ROM and a RAM connected to an external bus of the CPU, the control method comprising: Among the memory capacities, a step of varying the memory capacity used as the cache memory according to the operation mode of the device to use the built-in memory as the cache memory, and a memory other than the cache memory in the built-in memory A data storage control step of storing data in an area, and a control method in an information processing device. 5. The control method according to claim 4, wherein in the data storage control step, information on the operation mode is stored in the memory area. 6. When a memory check of the RAM is instructed, the checking program stored in the ROM is copied to the built-in memory, and the CPU is based on the checking program copied to the built-in memory. The control method according to claim 4, wherein a memory check of the RAM is executed.