JP2003133372A - Wiring circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring circuit board realizing a semiconductor package of high quality, where electrical conduction with a semiconductor chip and resin sealing can be conducted in batch, in the mounting process of the semiconductor chip. SOLUTION: A bonding layer 61, having an opening part 62, is formed on the semiconductor chip loading side of a film carrier 10, where a wiring circuit pattern 41b is formed on one face of an insulating base material 11, a land 41a at the end of the wiring circuit pattern 41b and a land 13a and a solder resist pattern 51 on the other face, and the wiring circuit board 100 is obtained. The area increase rate for the bonding layer 61 is set to 150% to 300% under the mounting condition, so that the dynamic elastic modulus E' of the bonding layer 61 does not become larger than E'=8×10<8> Pa in the laminate temperature region (100 to 180 deg.C) and not larger than E'=5×10<6> Pa in a mounting temperature region (250 to 310 deg.C).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board having a semiconductor adhesive layer formed thereon for mounting a semiconductor chip on a film carrier.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor chip is mounted on a film carrier, bumps formed on the semiconductor chip side are pressure-bonded by a method such as ultrasonic bonding to ensure electrical continuity and then molded with a sealing resin. A semiconductor package is manufactured by bonding a film carrier and a semiconductor chip, securing electrical continuity by wire bonding, and then covering the periphery with a sealing resin. However,
As the distance between bumps on the semiconductor chip side has become narrower and the number of pins has increased, some areas have become dimensionally incompatible with wire bonding. In addition, the method using bumps also narrows the gap between the film carrier and the semiconductor chip,
The size of the bumps has become smaller, making it difficult to inject the encapsulant without bubbles. If air bubbles remain, it is not desirable because it causes deterioration of heat resistance, exudation of absorbed moisture, and deterioration of insulation properties. As described above, it has become difficult to guarantee the quality of the semiconductor device in the conventional semiconductor package.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in a semiconductor chip mounting process, high-quality semiconductor capable of performing electrical conduction with a semiconductor chip and resin sealing at the same time. An object is to provide a printed circuit board that enables packaging.

[0004]

In order to achieve the above object in the present invention, first, in claim 1, a semiconductor carrier is secured on a film carrier having a wiring circuit pattern, and electrical continuity is secured. And a dynamic elastic modulus E ′ of the adhesive layer is E ′ in a temperature range (100 to 180 ° C.) for laminating the adhesive film on the film carrier. = 8 x
10 ⁸ Pa or less, semiconductor chip mounting temperature range (250 to
At 310 ° C.), E ′ = 5 × 10 ⁶ Pa or less, which is a printed circuit board. The dynamic elastic modulus is an elastic modulus observed when a vibrational (periodic) strain or force is applied to a linear viscoelastic body, and is related to frequency and temperature. The dynamic elastic modulus is equal to the amplitude of stress that changes in the same phase as the strain when the strain changes sinusoidally with a unit amplitude. A material softer than metal such as plastic has a physical property called viscoelasticity, which is a property in which elasticity corresponding to hardness and viscosity corresponding to stickiness are combined.

According to a second aspect of the present invention, the area increase rate of the adhesive layer is determined by the semiconductor chip mounting temperature range (250 to 3).
It is 150% or more and less than 300% at 10 ° C.), which is the printed circuit board according to claim 1.

The wired circuit board of the present invention has an opening for bump connection for bonding and electrically connecting a semiconductor chip to a semiconductor chip mounting side of a film carrier having a wired circuit pattern provided on one side or both sides. The adhesive layer in the B stage state is formed. Here, the B-stage state refers to a curing intermediate state of the thermosetting resin, and the adhesive layer in this state is softened by heating and swells when touched with a certain solvent, but is not completely dissolved. The invention according to claim 1 relates to the dynamic viscoelasticity of the adhesive layer, including the laminating temperature range (100 to 180 ° C.) of the adhesive film when forming the adhesive layer and the mounting temperature range (2) of the semiconductor chip.
50 to 310 ° C.), appropriate softness is required, viscoelasticity that allows the adhesive layer to be embedded between the wiring circuit patterns during lamination, and the surrounding of the bumps of the semiconductor chip in the mounting temperature range of the semiconductor chip. The viscoelasticity that enables sealing is optimized. That is, it defines the dynamic elastic modulus E ′ required for each treatment step, and E ′ = 8 × 1 in the laminating temperature range (100 to 180 ° C.) of the adhesive film.
0 ⁸ Pa or less, and wherein the mounting temperature range (two hundred and fifty to three hundred ten ° C.) at E '= 5 × is 10 ⁶ Pa or less. Practically, the range of E ′ = 1 × 10 ⁶ to 8 × 10 ⁸ Pa in the laminating temperature range (100 to 180 ° C.), and E ′ = 1 × 10 ³ to the mounting temperature range (250 to 310 ° C.). 5 x 10 ⁶
The range of Pa is preferable.

The invention according to claim 2 regulates the flowability of the adhesive layer when mounting the semiconductor chip, and seals the periphery of the bump of the semiconductor chip and pushes air bubbles under the mounting temperature and the bonding pressure. It is required to have flowability until it can be discharged and to maintain the gap between chips without excessively flowing out around the semiconductor chip.The area increase rate is set as a parameter that regulates this flowability, and The area increase rate is 150% or more and less than 300%. Here, with a material having an area increase rate of less than 150%, sealing is insufficient and mounting defects due to air bubbles remain, and with a material having an area increase rate of 300% or more, an adhesive flows out around the semiconductor chip and the bumps are crushed. The phenomenon was observed. The area increase rate was measured by cutting an adhesive film having the same thickness as that at the time of mounting into 5 mmφ pellets, applying temperature and pressure, and measuring the area increase rate.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a partial sectional view showing an example of a wired circuit board of the present invention, FIG. 2 is a partial sectional view showing an example of a semiconductor package manufactured using the wired circuit board of the present invention, and FIGS. f) is a partial cross-sectional view showing an example of the method of manufacturing the printed circuit board of the present invention in the order of steps,
4A to 4C are partial cross-sectional views showing a state in which a semiconductor chip is mounted on the printed circuit board of the present invention. First, the insulating base material 11 made of a polyimide film or the like
A double-sided copper-clad laminated film in which copper foils 12 and 13 are bonded to both surfaces of the above is prepared (see FIG. 3 (a)). Insulating base material 1
As 1, a polyimide resin, a phenol resin, an acrylic resin, a polyester resin, a fluororesin, a polyphenyl ether resin, or an organic film made of a polymer liquid crystal can be used.

Next, via holes 21 are formed in the copper foil 12 and the insulating base material 11 on one surface of the double-sided copper-clad laminated film by laser processing (see FIG. 3B). Next, the protective layer 13 is formed on the copper foil 13 on the other surface of the double-sided copper-clad laminated film, the via holes 21 are subjected to desmear treatment for conductivity, electrolytic copper plating is performed, and the via holes are formed. Filled vias 31 are formed at 21 and a conductor layer 41 in which a copper plating layer 32 is formed on the copper foil 12 is formed (see FIG. 3C).

Next, the protective layer 14 is peeled off and the conductor layer 41 is removed.
The copper foil 13 and the copper foil 13 are patterned to form a wiring circuit pattern 41b on one surface of the insulating base material 11 and a land 41a on the end of the wiring circuit pattern 41b, and a land 13a on the other surface (see FIG. 3D). . Here, the wiring circuit pattern 41b and the land 13a are electrically connected by the filled via 31. Next, the solder resist pattern 51 is formed on the other surface of the insulating base material 11, and the wiring pattern 4 is formed.
Electrolytic nickel and gold plating are performed on the 1b, the lands 41a, and the lands 13a to form a Ni / Au coating film, and the film carrier 10 is obtained (see FIG. 3E). As the film carrier 10, it is also possible to use a single-sided wired circuit board having a wired circuit pattern and lands formed on one surface.

Next, an adhesive film is laminated on the semiconductor chip mounting side of the film carrier 10 to form an adhesive layer 61.
Then, an opening 62 for joining the bump of the semiconductor chip and the land 41a is formed on the adhesive layer 61 on the land 41a by laser processing, and smear generated by the laser processing and remaining of the bottom of the opening 62 are formed. To remove the film, the adhesive layer 61
The surface and the opening 62 are dry-cleaned to obtain the printed circuit board 100 of the present invention (FIG. 3).
(See (f)).

The adhesive layer 61 is based on polyimide resin, epoxy resin, silicone resin, acrylic resin, polyester resin, fluororesin, polyphenyl ether resin, etc. and has the above-mentioned physical properties (dynamic elastic modulus, area increase rate). It is obtained by laminating the adhesive film prepared so as to obtain (1) under predetermined conditions. Table 1 shows the measurement data of the dynamic elastic modulus and the area increase rate of the adhesive film prototyped this time. The measurement was carried out by the test method for temperature dependence of dynamic elasticity of plastic according to the non-resonant forced vibration method of JIS K7244-4 Plastic-Dynamic mechanical property test method.

[0013]

[Table 1]

As the laminator, a vacuum type or an atmospheric pressure type roll or press type can be used, but a vacuum type is preferable from the viewpoint of embedding between wiring circuit patterns. As the laser processing machine, generally known excimer laser, UV-YAG and carbonic acid laser can be used. However, when the opening is formed with a laser processing machine, the processing shape and the degree of smear differ depending on the model, and since the carbon dioxide laser is a processing method by heat, the sealing performance deteriorates due to the hardening of the adhesive layer around the via hole. Therefore, excimer laser and UV-YAG laser are preferable. Opening 6
The size of 2 is set in consideration of the bump size and the adhesive layer thickness of the semiconductor chip, the diameter of the opening 62 is slightly larger than the bump diameter of the semiconductor chip, and the bump height of the semiconductor chip is equal to or larger than the adhesive layer thickness. It may be designed to be higher so that the volume when the bump is bonded to the land and crushed is about the same as the volume of the opening.

As a method of cleaning the surface of the adhesive layer 61 and the opening 62, since the adhesive layer 61 is the B stage, the phenomenon of peeling due to permeation to the adhesive interface is recognized in the wet system, and is limited to the dry system treatment. It Introduced gases for dry cleaning are argon, oxygen,
Although it is possible to use a mixed gas such as fluorine-based gas, the adhesive layer 6
It is necessary to consider the thermal damage of No. 1, and it is desirable to use a fluorine-based mixed gas that can suppress the reaction temperature rise. Although the film carrier 10 has been described with respect to the example in which the wiring circuit pattern and the land are formed on both sides, a single-sided wiring board in which the wiring circuit pattern and the land are formed on one side can also be used.

FIGS. 4A to 4C are partial sectional views of a semiconductor package 200 on which a semiconductor chip 70 is mounted using the wired circuit board 100 of the present invention. Adhesive layer 6 in which openings 62 are formed using the printed circuit board 100 of the present invention
1. The bumps 71 of the semiconductor chip 70 are inserted into the semiconductor chip 1 and pressured and heated to perform eutectic bonding between the bumps 71 and the lands 41a and to bond the semiconductor chip 71 to the adhesive layer 61, thereby forming the bumps 71 and the wiring circuit pattern. It is possible to obtain the semiconductor package 200 in which the land 41a at the end 41b is electrically connected. Here, the bump 71 is crushed to the gap thickness of the adhesive layer 61, and the periphery thereof is completely sealed by the adhesive layer 61.

[0017]

The present invention will be described in detail with reference to the following examples.
First, Microlux HP (DuPont / SQ-) in which ultrathin copper foils 12 and 13 are formed on both surfaces of the insulating substrate 11.
VLP: Mitsui Kinzoku: 9/25/9 micron thickness), and using a UV-YAG laser device (Sumitomo Heavy Industries, Ltd.) from one side of the insulating base material 11 to the copper foil 12 and the insulating base material 11. Drilling was performed to form via holes 21 (see FIGS. 3A and 3B). Next, the protective layer 14 is formed on the copper foil 13 on the other surface of the insulating base material 11, and the via hole 21 is formed.
Of the copper foil 13 is used as a cathode to perform electrolytic copper plating to form a conductor layer 41 in which a copper plating layer 32 is formed on the filled via 31 and the copper foil 12 (see FIG. 3C. )reference).

Next, the conductor layer 41 and the copper foil 13 on both surfaces of the insulating base material 11 are patterned to form a wiring circuit pattern 41.
b and the land 41a at the end of the wiring circuit pattern 41b and the land 13a on the back surface were formed (see FIG. 3D). Next, after forming the solder resist pattern 51, electrolytic nickel plating and electrolytic gold plating are sequentially performed to form the wiring circuit pattern 4.
A film carrier 10 in which a nickel film having a thickness of 2 μm and a gold film having a thickness of 0.1 μm were formed on the land 1b, the land 41a, and the land 13a was obtained (see FIG. 3E).

Next, a thermosetting polyimide adhesive film of N0.4 (manufactured by Nippon Steel Chemical Co., Ltd.) in Table 1 above was mounted on the semiconductor chip mounting surface of the film carrier 10 with a vacuum laminator (manufactured by Nichigo Morton Co.). 100 ° C, pressure 0.
50MPa, laminating time 60 seconds, and laminating, 50
An adhesive layer 61 having a thickness of μm is formed, and a 60 μmφ opening 6 is formed at a predetermined position of the adhesive layer 61 by a UV-YAG laser processing machine.
Formed 2. Further, in order to remove the smear generated by the laser processing and the resin residual film on the bottom of the opening 62, dry cleaning is performed with a CF ₄ / O ₂ mixed gas system with a plasma ashing device to obtain the printed circuit board 100 of the present invention. Obtained (see FIG. 3 (f)).

The above-mentioned printed circuit board 100 of the present invention and the semiconductor chip 70 on which the gold bumps 71 (bump diameter: 50 μmφ, height: 60 μm) are formed are thermocompression-bonded at a mounting temperature of 300 ° C., and the bumps 71 and lands 41a are gold-plated. -Gold eutectic bonding,
The electrical continuity is ensured and the bumps 7 are formed on the adhesive layer 61.
1 was completely sealed, and then the adhesive layer 61 was completely cured to obtain the semiconductor package 200.

[0021]

Since the printed circuit board of the present invention has the above-mentioned structure, it enables fine and high-density semiconductor mounting, and can easily and inexpensively provide a printed circuit board.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing an embodiment of a printed circuit board of the present invention.

FIG. 2 is a partial cross-sectional view showing an example of a semiconductor package using the wired circuit board of the present invention.

3A to 3F are partial configuration cross-sectional views showing an example of a method for manufacturing a wired circuit board of the present invention in the order of steps.

4A to 4C are explanatory views showing a state in which a semiconductor chip is mounted using the wired circuit board of the present invention.

[Explanation of symbols]

10: Film carrier 11 ... Insulating base material 12, 13 ... Copper foil 13a, 41a ... Land 14 ... Protective layer 21 ... Via hole 31 …… Filled beer 32: Copper plating layer 41 ... Conductor layer 41b ... wiring circuit pattern 51 ... Solder resist pattern 61 ... Adhesive layer 62 ... Opening 70 ... Semiconductor chip 71 ... Bump 100: Wiring circuit board 200 ... Semiconductor package

Claims (2)

[Claims] 1. A wiring circuit board comprising a film carrier having a wiring circuit pattern, and an adhesive layer having an opening for securing adhesion and electrical continuity of a semiconductor chip, the movement of the adhesive layer. Elastic modulus E ′ is a temperature range (100 to 1) for laminating an adhesive film on a film carrier.
E ′ = 8 × 10 ⁸ Pa or less at 80 ° C., E ′ = 5 × 10 ⁶ P in the mounting temperature range of the semiconductor chip (250 to 310 ° C.)
A printed circuit board characterized by being a or less. 2. The area increase rate of the adhesive layer is 150% or more and 3 in the mounting temperature range (250 to 310 ° C.) of the semiconductor chip.
It is less than 00%, The wired circuit board of Claim 1 characterized by the above-mentioned.