JP2003124469A - Thin film transistor and manufacturing method thereof - Google Patents

Thin film transistor and manufacturing method thereof

Info

Publication number
JP2003124469A
JP2003124469A JP2001310855A JP2001310855A JP2003124469A JP 2003124469 A JP2003124469 A JP 2003124469A JP 2001310855 A JP2001310855 A JP 2001310855A JP 2001310855 A JP2001310855 A JP 2001310855A JP 2003124469 A JP2003124469 A JP 2003124469A
Authority
JP
Japan
Prior art keywords
thin film
film
film transistor
silicon
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001310855A
Other languages
Japanese (ja)
Inventor
Toshihiko Itoga
敏彦 糸賀
Yukio Takasaki
幸男 高嵜
Takuo Kaito
拓生 海東
Naohiro Kamo
尚広 賀茂
Osamu Okura
理 大倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001310855A priority Critical patent/JP2003124469A/en
Publication of JP2003124469A publication Critical patent/JP2003124469A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To solve problems that, when a single layer of a silicon nitride film is used as the ground, a level of an interface increases and element characteristics are deteriorated and that, when a ground film is an oxide film formed by a PE-CVD method, the level of the interface also increases, since the film contains many defects and impurities, and the element characteristics are deteriorated. SOLUTION: As to the problem that the levels of the silicon nitride film and the interface of a semiconductor thin film are increased, the surface of the silicon nitride film is oxidized to make the surface portion be a silicon oxy-nitride film. As for the problem due to the defects and impurities of the silicon oxide film formed by the PE-CVD method, the silicon oxide film obtained by oxidizing a silicon thin film is used.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は薄膜トランジスタに
係わり、特に画像表示装置用ドライバおよびその周辺回
路を構成するのに好適な低温工程(650℃以下)で作
製される多結晶シリコン薄膜トランジスタ(低温pol
y−SiTFT)に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a polycrystalline silicon thin film transistor (low temperature pol) manufactured by a low temperature process (650 ° C. or lower) suitable for forming a driver for an image display device and its peripheral circuits.
y-Si TFT).

【0002】[0002]

【従来の技術】従来の液晶ディスプレイ(LCD)用の
薄膜トランジスタの構造は、絶縁基板上に窒化シリコン
膜あるいは、酸化シリコン膜をCVD(Chemica
l vapor deposition)法により形成
し、基板からの不純物拡散を抑制する拡散防止膜として
用いることが一般的である。この場合のCVD法は、低
温poly−SiTFTにおいては、PE−CVD法が
一般的に使用される。
2. Description of the Related Art A conventional structure of a thin film transistor for a liquid crystal display (LCD) has a structure in which a silicon nitride film or a silicon oxide film is formed on a insulating substrate by CVD (Chemical).
In general, it is formed by a vapor deposition method and used as a diffusion prevention film that suppresses the diffusion of impurities from the substrate. As the CVD method in this case, the PE-CVD method is generally used in the low temperature poly-Si TFT.

【0003】[0003]

【発明が解決しようとする課題】上記従来技術には以下
の課題がある。下地が窒化シリコン膜単層である場合、
拡散防止効果は十分であるが、TFTの半導体層が窒化
シリコンと接するため、界面の準位が増大して、素子特
性が悪くなる問題がある。また、半導体層と接する下地
膜が酸化シリコン膜である場合、PE−CVD法により
形成した酸化膜は、多くの欠陥および不純物を含むた
め、やはり界面の準位が多く、素子特性が悪くなってし
まう。特に、PE−CVDで形成した酸化シリコン膜
は、炭素、フッ素、OH基およびHOを多く含むた
め、TFTのしきい値電圧を制御しにくい、TFTの特
性が劣化し易い、といった問題がある。
The above-mentioned conventional techniques have the following problems. When the base is a silicon nitride film single layer,
Although the diffusion prevention effect is sufficient, there is a problem in that the semiconductor layer of the TFT is in contact with silicon nitride, the level of the interface increases, and the device characteristics deteriorate. Further, when the base film in contact with the semiconductor layer is a silicon oxide film, the oxide film formed by the PE-CVD method contains many defects and impurities, so that the interface level is also large and the device characteristics deteriorate. I will end up. In particular, since the silicon oxide film formed by PE-CVD contains a large amount of carbon, fluorine, OH groups and H 2 O, it is difficult to control the threshold voltage of the TFT and the characteristics of the TFT are likely to deteriorate. is there.

【0004】[0004]

【課題を解決するための手段】上記問題は、以下の手段
により解決される。まず、窒化シリコン膜と半導体薄膜
界面の準位が多いという問題については、窒化シリコン
膜表面を酸化し、表面部分を酸窒化シリコン膜とするこ
とにより解決できる。また、PE−CVD法で形成した
酸化シリコン膜の欠陥、不純物に起因する問題について
は、酸化シリコン膜をCVD法で形成するのではなく、
シリコン薄膜を酸化した酸化シリコン膜を使用すること
により解決できる。またこの際の酸化の方法としては、
加熱したガスを基板に吹き付け、短時間に酸化を行うこ
とにより、基板温度上昇を抑制して酸化を行うことが有
効である。また、酸素プラズマ酸化等の低温で酸化が可
能な方法を用いてもよい。
The above problems can be solved by the following means. First, the problem that there are many levels at the interface between the silicon nitride film and the semiconductor thin film can be solved by oxidizing the surface of the silicon nitride film and making the surface portion a silicon oxynitride film. Regarding the problem caused by the defects and impurities of the silicon oxide film formed by the PE-CVD method, the silicon oxide film is not formed by the CVD method but
This can be solved by using a silicon oxide film obtained by oxidizing a silicon thin film. In addition, as a method of oxidation in this case,
It is effective to blow the heated gas to the substrate and perform the oxidation in a short time to suppress the temperature rise of the substrate and perform the oxidation. Alternatively, a method capable of oxidizing at low temperature such as oxygen plasma oxidation may be used.

【0005】[0005]

【発明の実施の形態】(実施例1)図1に本発明を適用
して作製したCMOS TFTの断面図を示す。ここ
で、同図(a)はCMOS TFTのNMOSトランジ
スタ部、同図(b)はPMOSトランジスタ部である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 shows a sectional view of a CMOS TFT manufactured by applying the present invention. Here, FIG. 1A shows an NMOS transistor portion of a CMOS TFT, and FIG. 1B shows a PMOS transistor portion.

【0006】まず、ガラス基板101上に下地膜(保護
膜)として、PE−CVDにより、SiN膜102およ
びa−Si膜103をそれぞれ100nmおよび10n
mの厚さで形成した。上記a−Si膜表面103に、7
00℃加熱した水蒸気を吹き付けることにより、完全に
酸化シリコン膜に酸化した。この際の酸化時間は、数分
であり、a−Si膜103の温度は700℃にまで上昇
するが、ガラス基板101の温度は600℃以下である
ので、ガラスを変形させずに酸化が可能である。
First, as a base film (protective film) on a glass substrate 101, a SiN film 102 and an a-Si film 103 are formed by PE-CVD to 100 nm and 10 n, respectively.
It was formed with a thickness of m. 7 on the surface 103 of the a-Si film
By blowing steam heated at 00 ° C., the silicon oxide film was completely oxidized. The oxidation time at this time is several minutes, and the temperature of the a-Si film 103 rises to 700 ° C., but the temperature of the glass substrate 101 is 600 ° C. or lower, so that the oxidation is possible without deforming the glass. Is.

【0007】用いるガスは、水蒸気に限らず、O、N
O、NOか、Oと塩化水素、O と塩素の混合ガス
か、それらの混合ガスを含む雰囲気を用いてもよい。
The gas to be used is not limited to water vapor, but may be OTwo, N
O, NTwoO or OTwoAnd hydrogen chloride, O TwoGas mixture of chlorine
Alternatively, an atmosphere containing a mixed gas thereof may be used.

【0008】その後に、PE−CVD法によりa−Si
膜を50nm堆積し、エキシマレーザアニールによりp
oly−Si膜(106,107,108に相当)とし
た。この膜を、レジストマスクを用いてドライエッチン
グにより島状に加工した後に、100nmのゲートSi
膜104をPE−CVDにより作製し、150nm
のゲート電極105をスパッタ法により形成した。この
際に、上記と同じ方法により、56nmのpoly−S
i表面を10nm酸化した後に、ゲートSiO 膜10
4を90nm形成したTFTも作製した。
Then, a-Si is formed by PE-CVD method.
A film of 50 nm is deposited, and p is formed by excimer laser annealing.
As an poly-Si film (corresponding to 106, 107, 108)
It was This film is dry-etched using a resist mask.
100nm gate Si after processed into islands by
OTwoThe film 104 is formed by PE-CVD and has a thickness of 150 nm.
The gate electrode 105 was formed by the sputtering method. this
In this case, the same method as above was used to obtain 56 nm of poly-S.
After 10 nm oxidation of i surface, gate SiO TwoMembrane 10
A TFT in which 4 was formed to 90 nm was also manufactured.

【0009】上記工程後、NMOSトランジスタ部につ
いては、レジストマスクを用いたPイオン打ち込みによ
り、n層106およびLDD(lightly do
ped drain)層107を作成し、PMOSトラ
ンジスタ部については、Bイオン打ち込みによりp
108を形成し、CMOSトランジスタを作製した。
After the above steps, with respect to the NMOS transistor portion, the n + layer 106 and the LDD (lightly do) are implanted by P ion implantation using a resist mask.
A ped drain) layer 107 was formed, and for the PMOS transistor portion, ap + layer 108 was formed by B ion implantation to manufacture a CMOS transistor.

【0010】上記TFT作製工程後、PE−CVD法に
より、SiOの層間絶縁膜109、Al合金配線11
0を形成した。パッシベーション膜としてPE−CVD
によりSiO膜111およびSiN膜112を形成
し、コンタクトホールを形成した後、透明電極としてI
TO(Indium Titanium Oxide)
膜113を形成し、液晶駆動用のトランジスタおよび回
路用のCMOSトランジスタを完成した。その後、液晶
工程を行い、LCDの画素部を作製した。
After the above-mentioned TFT manufacturing process, the interlayer insulating film 109 of SiO 2 and the Al alloy wiring 11 are formed by the PE-CVD method.
Formed 0. PE-CVD as a passivation film
After forming the SiO 2 film 111 and the SiN film 112 by the contact hole and forming the contact hole, I
TO (Indium Titanium Oxide)
A film 113 was formed to complete a liquid crystal driving transistor and a circuit CMOS transistor. Then, a liquid crystal process was performed to fabricate a pixel portion of the LCD.

【0011】a−Siを酸化した下地膜を使用した場
合、PE−CVD膜のみで下地膜を形成した場合に比
べ、トランジスタのオン電流が20〜30%程度増加し
た。また、ドレインアバランシェホットホール劣化条件
で寿命を評価した場合、TFTのオン抵抗の10%劣化
寿命で比較すると、PE−CVD膜の下地膜の場合、1
sec程度であるのに対し、熱酸化膜を用いた場合
には、10sec以上と、一桁以上長くなった。
In the case of using a base film obtained by oxidizing a-Si,
In the case of forming a base film only with PE-CVD film,
On the other hand, the on-current of the transistor increases by about 20 to 30%.
It was Also, drain avalanche hot hole deterioration conditions
10% deterioration of TFT on-resistance
Comparing the lifetimes, in the case of the base film of the PE-CVD film, 1
0 FourIt is about sec, but when using a thermal oxide film
Is 105It became more than an order of magnitude longer than sec.

【0012】さらに、poly−Si表面を酸化して形
成したSiO膜を含むゲート酸化膜を使用した場合、
寿命は、10sec以上と極めて信頼性の高いTFT
が得られた。この際、poly−Si表面を酸化して形
成したSiO膜に変え、poly−Si表面をNH
で窒化して形成したSiN膜あるいは、そのSiN膜を
さらに酸化して形成したSiON膜を用いてもTFT信
頼性向上効果がある。
Further, when a gate oxide film including a SiO 2 film formed by oxidizing the poly-Si surface is used,
Extremely reliable TFT with a life of 10 6 sec or more
was gotten. At this time, the poly-Si surface was changed to a SiO 2 film formed by oxidation, and the poly-Si surface was changed to NH 3 film.
Even if a SiN film formed by nitriding the SiN film or a SiON film formed by further oxidizing the SiN film is used, the TFT reliability improving effect can be obtained.

【0013】下地膜として、PE−CVD法により形成
したSiN膜に変えて、a−Si膜をNHガスにより
窒化した膜を用いることも可能である。この場合、Si
N膜中の固定電荷が少なく、TFTのしきい値電圧制御
が容易であり、性能がよく、特性の揃ったTFTが得ら
れる。 (実施例2)図2に本発明を適用して作製した他の実施
例のCMOSTFTの断面図を示す。ここで、同図
(a)はCMOS TFTのNMOSトランジスタ部、
同図(b)はPMOSトランジスタ部である。
Instead of the SiN film formed by the PE-CVD method, a film obtained by nitriding the a-Si film with NH 3 gas can be used as the base film. In this case Si
A fixed charge in the N film is small, the threshold voltage of the TFT can be easily controlled, and the TFT having good performance and uniform characteristics can be obtained. (Embodiment 2) FIG. 2 shows a sectional view of a CMOS TFT of another embodiment produced by applying the present invention. Here, FIG. 1A shows the NMOS transistor part of the CMOS TFT,
FIG. 3B shows a PMOS transistor section.

【0014】まず、ガラス基板101上に下地膜とし
て、PE−CVDにより、SiN201を100nmの
厚さで形成した。このSiN膜表面を700℃に加熱し
た水蒸気を吹き付けることにより酸化し、表面を酸素リ
ッチな酸窒化膜202とした。この際に、ガラス基板に
変形が生じないのは実施例1と同様であり、用いるガス
は、他の酸化性ガスでもよい。
First, SiN201 was formed as a base film on the glass substrate 101 by PE-CVD to a thickness of 100 nm. The surface of this SiN film was oxidized by blowing water vapor heated to 700 ° C. to form an oxygen-rich oxynitride film 202 on the surface. At this time, the glass substrate is not deformed as in Example 1, and the gas used may be another oxidizing gas.

【0015】上記工程後、実施例1と同様にNMOSト
ランジスタおよびPMOSトランジスタを作製した。S
iNを酸化した下地膜を使用した場合、PE−CVDの
みで下地膜を形成した場合に比べ、トランジスタのオン
電流が10〜20%程度増加した。また、TFTのオン
抵抗の10%劣化の寿命で比較すると、PE−CVD膜
の下地膜の場合、10sec程度であるのに対し、熱
酸化膜を用いた場合には、10sec以上と、一桁以
上長くなった。また、実施例1と同様に、ゲート酸化膜
にpoly−Siの熱酸化膜を一部使用した場合は、さ
らに寿命が長くなる効果がある。 (実施例3)図3に実施例1および2で作製したTFT
を用いて作製した液晶表示装置の構成図を示す。LCD
はゲートドライバ回路301とドレインドライバ回路3
02と画像表示部303から構成され、ゲートドライバ
回路301およびドレインドライバ回路302はCMO
S TFT304により構成した。画像表示部303は
ゲート線305と信号線306とをマトリクス状に形成
した。
After the above steps, an NMOS transistor and a PMOS transistor were manufactured in the same manner as in Example 1. S
When the base film formed by oxidizing iN was used, the on-current of the transistor was increased by about 10 to 20% as compared with the case where the base film was formed only by PE-CVD. Further, when compared with the life of 10% deterioration of the on resistance of the TFT, it is about 10 4 sec in the case of the base film of the PE-CVD film, whereas it is 10 5 sec or more in the case of using the thermal oxide film. It became longer than an order of magnitude. Further, as in the first embodiment, when a part of the poly-Si thermal oxide film is used as the gate oxide film, there is an effect that the life is further extended. (Example 3) FIG. 3 shows TFTs manufactured in Examples 1 and 2.
FIG. 3 shows a configuration diagram of a liquid crystal display device manufactured using. LCD
Is a gate driver circuit 301 and a drain driver circuit 3
02 and an image display unit 303, and the gate driver circuit 301 and the drain driver circuit 302 are CMOs.
It is composed of STFT 304. The image display unit 303 has gate lines 305 and signal lines 306 formed in a matrix.

【0016】上記LCDは、良好な性能を示し、特にL
CD寿命は、各LCDともに10000時間以上であ
り、寿命の長いLCDが得られた。
The above LCD exhibits good performance, especially L
The CD life was 10,000 hours or more for each LCD, and an LCD with a long life was obtained.

【0017】[0017]

【発明の効果】上述のように、本発明によれば、下地と
半導体薄膜界面が良質なTFTが作製でき、初期特性が
よく、信頼性の高いTFTが得られ、寿命の長いLCD
が得られる。
As described above, according to the present invention, a TFT having a good interface between a base and a semiconductor thin film can be manufactured, a TFT having good initial characteristics and high reliability can be obtained, and an LCD having a long life can be obtained.
Is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施のTFT作製工程を説明するた
めの断面図。
FIG. 1 is a cross-sectional view for explaining a TFT manufacturing process of one embodiment of the present invention.

【図2】本発明の他の実施例によるTFT作製工程を説
明するための断面図。
FIG. 2 is a cross-sectional view for explaining a TFT manufacturing process according to another embodiment of the present invention.

【図3】LCDの構成を示す回路図。FIG. 3 is a circuit diagram showing a configuration of an LCD.

【符号の説明】[Explanation of symbols]

101…ガラス基板、102、201…SiN膜、10
3…a−Siを酸化したSiO膜、104…ゲート酸
化膜、105…ゲート電極、106…n層 107…LDD層、108…p層、109…層間Si
膜、110…Al合金配線、111…パッシベーシ
ョンSiO膜、112…パッシベーションSiN膜、
113…ITO電極、202…酸窒化シリコン膜。
101 ... Glass substrate, 102, 201 ... SiN film, 10
3 ... SiO 2 film obtained by oxidizing a-Si, 104 ... Gate oxide film, 105 ... Gate electrode, 106 ... N + layer 107 ... LDD layer, 108 ... P + layer, 109 ... Inter-layer Si
O 2 film, 110 ... Al alloy wiring, 111 ... Passivation SiO 2 film, 112 ... Passivation SiN film,
113 ... ITO electrode, 202 ... Silicon oxynitride film.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 海東 拓生 千葉県茂原市早野3300番地 株式会社日立 製作所ディスプレイグループ内 (72)発明者 賀茂 尚広 千葉県茂原市早野3300番地 株式会社日立 製作所ディスプレイグループ内 (72)発明者 大倉 理 千葉県茂原市早野3300番地 株式会社日立 製作所ディスプレイグループ内 Fターム(参考) 5F058 BC02 BC11 BF62 BF63 BF72 BJ01 5F110 AA14 BB02 BB04 CC02 DD02 DD13 DD14 DD15 DD17 EE44 FF02 FF03 FF04 FF07 FF23 FF26 FF30 GG02 GG13 GG25 GG45 HJ01 HJ13 HL06 HL07 HM15 NN03 NN23 NN24 NN35 PP03    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takuo Kaito             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Factory Display Group (72) Inventor Naohiro Kamo             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Factory Display Group (72) Osamu Okura             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Factory Display Group F term (reference) 5F058 BC02 BC11 BF62 BF63 BF72                       BJ01                 5F110 AA14 BB02 BB04 CC02 DD02                       DD13 DD14 DD15 DD17 EE44                       FF02 FF03 FF04 FF07 FF23                       FF26 FF30 GG02 GG13 GG25                       GG45 HJ01 HJ13 HL06 HL07                       HM15 NN03 NN23 NN24 NN35                       PP03

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】耐熱性650℃以下の絶縁体基板上に形成
されている薄膜トランジスタであり、薄膜トランジスタ
は、最低限、半導体薄膜、ゲート絶縁膜、ゲート電極か
らなり、前記薄膜トランジスタと絶縁基板間には、最低
限1層の絶縁基板保護膜が形成されており、薄膜トラン
ジスタの半導体薄膜と接する絶縁体基板保護膜は、シリ
コン薄膜を酸化したシリコン酸化膜であることを特徴と
する薄膜トランジスタ。
1. A thin film transistor formed on an insulating substrate having a heat resistance of 650 ° C. or lower, wherein the thin film transistor comprises at least a semiconductor thin film, a gate insulating film, and a gate electrode, and a thin film transistor is provided between the thin film transistor and the insulating substrate. A thin film transistor characterized in that at least one insulating substrate protective film is formed, and the insulating substrate protective film in contact with the semiconductor thin film of the thin film transistor is a silicon oxide film obtained by oxidizing a silicon thin film.
【請求項2】請求項1記載の酸化は、酸素、水蒸気、オ
ゾン、プラズマ酸素、NO、NO、塩化水素、塩素の
うち、少なくとも一種のガスを含む雰囲気中で行うこと
を特徴とする薄膜トランジスタの作製方法。
2. The oxidation according to claim 1 is performed in an atmosphere containing at least one gas selected from oxygen, water vapor, ozone, plasma oxygen, N 2 O, NO, hydrogen chloride and chlorine. Method for manufacturing thin film transistor.
【請求項3】請求項1記載の薄膜トランジスタにおい
て、半導体薄膜と接するシリコン酸化膜は、少なくとも
一部が、薄膜トランジスタを構成する半導体薄膜とは異
なる層のシリコン膜と接していることを特徴とする薄膜
トランジスタ。
3. The thin film transistor according to claim 1, wherein at least a part of the silicon oxide film in contact with the semiconductor thin film is in contact with a silicon film in a layer different from the semiconductor thin film forming the thin film transistor. .
【請求項4】耐熱性650℃以下の絶縁体基板上に形成
されている薄膜トランジスタであり、薄膜トランジスタ
は、最低限、半導体薄膜、ゲート絶縁膜、ゲート電極か
らなり、前記薄膜トランジスタと絶縁基板間には、最低
限1層の絶縁基板保護膜が形成されており、薄膜トラン
ジスタの半導体薄膜と接する絶縁基板保護膜は、シリコ
ン酸化膜であり、シリコン酸化膜の少なくとも一部の領
域中の炭素、フッ素、水素のうちのいずれかの元素濃度
は、1×1019/cm以下、好ましくは1×10
18/cm以下であることを特徴とする薄膜トランジ
スタ。
4. A thin film transistor formed on an insulating substrate having a heat resistance of 650 ° C. or less, the thin film transistor including at least a semiconductor thin film, a gate insulating film, and a gate electrode, and a thin film transistor between the thin film transistor and the insulating substrate. At least one layer of the insulating substrate protective film is formed, and the insulating substrate protective film in contact with the semiconductor thin film of the thin film transistor is a silicon oxide film, and carbon, fluorine, hydrogen in at least a part of the region of the silicon oxide film. The element concentration of any of the above is 1 × 10 19 / cm 3 or less, preferably 1 × 10
A thin film transistor having a density of 18 / cm 3 or less.
【請求項5】耐熱性650℃以下の絶縁体基板上に形成
されている薄膜トランジスタであり、薄膜トランジスタ
は、最低限、半導体薄膜、ゲート絶縁膜、ゲート電極か
らなり、前記薄膜トランジスタと絶縁基板間には、最低
限1層の絶縁基板保護膜が形成されており、絶縁基板保
護膜は酸窒化シリコン膜を含み、酸窒化シリコン膜は、
窒化シリコン膜形成後に表面を酸化して形成した酸窒化
シリコン膜であることを特徴とする薄膜トランジスタ。
5. A thin film transistor formed on an insulating substrate having a heat resistance of 650 ° C. or lower, the thin film transistor including at least a semiconductor thin film, a gate insulating film, and a gate electrode, and a thin film transistor between the thin film transistor and the insulating substrate. At least one layer of the insulating substrate protective film is formed, and the insulating substrate protective film includes a silicon oxynitride film, and the silicon oxynitride film is
A thin film transistor, which is a silicon oxynitride film formed by oxidizing a surface after forming a silicon nitride film.
【請求項6】請求項1または5に記載のシリコン薄膜お
よび窒化シリコン膜の酸化は、酸化性のガスを加熱して
シリコン膜および窒化シリコン膜に吹き付ける方法で行
うことを特徴とした薄膜トランジスタの作製方法。
6. Fabrication of a thin film transistor, characterized in that the oxidation of the silicon thin film and the silicon nitride film according to claim 1 or 5 is performed by a method of heating an oxidizing gas and spraying it on the silicon film and the silicon nitride film. Method.
【請求項7】請求項1から6のいずれか記載の薄膜トラ
ンジスタにおいて、ゲート絶縁膜の少なくとも一部は、
薄膜トランジスタを形成する半導体薄膜を酸化して得ら
れた酸化膜を含むことを特徴とする薄膜トランジスタ。
7. The thin film transistor according to claim 1, wherein at least a part of the gate insulating film is
A thin film transistor comprising an oxide film obtained by oxidizing a semiconductor thin film forming a thin film transistor.
JP2001310855A 2001-10-09 2001-10-09 Thin film transistor and manufacturing method thereof Pending JP2003124469A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7550328B2 (en) 2007-01-31 2009-06-23 Sony Corporation Method for production of thin-film semiconductor device
US7557416B2 (en) 2003-12-03 2009-07-07 Sharp Kabushiki Kaisha Transistor and CVD apparatus used to deposit gate insulating film thereof
JP2009188282A (en) * 2008-02-08 2009-08-20 National Institute Of Advanced Industrial & Technology Manufacturing method of high-density silicon oxide film, and silicon substrate and semiconductor device with high-density silicon oxide film manufactured by the same
JP2015019091A (en) * 2006-05-26 2015-01-29 株式会社半導体エネルギー研究所 Semiconductor device manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7557416B2 (en) 2003-12-03 2009-07-07 Sharp Kabushiki Kaisha Transistor and CVD apparatus used to deposit gate insulating film thereof
JP2015019091A (en) * 2006-05-26 2015-01-29 株式会社半導体エネルギー研究所 Semiconductor device manufacturing method
US9231070B2 (en) 2006-05-26 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor memory device and manufacturing method thereof, semiconductor device and manufacturing method thereof, and manufacturing method of insulating film
US7550328B2 (en) 2007-01-31 2009-06-23 Sony Corporation Method for production of thin-film semiconductor device
TWI399814B (en) * 2007-01-31 2013-06-21 Japan Display West Inc Method for manufacturing thin film semiconductor device
JP2009188282A (en) * 2008-02-08 2009-08-20 National Institute Of Advanced Industrial & Technology Manufacturing method of high-density silicon oxide film, and silicon substrate and semiconductor device with high-density silicon oxide film manufactured by the same

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