JP2002353458A - Thin film semiconductor element and manufacturing method therefor - Google Patents

Thin film semiconductor element and manufacturing method therefor

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Publication number
JP2002353458A
JP2002353458A JP2001156015A JP2001156015A JP2002353458A JP 2002353458 A JP2002353458 A JP 2002353458A JP 2001156015 A JP2001156015 A JP 2001156015A JP 2001156015 A JP2001156015 A JP 2001156015A JP 2002353458 A JP2002353458 A JP 2002353458A
Authority
JP
Japan
Prior art keywords
film
insulating film
gate insulating
gate
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001156015A
Other languages
Japanese (ja)
Inventor
Atsushi Sasaki
厚 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001156015A priority Critical patent/JP2002353458A/en
Publication of JP2002353458A publication Critical patent/JP2002353458A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a thin film semiconductor element of superior reliability and characteristics and its manufacturing method by using a gate insulating film, which prevents deterioration of the reliability of the thin film semiconductor element due to oxide formation of tungsten and deterioration of characteristic due to gate insulating film quality. SOLUTION: The thin film semiconductor element is provided with a silicon semiconductor film 2 having a prescribed form, a first gate insulating film 3 having a prescribed form, a second gate insulating film 4 having a prescribed form, and a gate electrode film 5; the first gate insulating film 3 is a silicon oxide film, where an absolute value of film stress is at most 300 MPa; the second gate insulating film 4 is a silicon oxinitride film; and the gate electrode film 5 is formed of alloy of molybdenum and tungsten.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体集積回路及び
液晶表示装置などに用いる薄膜半導体素子とその製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device used for a semiconductor integrated circuit, a liquid crystal display device, and the like, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】アクティブマトリックス方式の液晶表示
装置に多結晶シリコン薄膜トランジスタを用いるとトラ
ンジスタアレイと周辺回路を一体化できる。周辺回路の
一体化は、高精細な画像表示を実現し、また、低コスト
での製造を可能とする。多結晶シリコン薄膜トランジス
タの性能は、周辺回路の駆動特性と密接に関わっている
ため、高性能化が期待されている。
2. Description of the Related Art When a polycrystalline silicon thin film transistor is used in an active matrix type liquid crystal display device, a transistor array and peripheral circuits can be integrated. The integration of the peripheral circuit realizes high-definition image display and enables low-cost manufacturing. Since the performance of the polycrystalline silicon thin film transistor is closely related to the driving characteristics of peripheral circuits, higher performance is expected.

【0003】図3を用いて薄膜トランジスタの構造と、
これを作製するための従来の方法を説明する。薄膜トラ
ンジスタは石英あるいはガラスなどの基板1の表面に下
地膜10、シリコン半導体膜2、ゲート絶縁膜3、ゲー
ト電極膜5、ゲート配線膜6、層間絶縁膜7ソース及び
ドレイン電極膜8,9が設けられている。下地膜10は
基板1の構成成分が多結晶シリコン半導体膜2中に拡散
するのを防ぐ目的で形成されるが、基板1の材質や基板
の処理法の工夫によっては形成されない場合もある。
Referring to FIG. 3, the structure of a thin film transistor and
A conventional method for producing this will be described. The thin film transistor is provided with a base film 10, a silicon semiconductor film 2, a gate insulating film 3, a gate electrode film 5, a gate wiring film 6, an interlayer insulating film 7, source and drain electrode films 8, 9 on a surface of a substrate 1 such as quartz or glass. Have been. The base film 10 is formed for the purpose of preventing the constituent components of the substrate 1 from diffusing into the polycrystalline silicon semiconductor film 2, but may not be formed depending on the material of the substrate 1 and the method of processing the substrate.

【0004】ゲート絶縁膜3の材料には、酸化シリコン
や窒化シリコンが用いられることが多い。成膜はCVD
装置を用いて行われる。ゲート絶縁膜3の生成は、熱C
VDでもプラズマCVDでも可能であるが、多結晶シリ
コントランジスタの製造プロセスにおいては、プロセス
温度の低温化が望ましいのでプラズマCVDが用いられ
ることが多い。ゲート電極膜5は信号の遅延を防ぐため
低抵抗であり、ドーピングで注入したリンおよびボロン
の不純物を活性化する目的で行われる500〜600℃
の熱処理に耐えられることが求められる。低抵抗と耐熱
安定性を両立する材料として、MoとWの合金が提案さ
れている(特開平8−153722号公報)。
As a material of the gate insulating film 3, silicon oxide or silicon nitride is often used. Film formation is CVD
This is performed using a device. The gate insulating film 3 is formed by heat C
Although VD or plasma CVD is possible, plasma CVD is often used in the process of manufacturing a polycrystalline silicon transistor because it is desirable to lower the process temperature. The gate electrode film 5 has a low resistance in order to prevent delay of a signal, and is formed at a temperature of 500 to 600 ° C. for activating phosphorous and boron impurities implanted by doping.
Must be able to withstand the heat treatment. An alloy of Mo and W has been proposed as a material that achieves both low resistance and heat resistance stability (Japanese Patent Application Laid-Open No. 8-153722).

【0005】[0005]

【発明が解決しようとする課題】本発明者は、高温電圧
印加試験(B-T試験)で、従来の技術を用いて作製した
半導体薄膜素子の信頼性を評価した。高温電圧印加試験
は85〜150℃で、薄膜半導体素子のソースとドレイ
ンを接地しゲートに30Vを印加してトランジスタ特性
の時間変動を測定する方法である。そして、従来の技術
を用いた薄膜半導体素子においては、高温電圧印加試験
においてVthシフトが生じ、信頼性が不十分であるこ
とを見いだした。
The present inventor evaluated the reliability of a semiconductor thin film element manufactured by using the conventional technique in a high-temperature voltage application test (BT test). The high-temperature voltage application test is a method in which the source and drain of the thin film semiconductor device are grounded at a temperature of 85 to 150 ° C., and a voltage of 30 V is applied to the gate to measure the time variation of the transistor characteristics. Then, in a thin-film semiconductor device using the conventional technique, it has been found that a Vth shift occurs in a high-temperature voltage application test, resulting in insufficient reliability.

【0006】従来技術を用いた薄膜半導体素子におい
て、Vthシフトが大きくなる原因は、ゲート絶縁膜中
に含まれる水分とゲート電極膜中のタングステンが反応
し、タングステンの酸化物を生じるためであると考えら
れる。
In the thin film semiconductor device using the prior art, the reason why the Vth shift becomes large is that moisture contained in the gate insulating film reacts with tungsten in the gate electrode film to generate a tungsten oxide. Conceivable.

【0007】一方、ゲート絶縁膜の膜質と、薄膜半導体
素子の諸特性の関連を調べることにより、ゲート絶縁膜
の膜質によってサブスレッショルド特性の変動が生じる
という問題が見出されている。
On the other hand, by examining the relationship between the film quality of the gate insulating film and various characteristics of the thin-film semiconductor element, it has been found that the sub-threshold characteristic varies depending on the film quality of the gate insulating film.

【0008】本発明は、前記従来の問題を解決するた
め、タングステンの酸化物生成による薄膜半導体素子の
信頼性の劣化及びゲート絶縁膜質に起因する特性の劣化
を防止するゲート絶縁膜構成を用いることにより、信頼
性と特性に優れた薄膜半導体素子およびその製造方法を
提供することを目的とする。
In order to solve the above-mentioned conventional problems, the present invention uses a gate insulating film structure for preventing the deterioration of the reliability of a thin film semiconductor device due to the formation of tungsten oxide and the deterioration of characteristics due to the quality of the gate insulating film. Accordingly, an object of the present invention is to provide a thin-film semiconductor element having excellent reliability and characteristics and a method for manufacturing the same.

【0009】[0009]

【課題を解決するための手段】前記目的を達成するた
め、本発明の薄膜半導体素子は、透明絶縁性基板の表面
にシリコン半導体膜と、その表面のゲート絶縁膜と、そ
の表面のゲート電極膜と、その表面のゲート配線膜と、
前記ゲート電極膜を覆う層間絶縁膜と、前記シリコン半
導体膜から表面に導通するソース及びドレイン電極膜を
具備した薄膜半導体素子において、前記ゲート絶縁膜
が、第1のゲート絶縁膜と第2のゲート絶縁膜がこの順
番に形成され、前記第1のゲート絶縁膜が膜応力の絶対
値300MPa以下であるシリコン酸化膜であり、前記
第2のゲート絶縁膜がシリコン酸窒化膜であり、前記ゲ
ート電極膜がモリブデンとタングステンの合金であるこ
とを特徴とする。前記構成とすることにより、シリコン
半導体膜と第1のゲート絶縁膜との界面の界面応力が低
減され、薄膜半導体素子のサブスレッショルド特性の劣
化が防止されると共に、第2のゲート絶縁膜中に窒素が
存在することによりゲート絶縁膜中に含まれる水分とゲ
ート電極膜中のタングステンとの反応が抑制され、薄膜
半導体素子の信頼性の劣化が防止され、信頼性の高い薄
膜半導体素子を実現することができる。
In order to achieve the above object, a thin film semiconductor device according to the present invention comprises a silicon semiconductor film on a surface of a transparent insulating substrate, a gate insulating film on the surface, and a gate electrode film on the surface. And a gate wiring film on its surface,
In a thin film semiconductor device comprising an interlayer insulating film covering the gate electrode film, and source and drain electrode films conducting from the silicon semiconductor film to the surface, the gate insulating film has a first gate insulating film and a second gate. An insulating film is formed in this order; the first gate insulating film is a silicon oxide film having an absolute value of a film stress of 300 MPa or less; the second gate insulating film is a silicon oxynitride film; The film is an alloy of molybdenum and tungsten. With the above structure, interfacial stress at the interface between the silicon semiconductor film and the first gate insulating film is reduced, so that the subthreshold characteristics of the thin film semiconductor element are prevented from deteriorating. Due to the presence of nitrogen, the reaction between the moisture contained in the gate insulating film and the tungsten in the gate electrode film is suppressed, the deterioration of the reliability of the thin film semiconductor device is prevented, and a highly reliable thin film semiconductor device is realized. be able to.

【0010】前記素子においては、ゲート電極膜中に含
まれる酸素濃度よりも、前記第2のゲート絶縁膜中に含
まれる窒素の濃度が高いことが好ましい。より好ましく
は、ゲート電極膜中に含まれる酸素濃度よりも、前記第
2のゲート絶縁膜中に含まれる窒素の濃度が100〜7
00atomic%の範囲高いことが好ましい。前記の構成と
することにより、薄膜半導体素子の信頼性低下を更に効
果的に防止することができる。
In the above element, it is preferable that the concentration of nitrogen contained in the second gate insulating film is higher than the concentration of oxygen contained in the gate electrode film. More preferably, the second concentration is higher than the concentration of oxygen contained in the gate electrode film.
2. The concentration of nitrogen contained in the gate insulating film is 100 to 7
It is preferable that the range is as high as 00 atomic%. With the above configuration, it is possible to more effectively prevent a decrease in the reliability of the thin film semiconductor element.

【0011】また前記素子においては、第1のゲート絶
縁膜はテトラエトキシシランを原料ガスとしてプラズマ
CVDで成膜され、前記第2のゲート絶縁膜はクリプト
ンと窒素を放電ガスに用いてスパッタ成膜されているこ
とが好ましい。
In the above device, the first gate insulating film is formed by plasma CVD using tetraethoxysilane as a source gas, and the second gate insulating film is formed by sputtering using krypton and nitrogen as a discharge gas. It is preferred that

【0012】次に本発明の薄膜半導体素子の製造方法
は、透明絶縁性基板の表面にシリコン半導体膜と、その
表面のゲート絶縁膜と、その表面のゲート電極膜と、そ
の表面のゲート配線膜と、前記ゲート電極膜を覆う層間
絶縁膜と、前記シリコン半導体膜から表面に導通するソ
ース及びドレイン電極膜を具備した薄膜半導体素子の製
造方法において、前記ゲート絶縁膜として、第1のゲー
ト絶縁膜と第2のゲート絶縁膜とをこの順番に形成し、
前記第1のゲート絶縁膜はテトラエトキシシランを原料
ガスとしてプラズマCVDで成膜し、前記第2のゲート
絶縁膜はクリプトンと窒素を放電ガスに用いてスパッタ
成膜し、前記ゲート電極膜は、モリブデンとタングステ
ンの合金膜を放電ガスにアルゴンを用いてスパッタによ
り成膜することを特徴とする。
Next, a method of manufacturing a thin-film semiconductor device according to the present invention comprises the steps of: providing a silicon semiconductor film on a surface of a transparent insulating substrate; a gate insulating film on the surface; a gate electrode film on the surface; And a method of manufacturing a thin film semiconductor device comprising: an interlayer insulating film covering the gate electrode film; and a source and drain electrode film conducting from the silicon semiconductor film to the surface, wherein the first gate insulating film is used as the gate insulating film. And a second gate insulating film are formed in this order,
The first gate insulating film is formed by plasma CVD using tetraethoxysilane as a source gas, the second gate insulating film is formed by sputtering using krypton and nitrogen as a discharge gas, and the gate electrode film is formed by: An alloy film of molybdenum and tungsten is formed by sputtering using argon as a discharge gas.

【0013】前記の製造方法において、第1のゲート絶
縁膜をテトラエトキシシランを原料ガスとして、プラズ
マCVDで成膜すれば膜応力の制御範囲が広く、第1の
ゲート絶縁膜を300MPa以下の低応力に調整するのが
容易となり、薄膜半導体素子のサブスレッショルド特性
の劣化が効果的に防止される。また、第2のゲート絶縁
膜をクリプトンと窒素を放電ガスに用いてスパッタ成膜
することは、放電ガスとして通常用いられるアルゴンに
対してクリプトンは原子半径が大きく、成膜時に膜中へ
打ち込まれることが少ないという特徴を有しており、窒
素のみを第2の絶縁膜中に残留させ、クリプトンが第2の
絶縁膜及び第1の絶縁膜に打ち込まれて絶縁膜中に欠陥
を生じることを防止するという効果を有しており、ゲー
ト絶縁膜中に含まれる水分とゲート電極膜中のタングス
テンとの反応をより効果的に抑制し、薄膜半導体素子の
信頼性を高める作用を有する。この結果、初期特性に優
れ、信頼性の高い薄膜半導体素子を実現することができ
る。
In the above-mentioned manufacturing method, if the first gate insulating film is formed by plasma CVD using tetraethoxysilane as a source gas, the control range of the film stress is wide, and the first gate insulating film can be formed at a low pressure of 300 MPa or less. It is easy to adjust to the stress, and deterioration of the subthreshold characteristic of the thin film semiconductor element is effectively prevented. In addition, forming the second gate insulating film by sputtering using krypton and nitrogen as a discharge gas means that krypton has a larger atomic radius than argon which is usually used as a discharge gas, and is implanted into the film at the time of film formation. It has the characteristic that it is less likely to occur, leaving only nitrogen in the second insulating film, and preventing krypton from being implanted into the second insulating film and the first insulating film and causing defects in the insulating film. It has the effect of preventing the reaction between water contained in the gate insulating film and tungsten in the gate electrode film more effectively, and improves the reliability of the thin film semiconductor element. As a result, a thin film semiconductor device having excellent initial characteristics and high reliability can be realized.

【0014】[0014]

【発明の実施の形態】次に、本発明の具体例を説明す
る。
Next, a specific example of the present invention will be described.

【0015】(実施の形態)本発明の実施の形態につい
て、図1を用いて本発明の薄膜半導体素子の構成を説明
する。
(Embodiment) The structure of a thin film semiconductor device according to the present invention will be described with reference to FIG.

【0016】透明絶縁性基板1は、本実施の形態ではコ
ーニング社の1737ガラス基板を用いた。多結晶シリ
コン半導体膜2は、本実施の形態ではアモルファスシリ
コン(a−Si)をエキシマレーザーにより多結晶化し
た膜を用いた。
In this embodiment, a 1737 glass substrate manufactured by Corning Incorporated was used as the transparent insulating substrate 1. In this embodiment, a film obtained by polycrystallizing amorphous silicon (a-Si) using an excimer laser is used as the polycrystalline silicon semiconductor film 2.

【0017】第1のゲート絶縁膜3は、本実施の形態で
は膜応力を300MPa以下に制御するために、放電パ
ワーを400W、テトラエトキシシラン流量を200S
CCM、酸素流量を3000SCCM、基板温度を30
0℃とした。前記において"SCCM"は、"standard cc
/min"のことであり、大気圧(1.013hPa)で室温における
流量の単位である。
In the present embodiment, the first gate insulating film 3 has a discharge power of 400 W and a tetraethoxysilane flow rate of 200 S in order to control the film stress to 300 MPa or less.
CCM, oxygen flow rate 3000 SCCM, substrate temperature 30
0 ° C. In the above, "SCCM" means "standard cc"
/ min ", which is a unit of flow rate at atmospheric pressure (1.013 hPa) and room temperature.

【0018】第2のゲート絶縁膜4は、本実施の形態で
はクリプトンに窒素を混合して(クリプトン:窒素=1
00:1〜5)放電ガスとし、ターゲットには酸化シリ
コンを用いて成膜した。ここで、図2に示すように、第
2のゲート絶縁膜中に含まれる窒素濃度はゲート電極膜
に含まれる酸素濃度よりも高いことが望ましく。本実施
の形態では、第2のゲート絶縁膜に含まれる窒素濃度
は、200ppm程度になるようした。図2において、
黒丸の線は、高温高圧印可試験(B−T試験)結果を示
している。また、図2の縦軸の「BTシフト量」とは、
B−T試験におけるトランジスタ特性シフト量を示して
いる。
In the present embodiment, the second gate insulating film 4 is formed by mixing krypton with nitrogen (krypton: nitrogen = 1).
00: 1 to 5) As a discharge gas, a film was formed using silicon oxide as a target. Here, as shown in FIG. 2, the concentration of nitrogen contained in the second gate insulating film is preferably higher than the concentration of oxygen contained in the gate electrode film. In this embodiment mode, the concentration of nitrogen contained in the second gate insulating film is set to be about 200 ppm. In FIG.
The black circles indicate the results of the high-temperature and high-pressure application test (BT test). Further, the “BT shift amount” on the vertical axis in FIG.
4 shows a transistor characteristic shift amount in a BT test.

【0019】ゲート電極膜5は、本実施の形態では約3
00nmのモリブデンとタングステンの合金膜を放電ガ
スにアルゴンを用いてスパッタにより成膜した。層間絶
縁膜7は、本実施の形態ではテトラエトキシシランと酸
素の混合ガスを用いてプラズマCVDにより、400n
mのSiO2膜を作製した。ゲート配線膜6はTiとA
lの二層構成膜をスパッタリングにより厚み100n
m、ソース電極8及びドレイン電極9はTiとAlの二
層構成膜をスパッタリングによりそれぞれ厚み600n
mに形成した。
The gate electrode film 5 has a thickness of about 3 in this embodiment.
A 00 nm molybdenum-tungsten alloy film was formed by sputtering using argon as a discharge gas. In this embodiment, the interlayer insulating film 7 has a thickness of 400 nm by plasma CVD using a mixed gas of tetraethoxysilane and oxygen.
m of SiO 2 films were produced. The gate wiring film 6 is made of Ti and A
100 nm thick by sputtering
m, the source electrode 8 and the drain electrode 9 are each formed by sputtering a two-layer film of Ti and Al to a thickness of 600 n.
m.

【0020】下地膜10は、本実施の形態ではテトラエ
トキシシラン(TEOS)とO2混合ガスを用いてプラ
ズマCVDにより、厚み400nmのSiO2膜を作製
した。
In this embodiment, a 400 nm thick SiO 2 film is formed by plasma CVD using a mixed gas of tetraethoxysilane (TEOS) and O 2 in this embodiment.

【0021】なお、薄膜半導体素子としては、さらに多
結晶シリコン膜にn+ドーピング層やp+ドーピング層、
表面にSiNx膜よりなる保護膜などを形成するが、図
には示していない。
As a thin film semiconductor device, an n + doping layer, a p + doping layer,
Although a protective film made of a SiNx film is formed on the surface, it is not shown in the figure.

【0022】このように、第1のゲート絶縁膜を300
MPa以下の低応力酸化シリコン膜とし、第2のゲート
絶縁膜をゲート電極膜に含まれる酸素濃度よりも高い窒
素濃度のシリコン酸窒化膜にすることにより、多結晶シ
リコン半導体膜と第1のゲート絶縁膜との界面応力に起
因する薄膜半導体素子のサブスレッショルド特性劣化を
防止し、また、第2のゲート絶縁膜とゲート電極膜との
界面におけるタングステン(W)の酸化反応に起因した
半導体薄膜素子の信頼性低下防止するという効果が得ら
れ、特性に優れ、かつ信頼性の高い薄膜半導体素子を実
現することができる。
As described above, the first gate insulating film is
The low-stress silicon oxide film of not more than MPa, and the second gate insulating film is a silicon oxynitride film having a nitrogen concentration higher than the oxygen concentration contained in the gate electrode film, whereby the polycrystalline silicon semiconductor film and the first gate are formed. Deterioration of subthreshold characteristics of a thin film semiconductor device due to interface stress with an insulating film is prevented, and semiconductor thin film device caused by an oxidation reaction of tungsten (W) at an interface between a second gate insulating film and a gate electrode film The effect of preventing a decrease in the reliability of the semiconductor device is obtained, and a thin film semiconductor device having excellent characteristics and high reliability can be realized.

【0023】[0023]

【発明の効果】以上のように本発明によれば、シリコン
半導体膜と第1のゲート絶縁膜との界面応力に起因する
薄膜半導体素子のサブスレッショルド特性劣化を防止
し、また、第2のゲート絶縁膜とゲート電極膜との界面
におけるタングステン(W)の酸化反応に起因した半導
体薄膜素子の信頼性低下防止するという二つの効果が得
られ、全体としての特性に優れ、かつ信頼性の高い薄膜
半導体素子を実現することができる。
As described above, according to the present invention, it is possible to prevent the sub-threshold characteristic of the thin film semiconductor element from deteriorating due to the interface stress between the silicon semiconductor film and the first gate insulating film, The two effects of preventing a decrease in the reliability of the semiconductor thin film element caused by the oxidation reaction of tungsten (W) at the interface between the insulating film and the gate electrode film are obtained, and the thin film has excellent overall characteristics and high reliability. A semiconductor element can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による一実施の形態の構造を示す断面図FIG. 1 is a cross-sectional view showing a structure according to an embodiment of the present invention.

【図2】本発明による一実施の形態の第2のゲート絶縁
膜中の窒素濃度とBTシフト量の関係を示す図
FIG. 2 is a diagram showing a relationship between a nitrogen concentration in a second gate insulating film and a BT shift amount in one embodiment according to the present invention;

【図3】従来の薄膜半導体素子の構造を示す断面図FIG. 3 is a sectional view showing the structure of a conventional thin film semiconductor device.

【符号の説明】[Explanation of symbols]

1 基板 2 シリコン半導体膜 3 第1のゲート絶縁膜 4 第2のゲート絶縁膜 5 ゲート電極膜 6 ゲート配線膜 7 層間絶縁膜 8 ソース電極 9 ドレイン電極 10 下地膜 Reference Signs List 1 substrate 2 silicon semiconductor film 3 first gate insulating film 4 second gate insulating film 5 gate electrode film 6 gate wiring film 7 interlayer insulating film 8 source electrode 9 drain electrode 10 base film

フロントページの続き Fターム(参考) 4M104 AA09 BB16 CC05 DD37 EE03 EE14 GG20 HH20 5F058 BD01 BD04 BD15 BF07 BF14 BF15 BF27 BJ01 5F110 AA14 BB01 CC02 DD02 DD13 EE06 EE38 EE44 FF02 FF04 FF05 FF09 FF28 FF30 GG02 GG13 HL03 HL04 HL11 HL23 NN03 NN04 NN23 NN24 NN35 PP03 Continued on the front page F-term (reference) 4M104 AA09 BB16 CC05 DD37 EE03 EE14 GG20 HH20 5F058 BD01 BD04 BD15 BF07 BF14 BF15 BF27 BJ01 5F110 AA14 BB01 CC02 DD02 DD13 EE06 EE38 EE44 FF02 FF04 FF28 NN NN23 NN24 NN35 PP03

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 透明絶縁性基板の表面にシリコン半導体
膜と、その表面のゲート絶縁膜と、その表面のゲート電
極膜と、その表面のゲート配線膜と、前記ゲート電極膜
を覆う層間絶縁膜と、前記シリコン半導体膜から表面に
導通するソース及びドレイン電極膜を具備した薄膜半導
体素子において、 前記ゲート絶縁膜が、第1のゲート絶縁膜と第2のゲー
ト絶縁膜がこの順番に形成され、前記第1のゲート絶縁
膜が膜応力の絶対値300MPa以下であるシリコン酸
化膜であり、前記第2のゲート絶縁膜がシリコン酸窒化
膜であり、 前記ゲート電極膜がモリブデンとタングステンの合金で
あることを特徴とする薄膜半導体素子。
1. A silicon semiconductor film on a surface of a transparent insulating substrate, a gate insulating film on the surface, a gate electrode film on the surface, a gate wiring film on the surface, and an interlayer insulating film covering the gate electrode film And a thin-film semiconductor device comprising a source and drain electrode film conducting from the silicon semiconductor film to the surface, wherein the gate insulating film is formed with a first gate insulating film and a second gate insulating film in this order, The first gate insulating film is a silicon oxide film having an absolute value of a film stress of 300 MPa or less, the second gate insulating film is a silicon oxynitride film, and the gate electrode film is an alloy of molybdenum and tungsten. A thin film semiconductor device characterized by the above-mentioned.
【請求項2】 前記ゲート電極膜中に含まれる酸素濃度
よりも、前記第2のゲート絶縁膜中に含まれる窒素の濃
度が高い請求項1に記載の薄膜半導体素子。
2. The thin film semiconductor device according to claim 1, wherein the concentration of nitrogen contained in said second gate insulating film is higher than the concentration of oxygen contained in said gate electrode film.
【請求項3】 前記第1のゲート絶縁膜はテトラエトキ
シシランを原料ガスとしてプラズマCVDで成膜され、
前記第2のゲート絶縁膜はクリプトンと窒素を放電ガス
に用いてスパッタ成膜されている請求項1または2に記
載の薄膜半導体素子。
3. The first gate insulating film is formed by plasma CVD using tetraethoxysilane as a source gas,
3. The thin-film semiconductor device according to claim 1, wherein the second gate insulating film is formed by sputtering using krypton and nitrogen as a discharge gas.
【請求項4】 透明絶縁性基板の表面にシリコン半導体
膜と、その表面のゲート絶縁膜と、その表面のゲート電
極膜と、その表面のゲート配線膜と、前記ゲート電極膜
を覆う層間絶縁膜と、前記シリコン半導体膜から表面に
導通するソース及びドレイン電極膜を具備した薄膜半導
体素子の製造方法において、 前記ゲート絶縁膜として、第1のゲート絶縁膜と第2の
ゲート絶縁膜とをこの順番に形成し、前記第1のゲート
絶縁膜はテトラエトキシシランを原料ガスとしてプラズ
マCVDで成膜し、前記第2のゲート絶縁膜はクリプト
ンと窒素を放電ガスに用いてスパッタ成膜し、 前記ゲート電極膜は、モリブデンとタングステンの合金
膜を放電ガスにアルゴンを用いてスパッタにより成膜す
ることを特徴とする薄膜半導体素子の製造方法。
4. A silicon semiconductor film on a surface of a transparent insulating substrate, a gate insulating film on the surface, a gate electrode film on the surface, a gate wiring film on the surface, and an interlayer insulating film covering the gate electrode film And a method of manufacturing a thin-film semiconductor device having a source and drain electrode film conducting from the silicon semiconductor film to the surface, wherein a first gate insulating film and a second gate insulating film are arranged in this order as the gate insulating film. The first gate insulating film is formed by plasma CVD using tetraethoxysilane as a source gas, and the second gate insulating film is formed by sputtering using krypton and nitrogen as a discharge gas. The method for manufacturing a thin film semiconductor device, wherein the electrode film is formed by sputtering an alloy film of molybdenum and tungsten using argon as a discharge gas.
JP2001156015A 2001-05-24 2001-05-24 Thin film semiconductor element and manufacturing method therefor Pending JP2002353458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2002353458A true JP2002353458A (en) 2002-12-06

Family

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Family Applications (1)

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Country Status (1)

Country Link
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6929991B2 (en) * 1998-12-15 2005-08-16 Kabushiki Kaisha Toshiba Reliable semiconductor device and method of manufacturing the same
KR100635567B1 (en) * 2004-06-29 2006-10-17 삼성에스디아이 주식회사 Thin film transistor and method fabricating thereof
KR100723807B1 (en) 2004-09-30 2007-05-31 가부시키가이샤 트리케미컬 겐큐쇼 Film forming material, film forming method and device
US7312140B2 (en) 2004-09-30 2007-12-25 Tri Chemical Laboratories Inc. Film forming method
JP2012169545A (en) * 2011-02-16 2012-09-06 Fujitsu Ltd Semiconductor device, power supply device, amplifier and semiconductor manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6929991B2 (en) * 1998-12-15 2005-08-16 Kabushiki Kaisha Toshiba Reliable semiconductor device and method of manufacturing the same
KR100635567B1 (en) * 2004-06-29 2006-10-17 삼성에스디아이 주식회사 Thin film transistor and method fabricating thereof
KR100723807B1 (en) 2004-09-30 2007-05-31 가부시키가이샤 트리케미컬 겐큐쇼 Film forming material, film forming method and device
US7312140B2 (en) 2004-09-30 2007-12-25 Tri Chemical Laboratories Inc. Film forming method
JP2012169545A (en) * 2011-02-16 2012-09-06 Fujitsu Ltd Semiconductor device, power supply device, amplifier and semiconductor manufacturing method

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