JP2003124386A - Multi-cavity molded wiring board, wiring board, package for housing multi-cavity molded semiconductor device and package for housing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable product improved in the transmission characteristics of high frequency signals by preventing a high frequency signal from being detoured to a conduction pattern by removing residue at the end of the conduction pattern on a signal line still as connected. SOLUTION: This package is provided with a plurality of wiring patterns 2 formed across a divided groove 6 between adjacent wiring board areas and a conduction pattern 5 formed over the divided groove 6 between the adjacent wiring patterns 2 and connected to only one wiring board area with respect to one wiring pattern 2, and the conduction pattern 5 is almost orthogonal to the divided groove 6 and curved between the wiring pattern 2 and the divided groove 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-cavity wiring board for dividing and manufacturing a large number of wiring boards from one board, a wiring board manufactured from the multi-cavity wiring board, and a multi-cavity wiring board. The present invention relates to a multi-cavity semiconductor element storage package using a wiring board and a semiconductor element storage package using a wiring board.

[0002]

2. Description of the Related Art FIG. 6 shows an exploded perspective view of a leadless chip carrier package (LCC package), which is a conventional semiconductor device housing package for housing semiconductor devices that operate with high frequency signals. As shown in the figure, this LC
The C package generally comprises a base 11 on which a plurality of ceramic substrates such as alumina (Al ₂ O ₃ ) ceramics and aluminum nitride (AlN) ceramics having a mounting portion 11d on which the semiconductor element 14 is mounted are laminated.

The first ceramic substrate 11a of the base 11,
A groove is provided on the side surface of the second ceramic substrate 11b, and a conductive portion made of an electrolytic plating layer or the like is provided on the inner surface of the groove. Then, an external mounting substrate (not shown) and the wiring pattern 12 formed inside the semiconductor element housing package and formed with the signal (S) line and the ground (G) line are connected to electrode pads (external connection terminals). By 11e,
It is electrically connected. The electrode pad 11e is composed of a conductive portion formed on the inner surface of the groove.

The third ceramic substrate 11c of the base 11 is also used.
In order to increase the bonding area of the lid 13 to the base body 11 and to strengthen the bonding of the lid 13 to the base body 11, the side surfaces of the grooves of the first ceramic substrate 11a and the second ceramic substrate 11b are formed. Is not formed, this third ceramic substrate 11
e has a function as a so-called seal ring.

Since such a package for housing a semiconductor element is very small, a dividing groove (slit) 16 is provided in one ceramic green sheet which is a mother substrate, and a plurality of layers are laminated and sintered to obtain a ceramic. It is preferable to manufacture by so-called multi-cavity production in which individual products (LCC packages) are obtained by performing electrolytic plating later and then dividing by the dividing groove 16. Manufacturing by this multi-cavity production is much easier than stacking and sintering individual ceramic green sheets that have been divided, and the cost can be kept low.

Therefore, the base 11 is the first ceramic substrate 11 shown in the partially enlarged plan views of FIGS.
a, second ceramic substrate 11b, third ceramic substrate
Ceramic green sheets for 11c are laminated, sintered into ceramics, electrolytically plated, and then divided by the dividing grooves 16 to produce a base 11 for a package for housing a semiconductor element.

On the ceramic green sheet to be the first ceramic substrate 11a, as shown in the plan view of FIG.
The mounting portion 11d of the semiconductor element 14 is provided and the through hole is formed.
11e 'is provided, and a dividing groove 16 is provided so as to cross the substantially central portion of the through hole 11e'.

As shown in the partially enlarged plan view of FIG. 8 and the partially enlarged plan view of FIG. 10, the ceramic green sheet serving as the second ceramic substrate 11b has a dividing groove 16 and a through hole (opening) at the center. ) 11b 'is formed,
A substantially central portion is formed so as to straddle the dividing groove 16, and a through hole 11e ′ which constitutes an electrode pad 11e when divided into individual wiring boards is provided. Further, the wiring pattern is formed so as to be connected to both sides of the dividing groove 16 of the through hole 11e '.
12 are formed. Further, in order to perform electrolytic plating on the inner peripheral surface of these through holes 11e 'and the wiring pattern 12, the through holes 11e' are formed.
Conduction pattern in a zigzag shape so as to cross the dividing groove 16 between e '
15 are formed.

Further, as shown in a partially enlarged plan view of FIG. 9, the ceramic green sheet to be the third ceramic substrate 11c is provided with a size slightly larger than the through hole 11b 'in the central portion of FIG. 8 and FIG. The through hole 11c 'is formed together with the dividing groove 16.

The through-hole of the first ceramic substrate 11a
The electroplating on the inner peripheral surface of 11e 'is performed by bringing the respective through holes 11e' into contact with each other when the first ceramic substrate 11a and the second ceramic substrate 11b are stacked, and thus they are electrically connected.

Thus, the conductive pattern for electrolytic plating
15 can electrically connect all the through holes 11e ′ and the wiring pattern 12 during electrolytic plating, and further, when divided into individual products (semiconductor element housing packages) by the dividing grooves 16. Since the conductive pattern 15 is cut at the division surface, each wiring pattern is not electrically short-circuited.

In such a substrate 11, the semiconductor element 14 is bonded to the mounting portion 11d with a low melting point brazing material such as gold (Au) -germanium (Ge) or a resin adhesive, and the semiconductor is formed on the wiring pattern 12. The electrodes of the element 14 are electrically connected via bonding wires (not shown). Further, on the upper surface of the base 11, a metal material such as an iron (Fe) -nickel (Ni) -cobalt (Co) alloy or an iron (Fe) -nickel (Ni) alloy, or a ceramic such as alumina ceramics or aluminum nitride ceramics is used. The lid body 13 is joined by welding such as seam welding or bonding with a low melting point brazing material such as gold (Au) -tin (Sn) solder. In this way, a semiconductor device as a product in which the semiconductor element 14 is housed is obtained.

Such a semiconductor device has its electrode pad
Tin (Sn) -Lead (Pb) on the external mounting board via 11e
It is electrically connected by a low melting point solder such as solder, and operates the semiconductor element 14 by exchanging a high frequency signal with the mounting substrate.

[0014]

However, in the above-mentioned conventional package for accommodating semiconductor elements, for example, 10G
After the semiconductor element 14 that operates in the case of a high frequency signal of Hz or more is housed inside the semiconductor element housing package to form a semiconductor device, the semiconductor element 14 is connected to an external mounting board.
Through the through-hole 11 when divided by the dividing groove 16
The high frequency signal is transmitted not only to the signal line of the wiring pattern 12 but also to the cut edge of the conductive pattern 15 by the cut edge of the conductive pattern 15 remaining in the peripheral portion of e ′. Therefore, there is a problem that the transmission loss of the high frequency signal becomes large and the high frequency signal cannot be transmitted smoothly.

The present invention has been devised in view of the above problems, and an object thereof is to make the transmission characteristic of a high frequency signal transmitted through a signal line of a wiring pattern smooth so that the high frequency signal of a semiconductor device can be used. It is to improve the operability.

[0016]

A multi-cavity wiring board according to the present invention has a large number of wiring board regions, which are substantially quadrangular and divided by dividing grooves, are formed vertically and horizontally on a main surface of a mother board made of ceramics. In the individual wiring board, a plurality of wiring patterns formed across the dividing line between adjacent wiring board regions and one wiring formed between the adjacent wiring patterns over the dividing line. A conductive pattern connected to only one of the wiring board regions with respect to the pattern, the conductive pattern being substantially orthogonal to the dividing groove, and between the wiring pattern and the dividing groove. It is characterized by being curved.

According to the multi-cavity wiring board of the present invention having the above structure, when the wiring board is manufactured by dividing the wiring board along the dividing grooves, the conductive patterns are connected to, for example, every other wiring pattern. By remaining in the peripheral portion of the wiring board, the conductive pattern can be curved, for example, in an arc shape to prevent disconnection due to fading of the pattern, and by making it substantially orthogonal to the dividing groove. ,
Even when the dividing groove is displaced, the exposed area of the conductive pattern that is exposed can be reduced, and the transmission loss of the high frequency signal propagating through the signal wiring pattern can be reduced.

Further, the wiring board of the present invention has n (n is an integer of 2 or more) wiring patterns formed between the peripheral portion and the central portion on the main surface of a ceramic substrate having a substantially rectangular outer shape.
1 to m of the wiring pattern (however, m = n / 2 when n is an even number and m = (n tenths) / 2 when n is an odd number) are provided in the middle of the wiring pattern. From both sides to a conductive pattern added so as to branch toward the peripheral portion, the conductive pattern being substantially orthogonal to the outer edge of the ceramic substrate, and the wiring pattern and the outer edge. It is characterized by being curved between.

The wiring board of the present invention has the above structure.
In the adjacent wiring pattern after dividing the multi-cavity wiring board by the dividing groove, by curving the conductive pattern into, for example, an arc shape, it is possible to prevent disconnection due to fading of the pattern, etc. By making them substantially orthogonal to the outer side, it is possible to reduce the exposed area of the conductive pattern that is exposed even when the outer side is displaced. Therefore, by forming the conductive pattern for electrolytic plating as in the present invention, it is possible to provide a highly reliable product having excellent high-frequency signal transmission characteristics.

Further, the multi-cavity semiconductor device housing package of the present invention is a multi-cavity semiconductor package in which a plurality of mounting substrate regions separated by dividing grooves are formed, each having a mounting portion for mounting a semiconductor device thereon. In a multi-cavity semiconductor device housing package including a wiring board and a plurality of lids for sealing the semiconductor elements, the multi-cavity wiring board is the multi-cavity wiring board of the present invention. It is a feature.

According to the package for accommodating a multi-cavity semiconductor device of the present invention, after the multi-cavity wiring board is divided by the dividing groove in the above-described structure, the conductive patterns in adjacent wiring patterns on the wiring board are, for example, circular. By curving in an arc shape or the like, it is possible to prevent disconnection due to fading of the pattern, and by making them substantially orthogonal to the dividing groove, the exposed area of the conductive pattern that is exposed even when the dividing groove is displaced can be made small. can do. As a result, it is possible to provide a package for accommodating a semiconductor element in which the operability of the semiconductor element by a high frequency signal is very good.

The semiconductor element storage package of the present invention is provided with a mounting substrate having a mounting portion for mounting a semiconductor element on its upper surface, and a lid for sealing the semiconductor element. In the package, the mounting board is the wiring board of the present invention.

The package for housing a semiconductor device of the present invention is
With the above configuration, in the adjacent wiring pattern of the wiring board after dividing the multi-cavity wiring board by the dividing groove,
By curving the conductive pattern into, for example, an arc shape, it is possible to prevent disconnection due to fading of the pattern,
Further, by making the ceramic substrate substantially orthogonal to the outer edge, the exposed area of the conductive pattern that is exposed even when the outer edge is displaced can be reduced, and the high-frequency signal transmission characteristics are excellent and the reliability is high. A package for housing a semiconductor element can be provided.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor element housing package of the present invention will be described in detail below. FIG. 1 is an exploded perspective view showing an example of an embodiment of a semiconductor element housing package of the present invention, FIGS. 2 to 4 are partially enlarged plan views showing respective ceramic green sheets before lamination, and FIG. 5 is a conductive pattern formation. It is a partial enlarged plan view showing an example. In these figures,
Reference numeral 1 is a base, 3 is a lid, and 4 is a semiconductor element. The base 1 and the lid 3 constitute a container for housing the semiconductor element 4 therein.

The base 1 has a concave portion on its upper surface, and on the outer side surface thereof, a groove serving as an electrode pad 1e is formed by electrolytically plating the inner peripheral surface, and is made of various ceramics such as alumina ceramics and aluminum nitride ceramics. Become. In addition, the semiconductor element 4 is formed on the bottom surface of the recess of the substrate 1.
Has a mounting portion 1d for mounting and fixing. Such a base 1 functions as a mounting and fixing member for the semiconductor element 4, and the material of the ceramics for the base 1 is appropriately selected according to the electrical characteristics of the semiconductor element 4.

If the base 1 is made of alumina ceramics, for example, it is manufactured as follows. First, an organic binder, a solvent and the like are added and mixed to raw material powders such as aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), magnesium oxide (MgO) and calcium oxide (CaO) to prepare a paste. By applying the paste to a doctor blade method, a calendar roll method, or the like, one or a plurality of ceramic pastes to be the first ceramic substrate 1a, the second ceramic substrate 1b, and the third ceramic substrate 1c are formed. Sheet. A through hole 1e ′, which is a concave portion for accommodating the semiconductor element 4 provided in the central portion of each wiring board region, is formed in these ceramic green sheets as necessary.
After punching to form b ′ and 1c ′, molybdenum (Mo) -manganese (Mn) and tungsten (Mn) and tungsten ( A metal paste such as W) is applied by printing. Then, after laminating these and sintering them at a temperature of about 1600 ° C. to make ceramics, the first, second, and third ceramic substrates 1a, 1b, 1c are formed so that they are vertically overlapped with each other. By being divided by the groove, it is manufactured as an individual semiconductor element housing package.

The through holes 1e 'may not be formed in each ceramic green sheet. In that case, when the semiconductor green sheet is formed into a package for storing a semiconductor element, the first, second, and third layers are stacked. The electrode pads 1e made of a metallized wiring layer or the like connected to the wiring pattern 2 may be formed on the side surfaces of the ceramic substrates 1a, 1b, 1c.

As shown in the partially enlarged plan view of FIG. 2, the dividing groove 6 is formed on one main surface of the first ceramic green sheet which becomes the first ceramic substrate 1a of the base body 1.
Substantially quadrangular substrate regions such as rectangles separated by are vertically and horizontally arranged. The mounting portion 1d of the semiconductor element 4 is provided in this substrate region. Further, a through hole 1e ′ is provided on the line of the dividing groove 6. That is, the dividing groove 6 is provided so as to cross the substantially central portion of the through hole 1e '. The through-holes 1e 'are formed at similar positions on the dividing groove 6 between the respective substrate regions so as to form a large number of substrates having the same structure.

As shown in the partially enlarged plan view of FIG. 3 and the partially enlarged plan view of FIG. 5, the first ceramic green sheet serving as the second ceramic substrate 1b of the base 1 is provided with the first Dividing groove 6 on the ceramic green sheet
A wiring board region having a quadrangular outer shape and a frame shape is formed vertically and horizontally in an array in which a through hole 1b ′ for surrounding the semiconductor element 4 is formed in the center, which is divided by a dividing groove 6 corresponding to. In each wiring board region, a through hole 1e 'corresponding to the through hole 1e' of the first ceramic green sheet is formed on the dividing groove 6. That is, the dividing groove 6 is provided on the second ceramic green sheet so as to extend across the substantially central portion of the through hole 1e ′ of the second ceramic green sheet.

When forming the wiring pattern 2 extending from the through hole 1e 'of the second ceramic green sheet to the through hole 1b' side, the wiring pattern 2 for the signal [signal (S)] and the ground are formed in each wiring board region. The wiring patterns 2 for [ground (G)] are formed so as to be alternately arranged, for example. In this case, if there is no through hole 1e ', the wiring pattern 2 is formed across the dividing groove 6 between the wiring board regions adjacent to each other.

Further, between adjacent wiring board regions, a signal wiring pattern 2 and a ground wiring pattern 2 are provided on both sides of the dividing groove 6 with respect to the through hole 1e '. That is,
The wiring pattern 2 for signals is formed on one side and the wiring pattern 2 for grounding is formed on the other side of one through hole 1e '.

Further, in order to apply electrolytic plating to the inner peripheral surface of the through hole 1e 'and the wiring pattern 2, the through groove 1e' is crossed over the division groove 6 and is substantially orthogonal to the division groove 6, In addition, the conductive pattern 5 is formed between the wiring pattern 2 and the dividing groove 6 in a curved shape such as an arc shape.
In this case, if there is no through hole 1e ', the conduction pattern 5
Is formed so as to be close to the dividing groove 6 so as to be aligned with or along the direction thereof, and is formed between the adjacent wiring patterns 2 beyond the dividing groove 6 and is divided in one wiring pattern 2. Only one side of the groove 6 is connected to the wiring pattern 2 in the wiring board region.

In the present invention, this conductive pattern 5
Is substantially orthogonal to the dividing groove 6 and curved between the wiring pattern 2 and the dividing groove 6.

Since the conductive pattern 5 is substantially orthogonal to the dividing groove 6, the area of the exposed surface of the conductive pattern 5 when the mother substrate is divided along the dividing groove 6 can be minimized, It is possible to minimize the loss of the transmission signal when the frequency becomes high.

Further, by curving the conductive pattern 5 between the wiring pattern 2 and the dividing groove 6, there is no corner which bends at a substantially right angle in the middle of the conductive pattern 5, and a metal paste is used to eliminate scrapes and blurring. It can be printed easily and reliably. At the same time, even if the position of the dividing groove 6 is slightly displaced, the side surface of the conductive pattern 5 is not largely hollowed and exposed, and the signal transmission loss when a high frequency signal is transmitted to the wiring pattern 2 can be suppressed. .

Wiring pattern 2 adjacent to conductive pattern 5
As shown in FIGS. 3 and 5, the number of times of crossing the dividing groove 6 may be once, but in the case of multiple times, if the number is an odd number of three or more, the conductive patterns 5 are adjacent wiring patterns. In 2, the area moves to the wiring board region on the opposite side of the dividing groove 6. Further, if the number of times the conductive pattern 5 crosses the dividing groove 6 between the adjacent wiring patterns 2 is an even number,
The conductive pattern 5 does not move to the wiring board region on the opposite side of the dividing groove 6 in the adjacent wiring pattern 2.
In this way, by adjusting the number of times the groove 6 is crossed,
The number of connection points of the conductive pattern 5 connected to the wiring pattern 2 can be adjusted in one wiring board region. Further, if the number of times the conductive pattern 5 crosses the dividing groove 6 between the adjacent wiring patterns 2 is 1, the conductive patterns 5 are alternately connected to the wiring patterns 2 in one wiring board region.

Further, the conductive pattern 5 is connected to the through hole 1e 'so that, for example, the signal pattern and the ground pattern are alternately arranged in order to improve the impedance characteristic. It should be noted that the ground line does not impair the high-frequency transmission characteristic even if the cut end of the conduction line 5 remains in the peripheral portion of the through hole 1e '.

The signal line is the wiring pattern 2
And a conductor of the through hole 1e ′ connected thereto, which is a transmission line of a high frequency signal, and the ground line is a ground potential of the wiring pattern 2 and the conductor of the through hole 1e ′ connected thereto. It is a conductive path.

The structure of the wiring pattern 2 itself is as follows.
Although there is no particular distinction between the signal line and the ground line, it is possible to improve the impedance characteristics by forming the ground lines on the left and right sides of the signal line.

Further, each of the divided second ceramic substrates 1b as the wiring substrate has the following structure. That is, n (n is an integer of 2 or more) wirings formed between the peripheral portion and the central portion (through hole 1b ′) on the main surface of the frame-shaped second ceramic substrate 1b having a substantially square outer shape. Pattern 2 and 1 to m of wiring patterns (however, if n is an even number, m = n / 2, and if n is an odd number, m = (n + 1) / 2)
The wiring pattern 2 is provided so as to branch from the middle of the wiring pattern 2 to both sides toward the peripheral portion. In this case, the through hole 1b ′ formed in the central portion of the main surface of the wiring board is not particularly necessary when the wiring board is used alone, but the laminated wiring as shown in FIG. When used as an intermediate layer of the substrate, a through hole 1b 'is provided.

As shown in FIG. 4, the main surface of the third ceramic green sheet which becomes the third ceramic substrate 1c is divided by dividing grooves 6 corresponding to the dividing grooves 6 on the second ceramic green sheet. In addition, frame-shaped substrate regions having a quadrangular outer shape in which a through hole 1c ′ is formed in the central portion are arranged vertically and horizontally. Further, as shown in the partially enlarged plan view of FIG. 4, a through hole 1c ′ having an opening width slightly larger than that of the through hole 1b ′ of FIGS. 3 and 5 is formed. This is because, as shown in FIG. 1, the concave portion of the base body 1 is gradually narrowed downward.

The upper surface of the third ceramic substrate 1c has a lid 3 for sealing the semiconductor element 4 welded by seam welding or a low melting point solder such as gold (Au) -tin (Sn) solder. It functions as a so-called seal ring, which is a seal member that is firmly joined by adhesion with a material. Further, the width of the frame is set to an appropriate size so as to maintain the bonding strength.

The electrolytic plating on the inner peripheral surface of the through hole 1e 'of the first ceramic substrate 1a is performed by the through holes 1e' when the first ceramic substrate 1a and the second ceramic substrate 1b are laminated. Are brought into contact with each other to make them conductive.

As described above, the conductive pattern 5 has all through holes 1e 'and wiring patterns when electrolytic plating having excellent corrosion resistance such as nickel (Ni) plating and gold (Au) plating is applied after stacking and sintering. 2 is connected at the time of electricity. In addition, since the conductive pattern 5 is cut at the dividing surface when divided into individual products (semiconductor element housing packages), each wiring pattern 2 is not electrically short-circuited, and a high frequency signal is transmitted. The exposed area of the cut end of the conductive pattern 5 in the peripheral portion of the signal line can be reduced.

Thus, the package for accommodating a multi-cavity semiconductor device of the present invention is provided with through holes 1b 'and 1c' provided in the substantially central portion of the base 1 and the outer side surface of the base 1,
A groove which is formed by vertically dividing the through hole 1e ′ and becomes the electrode pad 1e for electrically connecting to the outside, and the first, second, and third ceramic green sheets are provided. The dividing groove 6 that crosses the substantially central portion of the upper end opening of the through hole 1e ′ and the dividing groove 6 of the through hole 1e ′ provided in the second ceramic green sheet are joined to both sides of the dividing groove 6 and the semiconductor element 4. The wiring pattern 2 has an electrical connection and a signal line and a ground line are alternately formed.

Further, the through hole 1e 'provided in the second ceramic green sheet is provided not on the signal line side but on the ground line side with respect to the dividing groove 6,
The wiring pattern 2 and the inner peripheral surface of the through hole 1e ′ of the first and second ceramic green sheets have a conductive pattern 5 for electrolytic plating.

The semiconductor element accommodating package of the present invention includes a base body 1 as a mounting substrate having a mounting portion 1d on which the semiconductor element 4 is mounted, and a lid 3 for sealing the semiconductor element 4. It is a configuration provided with.

In the case of FIG. 1, the semiconductor element housing package is provided with through holes 1b 'and 1c', through holes 1e ', dividing grooves 6, wiring patterns 2, and conductive patterns 5. After stacking the first to third ceramic green sheets, sintering and electrolytically plating them, the first, second and third ceramic green sheets are divided by the corresponding dividing grooves 6 so as to overlap in the vertical direction. It is produced by. As a result, a recess is formed on the upper surface of this semiconductor element housing package, and the base 1 having the mounting portion 1d for mounting the semiconductor element 4 on the bottom surface of the recess is provided.

That is, the first ceramic substrate 1a having the mounting portion 1d for mounting the semiconductor element 4 on the upper surface and the first ceramic substrate 1a are laminated on the upper surface to electrically connect the semiconductor element 4 to the outside. Frame-shaped second ceramic substrate 1 to be performed
b and a second ceramic substrate 1b, which is laminated on the upper surface of the second ceramic substrate 1b, and a frame-shaped third ceramic substrate 1c for joining the lid 3 for sealing the semiconductor element 4 to the upper surface of the semiconductor element 1. It becomes a package for storage.

Further, the package for accommodating semiconductor elements of the present invention is not limited to the one in which the concave portion is formed on the upper surface of the base body 1 as shown in FIG. It may be joined.

As a result, even if the sintered ceramic multilayer wiring substrate, which is a mother substrate for multi-piece production, is divided by the dividing groove 6, it becomes a signal line of the wiring pattern 2 in each second ceramic substrate 1b. Continuity pattern 5
However, since the wiring pattern 2 is formed so as to cross the division groove 6 between the adjacent wiring patterns 2 and be substantially orthogonal to the division groove 6, the conductive pattern 5 exposed even when the division groove 6 is displaced. The area can be reduced, the transmission loss of the high frequency signal can be minimized, and the operability of the semiconductor element 4 becomes very good.

In this way, each of the ceramic substrates 1a, 1b, 1c formed by laminating a plurality of ceramic green sheets, sintering, and electrolytically plating is divided by the dividing groove 6 to form the substrate 1
After that, the semiconductor element 4 is placed on the mounting portion 1d with gold (Au)-
A low melting point brazing material such as germanium (Ge) or a resin adhesive is placed and fixed, and the electrode of the semiconductor element 4 is electrically connected to the wiring pattern 2 through a bonding wire. After that, iron (Fe) -nickel (Ni) -on the upper surface of the substrate 1.
The lid 3 made of a metal material such as a cobalt (Co) alloy or an iron-nickel alloy, or a ceramic such as alumina ceramics or aluminum nitride ceramics is welded by seam welding or the like, or gold (Au) -tin (Sn) solder or the like. The semiconductor device is a product in which the semiconductor element 4 is housed inside by being bonded by adhesion with a low melting point brazing material.

In such a semiconductor device, tin (Sn) -lead (Pb) is attached to an external mounting substrate via the electrode pad 1e.
The semiconductor element 4 is electrically connected by low melting point solder such as solder, and operates the semiconductor element 4 by exchanging a high frequency signal with the mounting substrate.

Further, in the present invention, a multi-cavity semiconductor element accommodating package is constructed using the multi-cavity wiring board of the present invention. In that case, a multi-cavity wiring board in which a plurality of mounting board regions, each of which is a base 1 and has a mounting portion 1d on which the semiconductor element 4 is mounted and which is divided by the dividing groove 6, is formed; And a plurality of lids 3 for sealing.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

For example, the present invention can be applied to the case of an optical semiconductor element housing package for housing an optical semiconductor element such as a semiconductor laser (LD) which is a kind of light emitting element that operates with a high frequency signal. Further, in the example of the above-described embodiment, the configuration of the package for accommodating a semiconductor element having the concave portion on the upper surface and having the conductive pattern 5 of the present invention on the inner layer portion (second ceramic substrate 1b) of the substrate 1 has been described. It goes without saying that the wiring board of the present invention may be a single-plate wiring board having a wiring structure such as the conductive pattern 5 on the surface layer.

Furthermore, the signal lines and the ground lines do not necessarily have to be arranged alternately, that is, 10
When transmitting not only high frequency signals of GHz or higher but also signals in a low frequency band that does not impair the transmission characteristics,
You may use the wiring pattern 2 in which the piece of the conduction pattern 5 remains as a signal line. In the example of the above embodiment, one layer of the second ceramic green sheet is laminated, but two or more layers may be laminated.

[0058]

According to the multi-cavity wiring board of the present invention, a plurality of wiring patterns are formed across the dividing grooves between the adjacent wiring board regions, and the wiring patterns are formed between the adjacent wiring patterns over the dividing grooves. And a conductive pattern connected to one wiring pattern in only one wiring board region, the conductive pattern being substantially orthogonal to the dividing groove, and the wiring pattern and the dividing pattern. Since the wiring board region is divided by the dividing groove by being curved between the groove and the groove, it is possible to prevent disconnection due to fading of the pattern by curving the conductive pattern into, for example, an arc shape. By making the dividing grooves substantially orthogonal to each other, it is possible to reduce the exposed area of the conductive pattern that is exposed even when the dividing grooves are displaced. As a result, by forming the conductive pattern for electrolytic plating as in the present invention, it is possible to provide a highly reliable product having excellent high-frequency signal transmission characteristics.

Further, the wiring board of the present invention has n (n is an integer of 2 or more) wiring patterns formed between the peripheral portion and the central portion on the main surface of the ceramic substrate having a substantially rectangular outer shape.
1 to m of the wiring pattern (however, if n is an even number, m = n / 2, and if n is an odd number, m = (n + 1) / 2), and the wiring pattern is provided from the middle to both sides. A conductive pattern added so as to branch toward the portion, the conductive pattern being substantially orthogonal to the outer side of the ceramic substrate and curved between the wiring pattern and the outer side. By dividing the multi-cavity wiring board by the dividing groove, the adjacent wiring patterns can be prevented from being broken due to fading of the pattern by curving the conductive pattern into, for example, an arc shape. By making the dividing grooves substantially orthogonal to each other, it is possible to reduce the exposed area of the conductive pattern that is exposed even when the dividing grooves are displaced. Therefore, by forming the conductive pattern for electrolytic plating as in the present invention, it is possible to provide a highly reliable product having excellent high-frequency signal transmission characteristics.

Further, the conductive pattern added to the wiring pattern also has the effect of strengthening the ground potential when the wiring pattern is used as a ground line.

A multi-cavity semiconductor device housing package of the present invention is a multi-cavity wiring board having a plurality of mounting substrate regions separated by dividing grooves and having a mounting portion for mounting a semiconductor device on its upper surface. And a plurality of multi-cavity semiconductor element housing packages each including a plurality of lids for sealing each semiconductor element, wherein the multi-cavity wiring board is the multi-cavity wiring board of the present invention, It is possible to provide a package for accommodating a multi-cavity semiconductor device, which has the same effect as that of the multi-cavity wiring board of the invention, and therefore has a very good operability of the semiconductor device by a high frequency signal.

The package for housing a semiconductor device of the present invention is
In a semiconductor element housing package including a mounting board having a mounting portion for mounting a semiconductor element on an upper surface thereof, and a lid for sealing the semiconductor element, the mounting board is the wiring board of the present invention. As a result, it is possible to provide a package for accommodating a semiconductor element, which has the same effect as that of the wiring board of the present invention described above, and therefore has a very good operability by the high frequency signal of the semiconductor element.

[Brief description of drawings]

FIG. 1 is an exploded perspective view showing an example of an embodiment of a package for housing a semiconductor element of the present invention.

FIG. 2 is a partially enlarged plan view showing a first ceramic green sheet before being laminated, which is a first ceramic substrate in the present invention.

FIG. 3 is a partially enlarged plan view showing a second ceramic green sheet before being laminated, which is a second ceramic substrate in the present invention.

FIG. 4 is a partially enlarged plan view showing a third ceramic green sheet before being laminated, which is a third ceramic substrate in the present invention.

FIG. 5 is a partially enlarged plan view of a second ceramic green sheet before lamination showing an example of formation of a conductive pattern in the present invention.

FIG. 6 is an exploded perspective view showing a conventional semiconductor element housing package.

FIG. 7 is a partially enlarged plan view showing a ceramic green sheet which is a conventional first ceramic substrate.

FIG. 8 is a partially enlarged plan view showing a ceramic green sheet which is a conventional second ceramic substrate.

FIG. 9 is a partially enlarged plan view showing a ceramic green sheet which is a conventional third ceramic substrate.

10 is a partially enlarged plan view of the ceramic green sheet showing the conduction pattern of FIG.

[Explanation of symbols]

1: Base 1a: first ceramic substrate 1b: second ceramic substrate 1c: Third ceramic substrate 1d: Placement part 1e ': Through hole 2: Wiring pattern 3: Lid 4: Semiconductor element 5: Conduction pattern 6: Dividing groove

Claims (4)

[Claims] 1. A multi-cavity wiring board in which a plurality of wiring board areas of a substantially quadrangle separated by dividing lines are vertically and horizontally arranged on a main surface of a mother board made of ceramics, and between adjacent wiring board areas. A plurality of wiring patterns formed across the dividing line, and formed between the adjacent wiring patterns over the dividing line, and connected to one wiring pattern in only one of the wiring board regions. A multi-cavity wiring board, wherein the conductive pattern is substantially orthogonal to the dividing groove and curved between the wiring pattern and the dividing groove. . 2. An n (n is an integer of 2 or more) wiring pattern formed between a peripheral portion and a central portion on a main surface of a ceramic substrate having an outer shape of a substantially quadrangle, and one of the wiring patterns.
To m lines (where m = n / 2 when m is an even number and m = (n + 1) / 2 when n is an odd number), and the wiring pattern extends from the middle of the wiring pattern toward the peripheral portion. And a conductive pattern added so as to be branched. The conductive pattern is substantially orthogonal to the outer side of the ceramic substrate and curved between the wiring pattern and the outer side. Wiring board characterized by. 3. A multi-cavity wiring board having a mounting portion for mounting a semiconductor element on an upper surface and having a plurality of mounting substrate areas separated by dividing lines, and a plurality of sealing elements for sealing each semiconductor element. 2. A multi-cavity semiconductor device housing package comprising the multi-cavity semiconductor device housing package according to claim 1, wherein the multi-cavity semiconductor wiring substrate is the multi-cavity semiconductor wiring substrate according to claim 1. 4. A semiconductor element storage package comprising a mounting substrate having a mounting portion for mounting a semiconductor element on an upper surface thereof, and a lid body for sealing the semiconductor element, wherein the mounting substrate is a substrate. 2. A package for housing a semiconductor element, which is the wiring board according to 2.