JP2003121381A - Printed circuit board inspection device - Google Patents

Printed circuit board inspection device

Info

Publication number
JP2003121381A
JP2003121381A JP2001318510A JP2001318510A JP2003121381A JP 2003121381 A JP2003121381 A JP 2003121381A JP 2001318510 A JP2001318510 A JP 2001318510A JP 2001318510 A JP2001318510 A JP 2001318510A JP 2003121381 A JP2003121381 A JP 2003121381A
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
image
inspection
inspection device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001318510A
Other languages
Japanese (ja)
Inventor
Kenichi Kanemasa
賢一 兼政
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2001318510A priority Critical patent/JP2003121381A/en
Publication of JP2003121381A publication Critical patent/JP2003121381A/en
Pending legal-status Critical Current

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  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)

Abstract

PROBLEM TO BE SOLVED: To shorten the inspection time of an optical automatic inspection device for printed circuit board by reducing the number of processed image data. SOLUTION: The time required by the optical automatic inspection device for comparison and acceptance/rejection discrimination when the device performs image processing is shortened by reducing the data volume of a circuit pattern shape, by not comparing the image of a printed circuit board which is an object to be inspected directly with a model image in the unit of picture elements, but extracting the outline of the circuit pattern of the printed circuit board and obtaining data from an aggregate of extremely short segments of sub-pixel accuracy.

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、プリント回路板の
回路パターンの回路欠損や回路太り、異物等の欠陥の有
無を検査する検査装置に関するものである。 【0002】 【従来の技術】部品実装前のプリント回路板の検査方法
としては、実際に回路に電気を通して断線や短絡の有無
を検査する導通検査と、導通検査では検出できない回路
欠損、異物などを検査員が見て、あるいは、画像処理に
よる光学式自動検査装置で検出する光学的な検査があ
る。 【0003】画像処理による光学式自動検査装置での検
査方法としては、大きく分類して、特徴抽出法と比較検
査法の2種類がある。特徴抽出法においては、プリント
回路板の回路パターンの特徴が設計規則に合致するかど
うかを検査する。設計規則としては、回路幅が規定され
た最小回路幅より太いかどうか、回路間隔が規定された
最小回路間隔より太いかどうか、回路終端部は端子にな
っているかどうか、回路輪郭の曲率が規定された最大曲
率よりも小さいかどうか、等があげられる。一般的に、
特徴抽出法は検査装置が小規模でも処理可能で、検査時
間も短いが、比較検査法に比べて検査の信頼性が低い。 【0004】比較検査法には、検査対象であるプリント
回路板と比較するモデルとして、良品サンプルを使用し
てプリント回路板同士を比較する実パターン比較法と、
CADデータ等の設計情報をモデルする設計パターン比
較法の2種類の方法が存在する。いずれの方式において
も、検査対象のプリント回路板パターン画像とモデルを
重ね合わせ、両者を比較することで合否判定を行う。比
較検査法は画像処理等の計算量が多いため、装置規模は
大きく、また、検査時間が長くなるが、特徴抽出法に比
べて検査の信頼性は高い。 【0005】比較検査法においては、検査対象のプリン
ト回路板パターン画像とCADデータもしくは良品より生
成したモデル画像とを比較するのが一般的である。プリ
ント回路坂内で寸法による判定が必要となる部分のう
ち、最も小さい部分の寸法を最小寸法と呼ぶことにする
と、通常は最小回路幅もしくは最小回路間隔が最小寸法
となる。外観検査では回路の欠けや突起を検査する必要
があるため、パターン画像やモデル画像は、最小寸法部
分の回路外観の合否判定するのに十分な解像度を有する
必要がある。画像内の画素を寸法測定の単位とした場
合、仮に画素寸法を最小寸法の10分の1程度とする
と、最小寸法が100μmの場合、画素寸法は10μm
程度にする必要がある。 【0006】しかしながら、最小寸法が100μmで1
00mm角のプリント回路板を検査する場合、画素寸法
を10μmとすると、検査対象のパターン画像の1辺の
画素数は1万画素にもなる。このような巨大な画像は、
画像を撮影する撮像手段においても、また、撮影後の画
像を処理する画像処理手段においても、取扱いが困難で
あり、また、取扱いが可能な場合でも処理に時間を要す
るという問題があった。 【0007】 【発明が解決しようとする課題】本発明は従来のプリン
ト回路板の回路パターン自動検査方法のこのような問題
点を解決するためになされたもので、その目的は検査精
度を維持しながら検査対象のパターン画像データ量を抑
え、処理時間を短縮したプリント回路板パターン自動検
査方法を提供することにある。 【0008】 【課題を解決するための手段】本発明は、設計情報もし
くは良品画像より生成したモデルデータと、プリント回
路板製品とを比較することで製品の合否判定を行うプリ
ント回路板パターン検査装置において、プリント回路板
製品の回路パターン輪郭形状をサブピクセル精度を持つ
微小線分群に変換し、各微小線分の位置と向きをモデル
データの輪郭と比較することで製品の合否判定を行うプ
リント回路板検査装置である。 【0009】 【発明の実施の形態】次に、本発明の実施の形態につい
て説明する。図1は実パターン比較法によるプリント回
路板検査方法の模式図である。検査対象のプリント回路
板1と良品モデルとなるプリント回路板2を撮像手段3
で画像化し、画像処理手段4で比較を行い、合否判定す
る。図2は設計パターン比較法によるプリント回路板検
査方法の模式図である。検査対象のプリント回路板1を
CADデータ等から生成した設計パターン5と比較し、合
否判定する。いずれの方法においても、撮像手段3とし
ては主にCCDが用いられる。また、検査対象の画像と
モデル画像を画像処理手段4としては、専用回路による
ハードウェア処理やマイクロプロセッサによるソフトウ
ェア処理などが用いられる。 【0010】撮像手段3ではプリント回路板1の像を有
限個のある大きさをもった画素の集合に近似する。図3
は、このような画素を単位とした検査方法の問題点の説
明図である。図3の左図はプリント回路板の模式図で、
黒い部分が絶縁部分となる基板、白い部分が回路を示
す。このプリント回路板のAA’断面の明度をグラフに
表したのが図3右上の図である。撮像手段3により画像
化した場合の明度のグラフが図3右中および右下の図で
ある。プリント回路板の回路の輪郭位置と画像の画素の
格子位置が一致する場合には図3右中のように輪郭の位
置を正確に表すことができる。しかしながら、ほとんど
の場合、回路の輪郭位置と画素格子位置は一致しない。
従って、画像内の各画素があるしきい値より大きい部分
を回路部分として考えると、真の輪郭位置と、画像上の
見かけの輪郭位置が異なるという結果となる。この誤差
は空間量子化誤差と呼ばれ、撮像手段3の解像度の設定
に関しては、検査で検出すべき欠陥の大きさに比べ空間
量子化誤差を十分小さくする必要がある。これがプリン
ト回路板画像の画素数つまりデータ量の増大につなが
り、画像処理手段での処理時間の増大につながるという
問題点があった。 【0011】本発明によるプリント回路板検査装置にお
いては、検査対象のプリント回路板1の画像をそのまま
モデル画像と比較するのではなく、図4に示すようにプ
リント回路板の画像から回路の輪郭を抽出し、画素寸法
程度の微小な長さの線分の群で輪郭をデータ化した後、
各線分の位置と向きをモデルの回路輪郭と比較し、合否
判定する。各画素毎にしきい値と比較して回路部分とそ
うではない部分を分離する方法では、空間量子化エラー
として最大±0.5画素ずれが生じる可能性があるが、
ある画素とその周辺の画素の値から輪郭の位置を推定す
る輪郭抽出フィルターを用いることにより、輪郭が画素
内のどの位置を通るかを画素寸法の数分の一から数十分
の一の精度、いわゆる、サブピクセル精度で推定するこ
とが可能である。つまり、本発明によれば、従来の方法
に比べて数倍の画素寸法の画像を使用しても、同程度の
精度の検査が可能となる。従来の装置と本発明の装置で
同じ面積を検査する場合、画像の画素数は数分の一の二
乗つまり数十分の一の画素数で検査可能となる。画像の
画素数が少ないため、検査に必要な画像処理のデータ量
も少なくなる上、輪郭を表す微小線分の数は画素数より
もさらに少なくなるため、データ処理量を減らすことが
でき、検査の高速化を望むことが可能となる。 【0012】 【発明の効果】本発明の方法に従うと、プリント回路板
の検査において、検査精度を維持しつつ、画像処理のデ
ータ量を減らすことにより、検査時間を短縮した検査装
置を提供することが可能となる。
Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an inspection apparatus for inspecting a circuit pattern of a printed circuit board for defects such as circuit defects, circuit fatness, and foreign matter. 2. Description of the Related Art As a method of inspecting a printed circuit board before mounting components, there are provided a continuity test for actually checking the presence or absence of a disconnection or a short circuit by passing electricity through a circuit, and a circuit defect or foreign matter which cannot be detected by the continuity test. There are optical inspections that are inspected by an inspector or detected by an optical automatic inspection device by image processing. [0003] Inspection methods in an optical automatic inspection apparatus by image processing are roughly classified into two types, a feature extraction method and a comparative inspection method. In the feature extraction method, it is checked whether the features of the circuit pattern of the printed circuit board conform to the design rules. The design rules include whether the circuit width is larger than the specified minimum circuit width, whether the circuit interval is larger than the specified minimum circuit interval, whether the circuit end is a terminal, and the curvature of the circuit contour. Is smaller than the given maximum curvature. Typically,
The feature extraction method can process even a small-sized inspection device and has a short inspection time, but the inspection reliability is lower than the comparative inspection method. The comparative inspection method includes an actual pattern comparison method of comparing printed circuit boards using non-defective samples as a model for comparison with a printed circuit board to be inspected,
There are two types of design pattern comparison methods for modeling design information such as CAD data. In either method, a printed circuit board pattern image to be inspected is superimposed on a model, and a pass / fail judgment is made by comparing the two. The comparative inspection method requires a large amount of calculation for image processing and the like, so the apparatus scale is large and the inspection time is long, but the reliability of the inspection is higher than that of the feature extraction method. In the comparative inspection method, a pattern image of a printed circuit board to be inspected is generally compared with CAD data or a model image generated from a non-defective product. If the size of the smallest portion of the printed circuit slope that needs to be determined based on the size is referred to as the minimum size, the minimum circuit width or minimum circuit interval is usually the minimum size. In the appearance inspection, it is necessary to inspect a chip or a protrusion of a circuit. Therefore, the pattern image or the model image needs to have a resolution sufficient to determine whether or not the circuit appearance of the smallest dimension portion is acceptable. If the pixels in the image are used as the unit of the size measurement, and if the pixel size is about 1/10 of the minimum size, the pixel size is 10 μm if the minimum size is 100 μm.
Need to be about. However, when the minimum dimension is 100 μm,
In the case of inspecting a 00 mm square printed circuit board, if the pixel size is 10 μm, the number of pixels on one side of the pattern image to be inspected is as large as 10,000 pixels. Such a huge image,
There is a problem that it is difficult to handle the image capturing means for capturing an image and the image processing means for processing an image after capturing, and it takes time to process even if the handling is possible. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of a conventional method for automatically inspecting a circuit pattern of a printed circuit board, and its object is to maintain the inspection accuracy. Another object of the present invention is to provide a printed circuit board pattern automatic inspection method in which the amount of pattern image data to be inspected is reduced and the processing time is reduced. SUMMARY OF THE INVENTION The present invention provides a printed circuit board pattern inspection apparatus for comparing a model data generated from design information or a non-defective image with a printed circuit board product to determine whether the product is acceptable or not. A printed circuit board that converts the circuit pattern contour shape of a printed circuit board product into a group of minute line segments having sub-pixel accuracy, and compares the position and orientation of each minute line segment with the outline of the model data to determine the acceptability of the product. It is a board inspection device. Next, an embodiment of the present invention will be described. FIG. 1 is a schematic diagram of a printed circuit board inspection method using an actual pattern comparison method. The printed circuit board 1 to be inspected and the printed circuit board 2 serving as a non-defective model are imaged by the imaging means 3
To make an image, and the image processing means 4 makes a comparison to make a pass / fail decision. FIG. 2 is a schematic diagram of a printed circuit board inspection method using a design pattern comparison method. Printed circuit board 1 to be inspected
It is compared with a design pattern 5 generated from CAD data or the like, and a pass / fail judgment is made. In either method, a CCD is mainly used as the imaging means 3. Further, as the image processing unit 4, an image to be inspected and a model image are subjected to hardware processing by a dedicated circuit, software processing by a microprocessor, or the like. In the image pickup means 3, the image of the printed circuit board 1 is approximated to a finite set of pixels having a certain size. FIG.
FIG. 2 is an explanatory diagram of a problem of such an inspection method in units of pixels. 3 is a schematic diagram of a printed circuit board,
The black part indicates the substrate serving as the insulating part, and the white part indicates the circuit. FIG. 3 is a graph on the upper right of FIG. 3 in which the brightness of the AA ′ cross section of the printed circuit board is represented in a graph. Graphs of brightness when imaged by the imaging means 3 are the middle right and lower right figures in FIG. When the contour position of the circuit of the printed circuit board matches the grid position of the pixels of the image, the position of the contour can be accurately represented as shown in the middle right of FIG. However, in most cases, the contour position of the circuit does not match the pixel grid position.
Therefore, when a portion where each pixel in the image is larger than a certain threshold value is considered as a circuit portion, the result is that the true contour position is different from the apparent contour position on the image. This error is called a space quantization error, and it is necessary to make the space quantization error sufficiently smaller than the size of a defect to be detected in the inspection when setting the resolution of the imaging unit 3. This leads to an increase in the number of pixels of a printed circuit board image, that is, an amount of data, and an increase in processing time in the image processing means. In the printed circuit board inspection apparatus according to the present invention, instead of comparing the image of the printed circuit board 1 to be inspected with the model image as it is, as shown in FIG. After extracting and converting the contour into data with a group of line segments of minute length about the pixel size,
The position and direction of each line segment are compared with the circuit contour of the model, and pass / fail judgment is made. In the method of separating a circuit part and a part that is not so by comparing with a threshold value for each pixel, there is a possibility that a maximum of ± 0.5 pixel shift may occur as a spatial quantization error,
By using a contour extraction filter that estimates the position of the contour from the value of a certain pixel and its surrounding pixels, it is possible to determine which position in the pixel the contour passes through by a fraction to several tenths of the pixel size. , So-called sub-pixel accuracy. That is, according to the present invention, even if an image having a pixel size several times as large as that of the conventional method is used, the inspection can be performed with approximately the same accuracy. When the same area is inspected by the conventional apparatus and the apparatus of the present invention, the number of pixels of the image can be inspected with a fraction of a square, that is, a tenth of a pixel. Since the number of pixels in the image is small, the amount of image processing data required for inspection is also reduced, and the number of minute lines representing contours is even smaller than the number of pixels, so that the amount of data processing can be reduced. It is possible to hope for a higher speed. According to the method of the present invention, it is possible to provide an inspection apparatus in which the inspection time is reduced by reducing the data amount of image processing while maintaining the inspection accuracy in the inspection of a printed circuit board. Becomes possible.

【図面の簡単な説明】 【図1】 実パターン比較法によるプリント回路板検査
方法の模式図である。 【図2】 設計パターン比較法によるプリント回路板検
査方法の模式図である。 【図3】 画素を単位とした検査方法の問題点の説明図
である。 【図4】 本発明によるプリント回路板の回路輪郭表現
方法の説明図である。 【符号の説明】 1 検査対象のプリント回路板 2 良品モデルとなるプリント回路板 3 撮像手段 4 比較を行う画像処理手段 5 設計パターン 6 プリント回路板画像 7 回路の輪郭の微小線分群
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a printed circuit board inspection method using an actual pattern comparison method. FIG. 2 is a schematic diagram of a printed circuit board inspection method using a design pattern comparison method. FIG. 3 is an explanatory diagram of a problem of an inspection method in units of pixels. FIG. 4 is an explanatory diagram of a method for expressing a circuit contour of a printed circuit board according to the present invention. [Description of Signs] 1 Printed circuit board to be inspected 2 Printed circuit board 3 serving as a non-defective model 3 Imaging means 4 Image processing means 5 for comparison 5 Design pattern 6 Printed circuit board image 7 Fine line segment group of circuit outline

Claims (1)

【特許請求の範囲】 【請求項1】 設計情報もしくは良品画像より生成した
モデルデータと、プリント回路板製品とを比較すること
で製品の合否判定を行うプリント回路板パターン検査装
置において、プリント回路板製品の回路パターン輪郭形
状をサブピクセル精度を持つ微小線分群に変換し、各微
小線分の位置と向きをモデルデータの輪郭と比較するこ
とで製品の合否判定を行うプリント回路板検査装置。
Claims: 1. A printed circuit board pattern inspection apparatus for comparing a model data generated from design information or a non-defective image with a printed circuit board product to determine whether the product is acceptable or not. A printed circuit board inspection device that converts the circuit pattern contour shape of a product into a group of minute line segments having sub-pixel accuracy, and compares the position and orientation of each minute line segment with the contour of the model data to determine the acceptability of the product.
JP2001318510A 2001-10-16 2001-10-16 Printed circuit board inspection device Pending JP2003121381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001318510A JP2003121381A (en) 2001-10-16 2001-10-16 Printed circuit board inspection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001318510A JP2003121381A (en) 2001-10-16 2001-10-16 Printed circuit board inspection device

Publications (1)

Publication Number Publication Date
JP2003121381A true JP2003121381A (en) 2003-04-23

Family

ID=19136200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001318510A Pending JP2003121381A (en) 2001-10-16 2001-10-16 Printed circuit board inspection device

Country Status (1)

Country Link
JP (1) JP2003121381A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014238368A (en) * 2013-06-10 2014-12-18 株式会社ブリヂストン Tire inspection device and tire inspection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014238368A (en) * 2013-06-10 2014-12-18 株式会社ブリヂストン Tire inspection device and tire inspection device

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