JP2003117092A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken restoring time from power failure of a game machine 5. SOLUTION: This game machine 5 provides a game. Information is inputted from the game machine 5. The game machine 5 has a main base board 1 for executing processing for providing the game, a winning ball control base board 3 for controlling respective parts of the game machine 5 by receiving a command from the main base board 1, a reset signal making circuit 125 for starting operation of the game machine 5, a delay-wave reshaping part 435 for executing delay processing for delaying the timing of the main base board 1 for starting operation by the reset signal making circuit 125, and a directional charge- discharge circuit 455 for returning the delay-wave reshaping part 435 changed in a state by the delay processing to a state before executing the delay processing in a shorter time than time spent on the delay processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for controlling a main control means and a sub-control means of a gaming machine that provides a game such as a pachinko game or a pachislot game.

[0002]

2. Description of the Related Art Normally, when a game machine recovers from a power outage even when an unexpected situation such as a power outage occurs and the rental balls, prize balls (also simply called prize balls), or the payout of medals are interrupted. In addition, by paying out the rest, it is provided with a configuration that does not cause a disadvantage to the player.

In the prior art, as such a configuration, for example, the winning ball is left until the payout is actually performed, and when the power is restored, the remaining winning ball is
It was said that prize balls would be paid out. According to this conventional technique, even if the data of the prize balls to be paid out disappears due to a power failure or the like, for example, the maximum number of prizes is 15 for one remaining prize ball. By paying out individual prize balls, the player was prevented from suffering a disadvantage.

However, the above-mentioned conventional technique, that is, the technique of leaving the winning ball, has a drawback that the manufacturing cost is increased because a complicated mechanism is required to keep the winning ball. . Furthermore, even if the player wins the prize hole where the maximum prize ball is not paid out, the maximum prize ball is always paid out for the remaining prize balls, so from the player's perspective It is not a disadvantage, but there was a drawback that it was a disadvantage from the perspective of the hall. Therefore, in recent years, techniques developed in view of such circumstances have been developed.

The technique is to retain the memory of data corresponding to the number of prize balls to be paid out and the number of balls to be rented even during a power failure so that the prize balls are always accurately paid out regardless of the power failure. is there.

[0006]

By the way, recently, for the purpose of improving the fraud prevention function of a gaming machine, a board is divided for each function of the gaming machine such as a main control board and a sub-control board (so-called sub-control board). ), And the technology of unidirectionalizing the flow of data from the main control board to the sub-control board and controlling each part of the gaming machine without returning the data from the sub-control board to the main control board has become common. There is.

Therefore, it becomes impossible to input the state of the sub control board from the main control board. For example, in paying out the prize balls as described above, it is necessary to newly consider the following problems. It came out. For example, recent game machines have main control means (also referred to as a main board) that receives power supply from a power supply board, and prize balls as sub-control means that receive a command from the main control board and pay out prize balls. And a control board. The main control board and the prize ball control board start operating in a predetermined procedure when power is supplied from the power supply board. In this case, is the main control board operating faster? However, it was not specified whether the prize ball control board was activated earlier or was activated at the same time.

Therefore, if a power failure occurs during the payout of prize balls, when the power is restored, the main control board will be in a faster operating state, and the prize ball control boards that have not yet been operated will be There was a risk of sending a signal requesting the payout of prize balls. In this case, the signal sent from the main control board to the prize ball control board is wasted, that is, the prize ball control board cannot dispense the prize balls correctly.
The prize balls were not paid out, resulting in a disadvantage to the player.

Even if the operation start of the main control board is delayed more than the prize ball control board, if it is too delayed, the time (delay time) until the game can be started becomes too long and the player is frustrated. I will remember. On the contrary,
If the delay time is set too short, the above-mentioned problem of omission of prize balls will occur again.

It is an object of the present invention to solve these problems and always provide an appropriate delay time so that a player can smoothly return to a game.

[0011]

Means for Solving the Problems and Effects of the Invention As means for solving the above problems, a gaming machine according to the invention of claim 1 is a gaming machine that provides a game, and information is input from the gaming machine. Then, the main control means for performing the processing for the game machine to provide the game, the sub-control means for controlling each part of the game machine in response to a command from the main control means, and the operation of the game machine are started. The operation starting means, the operation starting means, delaying means for performing delaying processing for delaying the time when the main control means starts operation, and the delaying means whose state is changed by the delaying processing, The gist is to provide a delay circuit resetting means for returning to a state before the delay processing is performed in a shorter time than the spent time.

As a result, when the operation starting means starts the operation of the gaming machine, the main control means for performing the processing for providing the game, and the sub-controlling each part of the gaming machine in response to the command from the main control means. The control means start operation together, but the time when the main control means starts operation is delayed by the delay means. The processing in this delay (hereinafter, also referred to as delay processing) is performed by changing the state (changing the amount of stored electricity). Therefore, the delay means changes its state (for example, the amount of stored electricity) by the delay process.

In this way, the delay means which delays the start of the operation of the main control means by changing the state is returned to the state before the delay processing by the delay circuit resetting means. The time to be returned to is shorter than the time spent for delay processing.

Therefore, the delay means is reset in a shorter time than the delay processing time. This makes it possible to provide the delay processing provided at the start of operation of the gaming machine again in a short time. For example, in the case where the delay circuit resetting means is not used, it is common to require a reset time which is similar to the delay time provided by the delay circuit, and the interval until the delay processing is performed again is lengthened. There is a need.

As a result, at the time of recovery from a power failure, the most upstream main control means is activated after the terminal sub-control means is activated, so that a command is always transmitted to the activated sub-control means. , There is no need to say that the command disappears on the way. Moreover, the delay means that provides this function is quickly reset by the delay circuit reset means,
Since the state in which the delay processing can be provided again is returned, it becomes possible to operate the operation starting means again immediately after the delay processing is completed.

In other words, the operation starting means is practically almost free from the timing restriction for starting the operation of the sub control means and the main control means. In other words, the operation starting means needs to start the operation of the sub control means and the main control means with the delay means being reset. Therefore, when the delay circuit resetting means is not provided, the delaying means is slowly reset, so that it is necessary to delay the time when the operation starting means is operated.

Therefore, considering, for example, a case where an interruption of the power supply occurs in which power failure and power recovery are repeated in a short time,
The time to activate the operation start means, the delay processing time,
The time for resetting must be added to the time for resetting. Therefore, it is necessary to lengthen the time until the operation starts after the power is restored.

However, since the delay circuit resetting means resets the delaying means in a short time, it is possible to accelerate the operation start-up means by this short time, and it is possible to shorten the time after the power is restored. It becomes possible to put the gaming machine into operation. Therefore, the player can be provided with the game promptly, the player is not frustrated, and the customer satisfaction of the player can be improved, which is an extremely excellent effect.

According to another aspect of the gaming machine of the present invention, the delay means charges the capacitor with a predetermined charging characteristic,
Alternatively, the game machine according to claim 1 is characterized in that the delay process is performed according to a discharge time for discharging with a predetermined discharge characteristic. As a result, it is possible to make only a charge / discharge circuit with a relatively inexpensive resistor and capacitor, it is possible to configure with a small number of parts, and it is possible to set a delay time from an extremely short time to a long time. It has an excellent effect.

In the gaming machine according to the invention of claim 3, the delay circuit resetting means charges the capacitor with a predetermined charging characteristic when the capacitor performs delay processing by discharging. The gist is to provide the gaming machine according to claim 2. As a result, the delay time can be adjusted by the discharge resistance value and the reset time (which is a function of the charging time) can be adjusted by the charge resistance value, which can be configured with a small number of parts and from an extremely short time. This has an extremely excellent effect that the delay time up to a long time and the reset time can be set.

A gaming machine according to a fourth aspect of the present invention is characterized in that the delay circuit resetting means discharges the capacitor with a predetermined discharge characteristic when the capacitor performs delay processing by charging. The gist is to provide the gaming machine according to Item 2. This eliminates the need to supply power to reset the delay means.

Therefore, since it is possible to start the charging of the capacitor from the time when the power supply is resumed and perform the delay process, the time when the operation of the main control means is started is almost the time required for the delay process. It is possible to have the same minimum time. . A gaming machine according to a fifth aspect of the present invention is provided with the gaming machine according to the third aspect, wherein the time constant of the charging circuit of the capacitor is smaller than the time constant of the discharging circuit of the capacitor. Is the gist.

As a result, the reset time becomes shorter than the delay time, and it becomes possible to quickly execute the reset and bring the gaming machine into the operating state in a short time. The gaming machine according to the invention of claim 6 is provided with the gaming machine according to claim 4, wherein the time constant of the discharging circuit of the capacitor is smaller than the time constant of the charging circuit of the capacitor. Is the gist.

As a result, the reset time becomes shorter than the delay time, and the reset can be executed promptly to bring the gaming machine into the operating state in a short time. The game machine according to the invention of claim 7 is a power supply means for supplying power to the main control means and / or the sub control means, and a voltage drop for detecting whether or not the voltage of the power supply means has dropped for a predetermined time. And a voltage drop signal output means for outputting a voltage drop signal to the main control means and / or the sub control means when the voltage drop detection means detects a voltage drop. The gist of the present invention is to provide the gaming machine according to any one of claims 1 to 6.

Thus, the power supply means is the main control means,
Power is supplied to the sub-control unit, but the voltage drop detection unit detects whether the voltage of the power supply has dropped for a predetermined time, and when the voltage drop detection unit detects the voltage drop, a voltage drop signal is output. The output means outputs the voltage drop signal to the main control means and / or the sub control means.

The main control means and the sub-control means, which have received the voltage drop signal, protect the data, detect winning balls, and detect prize balls, for example, during a predetermined time. As a result, the main control unit and the sub control unit can receive the voltage drop signal before the power supply is cut off and perform a predetermined process before the power supply is cut off. When the supply is restarted, it is possible to perform a process of returning to the state when the power supply was cut off. Therefore,
When returning from a power outage, it becomes easy to continue the game state before the power outage and continue paying out the prize balls, so that it is possible to improve the satisfaction level of the player.

A gaming machine according to an eighth aspect of the present invention is summarized as comprising the gaming machine according to the seventh aspect, wherein the operation starting means is provided in the power supply means. This makes it possible to centrally start the operation of the main control means and the sub-control means in the gaming machine, and the main control means,
It is possible to synchronize the operation start timing with the sub control means.

As a result, all the operation start times of the main control means and the sub control means can be accurately controlled, and there is no variation. Therefore, the delay time of the delay process and the operation after the power supply is restored It is possible to set the time until the start processing is started with high accuracy. In other words, there is no need to increase the safety factor that absorbs variations,
It can be set to the optimum value obtained from theory or experiment. Therefore, when the power is restored from the power failure, the time to start the operation can be made almost the same as the theoretical minimum value and can be made extremely short, and the frustration due to the delay in operation can be prevented, and It has an extremely excellent effect that the degree of satisfaction can be improved.

A game machine according to a ninth aspect of the present invention is characterized in that the delay means has a noise filter function of shielding noise contained in a signal supplied from the power supply means to the main control means. The gist is to provide the gaming machine according to any one of claims 1 to 8.

The delay means has, for example, a combination of an RC type low pass filter structure and a Schmitt circuit, provides a delay time, removes high frequency and pulsed noise, and controls the control circuit. It has an extremely excellent effect of preventing malfunction.

According to a tenth aspect of the present invention, a gaming machine has a main backup storage means for storing the state of the main control means at the time when the power supplied to the main control means drops, and the start of operation of the main control means. 10. A main control state returning means for returning the state of the main control means to the state at the time when the power supply is lowered based on the storage of the main backup storage means. The gist is to provide the game machine according to any one of 1.

Thus, when a power failure occurs, the main backup storage means stores the state of the main control means. In that state, when the power supply is restored from the power failure, the operation starting means starts the operation of the main control means, and then the main control state returning means changes the state of the main control means based on the stored contents of the main backup storage means. Return to the state when the power was reduced.

Therefore, the main control means executes the continuation of the control before the power failure after returning from the power failure. As a result, after the recovery from the power failure, you can continue the game that was interrupted by the power failure, and if the player was in an advantageous state before the power failure, the advantageous state is maintained and the It is possible to provide a game after returning, and it is possible to improve the satisfaction of the player, which is an extremely excellent effect.

A gaming machine according to the invention of claim 11 has a sub backup storage means for storing the state of the sub control means at the time when the power supplied to the sub control means drops, and the start of operation of the sub control means. At times, when it is determined that the sub control means has become the same as the state at the time of the power supply drop based on the storage of the sub backup storage means, the sub control means returns to the state at the time of the power supply drop. It is a gist to provide the gaming machine according to any one of claims 1 to 10, characterized in that a power supply lowering time point return judging means for judging that it has been added is added.

As a result, when a power failure occurs, the sub backup storage means stores the state of the sub control means. In this state, when the power supply is restored from the power failure, the operation starting means starts the operation of the sub control means. Next, the power supply reduction time point return determination means determines, based on the stored contents of the sub backup storage means, whether the sub control means has become the same as the state at the time when the power supply is reduced, and the same as the state at the time when the power supply is reduced. When it is determined that the sub-control means has reached the next stage, for example, the sub-control means shifts to the processing of the next stage.

That is, when the power supply is restored from the power failure,
The sub-control unit determines whether the states before and after the power failure are the same state, and if they are the same, the process proceeds to the next step. As a result, after recovery from a power outage, it is returned to the state it was in when it was interrupted by a power outage, and the prize balls that were in the process of being paid out before the power outage were paid out, for example. Then, since it is possible to continue the game, there is an extremely excellent effect that the satisfaction level of the player can be improved.

According to a twelfth aspect of the present invention, a gaming machine has a signal input state backup storage means for storing the input state of a signal to the sub control means at the time when the power supplied to the sub control means drops, and the sub control means. When it is determined at the start of operation of the control means that the signal input to the sub control means has become the same as the state at the time when the power supply is reduced, based on the storage of the signal input state backup storage means, 11. The power-supply-down-time signal input state restoration judging means for judging that the signal input state of the control means has returned to the state at the time when the power supply is lowered, according to any one of claims 1 to 10. The main point is to equip the game machine.

Thus, when a power failure occurs, the signal input state backup storage means stores the signal input state of the sub control means. In this state, when the power supply is restored, the operation starting means starts the operation of the sub control means. When the sub-control means starts operating, first, the power-down time signal input state recovery determination means determines the signal input state of the sub-control means based on the stored contents of the signal input state backup storage means and the state at the time when the power supply drops. If it is determined that they are the same, and if it is determined that the state is the same as the state at the time when the power supply is lowered, for example, the process proceeds to the next stage.

That is, when the power supply is restored from the power failure,
The sub-control means determines whether the input states of the signals before and after the power failure are the same state, and if they are the same, the process proceeds to the next step. As a result, after the recovery from the power failure, after confirming that the instruction at the time of interruption due to the power failure was received, the subsequent signal is used to perform the subsequent processing, for example, before the power outage The payout of prize balls is continued without excess or deficiency, and the player can be satisfied with the disbursement of prize balls without distrust and can continue the game, thus improving the satisfaction of the player. It has an extremely excellent effect that it can be achieved.

According to a thirteenth aspect of the present invention, there is provided a gaming machine according to claim 13, wherein a signal input state backup storage means for storing a signal input state to the sub control means at the time when the power supplied to the sub control means is lowered, and the sub control means. At the start of the operation of the control means, on the basis of the storage of the signal input state backup storage means, wait until it is determined that the signal input to the sub-control means has become the same as the state at the time when the power supply drops, When the input state of the signal to the sub-control means becomes a signal at the time when the power supply to the sub-control means is low, the input control standby state is that the sub-control means is returned to the state at the time when the power supply is decreased. Means for adding means are provided.
The gist is to provide the game machine according to any one of 1.

Thus, when a power failure occurs, the signal input state backup storage means stores the signal input state of the sub control means. In this state, when the power supply is restored, the operation starting means starts the operation of the sub control means. When the operation of the sub-control means is started, the input return standby means, based on the stored contents of the signal input state backup storage means,
Wait until it is determined that the input state of the signal of the sub-control unit is the same as the state at the time of the power reduction, and if it is determined to be the same as the state at the time of the power reduction, for example, The process shifts to the stage.

That is, when the power supply is restored from the power failure,
The sub control means waits until the input states of the signals before and after the power failure become the same state, and shifts to the processing of the next stage. As a result, after the recovery from the power failure, after receiving the command at the time of interruption due to the power failure, based on the subsequent signal,
Continuing, for example, the payout of prize balls that were in the process of paying out before the power outage was continued without excess or deficiency, and the player was convinced of the prize ball payout without distrust,
Since it is possible to continue the game, there is an extremely excellent effect that the satisfaction of the player can be improved.

According to the fourteenth aspect of the present invention, the gaming machine according to the fourteenth aspect monitors for a predetermined time whether or not it has been judged by the power down time point return judging means that it has returned to the state at the time of the power down, and the predetermined time elapses. 12. A gaming machine according to claim 11, further comprising a watchdog timer for initializing the sub-control means when it is not judged that the power has returned to the state at the time of power reduction. That is the summary.

Thus, when a power failure occurs, the sub backup storage means stores the state of the sub control means. In this state, when the power supply is restored, the operation starting means starts the operation of the sub control means. When the operation of the sub-control means is started, the power-supply-down-time-restoring-judging means determines, based on the stored contents of the sub-backup storage means, whether or not the sub-control means has reached the same state as when the power is turned off, and the power is turned off. When it is determined that the state is the same as the state at the time of performing, the sub control unit shifts to the processing of the next stage.

If it is not judged that the power has returned to the state at the time when the power source drops, until the predetermined time elapses after the start of the operation of the sub control means, the watchdog timer causes the sub control means to operate. initialize. Therefore, if the states before and after the power failure are not the same, the sub control means is initialized. The initialized sub control unit executes control based on the command sent from the main control unit.

As a result, after the recovery from the power failure, it is judged whether or not there is any abnormality, and if there is no abnormality, the continuation of the control before the power failure is executed. When there is an abnormality, the sub control means is initialized. In other words, if the sub-control means determines that some abnormality has occurred due to a power failure, first the sub-control means is initialized, and after recovery from the power failure, according to the signal transmitted from the main control means, Perform a predetermined operation.

Therefore, for example, even if an abnormality occurs in the main control means and it becomes impossible to control the sub control means from the main control means, the sub control means returns to the normal state by itself, and the recovery function in case of abnormality is improved. That is an extremely excellent effect. Incidentally, when the watchdog timer initializes the sub control means, by outputting this, it becomes possible to obtain maintenance information of the gaming machine.

In the gaming machine of the fifteenth aspect of the present invention, the input state of the signal to the sub-control means becomes a signal at the time when the power source of the sub-control means decreases even if the input return standby means exceeds a predetermined time. When not, the sub-control means is initialized, and the game machine according to claim 13 is provided.

Thus, when a power failure occurs, the sub backup storage means stores the state of the sub control means. In this state, when the power supply is restored, the operation starting means starts the operation of the sub control means. When the operation of the sub-control means is started, the power-down time point return determination means waits until it is determined that the sub-control means is in the same state as the time point when the power supply is decreased, based on the stored contents of the sub-backup storage means, Then, when it is determined that the state is the same as the state at the time when the power supply is reduced, the sub-control unit shifts to the process of the next stage.

If it is not judged that the power has returned to the state at the time when the power source is lowered, after the start of the operation of the sub-control means, until the lapse of a predetermined time, the sub-control means is initialized. Therefore, if the states before and after the power failure are not the same, the sub control means is initialized. The initialized sub control unit executes control based on the command sent from the main control unit.

As a result, after the recovery from the power failure, it is judged whether or not there is any abnormality, and if there is no abnormality, the continuation of the control before the power failure is executed. When there is an abnormality, the sub control means is initialized. In other words, if the sub-control means determines that some abnormality has occurred due to a power failure, first the sub-control means is initialized, and after recovery from the power failure, according to the signal transmitted from the main control means, Perform a predetermined operation.

Therefore, for example, even if the main control means becomes abnormal and the main control means cannot control the sub control means, the sub control means returns to the normal state by itself, and the recovery function in case of abnormality is improved. That is an extremely excellent effect.

[0053]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described. FIG. 1 shows a main board 1 as main control means, a prize ball control board 3 as sub-control means, a pattern control board 7, a sound control board 9, a lamp control board 11, a launch control board 13, and a power supply means. 2 is a block diagram relating to an interface with the power supply board 15, and FIG. 2 is a block diagram of an electric control system of the gaming machine 5.

Although not shown in the figure, the gaming machine 5 dispenses a prize (prize ball) of the gaming ball when the gaming ball wins the winning opening and provides a pachinko game that outputs interesting images and sounds. As shown in FIG. 2, the main board 1 for game control is centered and the following boards and the like are provided.

That is, the game machine 5, although not described in detail, has a main board 1 for main control, a prize ball control board 3, a symbol control board 7, a voice control board 9, a lamp control board 11, for sub-control.
A firing control board 13 and a power supply board 15 are provided.
The main board 1 has an input switch (input SW) 16 as shown below, a special winning opening SOL, and an ordinary electric accessory S.
An output solenoid (output SOL) 18 such as an OL, and an external terminal board 21 for a board such as the number of symbol determinations, a big hit, a special winning opening, etc.
, A supply ball shortage switch (supply ball shortage SW) 23, and a lower saucer full switch (lower saucer full SW) 25 are connected.

The input SW16 is a switch signal by a 9-bit signal line such as a first-type starting opening SW, a specific area SW, a special winning opening SW, an ordinary symbol actuation gate SW, an ordinary electric prize SW, an ordinary winning opening SW, etc. (SW signal) is supplied to the main substrate 1. In addition, the main board 1 has an 8-bit data signal and 1
By supplying the strobe signal of the bit to the prize ball control board 3, the symbol control board 7, the voice control board 9, and the lamp control board 11, the following processes are performed.

The prize ball control board 3 receives the prize ball SW1 based on the data signal and the strobe signal input from the main board 1.
(31), prize ball SW2 (32), ball rental SW1 (33),
Using the ball renting SW2 (34), the prize ball motor control SW35, and the prize ball motor 37, the game balls are paid out to a not-shown upper plate, and a 1-bit launch control signal is launched.
Output to. Also, on the prize ball control board 3, a status indicator 46
Is attached, and the frame external terminal board 41 is connected. The frame external terminal board 41 is provided with a prize ball terminal, a ball lending terminal, a metal frame opening terminal, and an inner frame opening terminal.
And the inner frame opening SW 45 are connected.

The award ball SW1 (31) and the award ball SW2 (3
2), the ball renting SW1 (33), the ball renting SW2 (34), the prize ball motor control SW35, and the prize ball motor 37 are components of the prize ball payout device 600 whose schematic configuration is shown in FIG. The prize ball paying-out device 600 is a mechanism for performing ball lending and paying-out of prize balls, and a ball receiving tank 602 for storing game balls supplied from an island returning device for game balls (not shown) and a ball receiving tank 602. A ball transport path 604 for transporting the game balls stored in, a shortage supply ball SW23 for detecting whether a game ball exists in the ball transport path 604, and a prize ball supplied from the ball transport path 604 Case 606 and prize ball case 6
A discharge path 608 (608A, 608B, 608) for discharging through a game ball discharged from 06 to a tray (not shown)
C, 608D).

A ball receiving tank 602 and a ball transfer path 604
Since the supply ball shortage SW 23 and the discharge path 608 are substantially the same as those conventionally used, detailed description thereof will be omitted. The prize ball case 606 is equipped with a prize ball SW1 (31) and a prize ball SW2 (32) for counting the number of prize balls, and a ball rental SW1 (33) and a ball rental SW2 (34) for counting the ball loan number. ing.

FIG. 26 shows a configuration diagram of the prize ball case 606. FIG. 26 (A) is a right side view, FIG. 26 (B) is a front view,
(C) is a plan view, (D) is a cross-sectional view of the cutting plane A,
(E) is a cross-sectional view of the cut surface B. Prize ball case 606
Is a prize ball motor mounting chamber 610 for holding and storing the prize ball motor 37, a sprocket chamber 612 for rotatably holding and storing a sprocket unit 614 fitted on a shaft 37A of the prize ball motor 37, and a mounting claw. And 620.

The sprocket unit 614 is constructed by connecting a first sprocket 622 and a second sprocket 624 which have the same size with three teeth (FIG. 26).
(D)). The phase difference between the first sprocket 622 and the second sprocket 624 is such that the crest of one tooth and the trough of the other tooth have the same rotation angle. That is, when the crests of the teeth of the first sprocket 622 face upward, the troughs of the teeth of the second sprocket 624 are shown in FIG.
(E), they are connected so as to face upward. By connecting with such a phase difference, by using the first sprocket 622 with three teeth and the second sprocket 624, it is possible to pay out six game balls by one rotation of the sprocket unit 614. Also, it is possible to pay out an odd number of game balls.

The sprocket chamber 612 holds the sprocket unit 614, and supplies the game balls supplied from the ball transfer path 604 to the first supply path 632 for supplying the first sprocket 622 and the second sprocket 624. And a second supply path 634. Further, the sprocket chamber 612 is connected to the prize ball SW1 (3
1) The first sprocket 62 is passed through the position detected by
2 through the first prize ball discharge path 642 for discharging the game ball carried by 2 to the discharge path 608A and the position detected by the prize ball SW2 (32) from the second supply path 634
The first sprocket passes through the second prize ball discharge path 644 for discharging the game balls conveyed by the sprocket 624 to the discharge path 608A, and the position detected by the ball rental SW1 (33) from the first supply path 632. The first ball rental discharge path 646 for discharging the game ball conveyed by 622 to the discharge path 608A, and the ball rental SW2 (3 from the second supply path 634.
The second sprocket 62 is passed through the position detected by 4).
The second ball rental discharge path 648 for discharging the game balls conveyed by the No. 4 to the discharge path 608A.

As a result, in the prize ball case 606, the prize ball motor 37 is moved to the first position on the prize ball SW1 (31) side (direction of arrow A).
When the sprocket 622 rotates 1/3, one of the game balls is taken in from the first supply path 632, and the first prize ball discharge path 6
Discharge to 42. Furthermore, the first sprocket 622 is 1/6
When rotated, one game ball taken from the second supply path 634 is discharged to the second prize ball discharge path 644.

Similarly, in the prize ball case 606, when the prize ball motor 37 rotates toward the ball renting SW1 (33) side (direction of arrow B), the game ball is taken in from the first supply path 632,
It discharges to the ball rental discharge path 646, and the game balls are supplied to the second supply path 634.
And discharged to the second ball rental discharge path 648.

FIG. 27 is an explanatory view of the operation of the prize ball case 606, (A) is an explanatory view of the prize ball payout operation, and (B).
[Fig. 7] is an explanatory diagram of a ball rental operation. The prize ball case 606 includes a first supply path 632, a first prize ball discharge path 642, and a first ball rental discharge path 646. The end of the first supply path 632 and the first prize ball discharge path 642. Of the beginning and the first ball rental discharge route 6
The start end of 46 is the conveyance start position 652 of the first sprocket 622. The first supply path 632 has a game ball mounting recess 654 near the transport start position 652. The first prize ball discharge path 642 has a downward slope of 10 degrees from the first release point RPA located near the transfer start position 652, and the first ball rental ball discharge path 646 is located near the transfer start position 652. Second release point RPB
It has a downward slope of 10 degrees. As a result, first
The game ball that has fallen from the supply path 632 from above is sent to the transport start position 652 of the first sprocket 622, and stops on the mounting recess 654. In this state, when the first sprocket 622 rotates in the direction of arrow A, the game ball moves to the first sprocket 622 as shown in FIG.
Is sent between the teeth of and enters the first prize ball discharge path 642. Then, when it exceeds the first release point RPA, it is conveyed by the first sprocket 622 in the first prize ball discharge passage 642 and naturally falls. Further, when the first sprocket 622 rotates in the direction of the arrow B while the game ball is stopped on the mounting recess 654, as shown in FIG. 27B, the game ball is located between the teeth of the first sprocket 622. And sent into the first ball rental discharge path 646. Then, when the second release point RPB is exceeded, the first sprocket 622 conveys the inside of the first ball rental discharge passage 646, and
It falls naturally.

Further, the game balls are conveyed in the first prize ball discharge passage 642 by the first sprockets 622, and at the position of the natural falling state, that is, on the downstream side of the first release point RPA in the first prize ball discharge passage 642. Award ball SW1 (3
1) is set to the detection position for detecting the game ball. The game ball is in the first ball rental discharge path 646, the first sprocket 62.
While being conveyed by 2, the detection position where the ball rental SW1 (33) detects the game ball is set at the position of the natural falling state, that is, on the downstream side of the second release point RPB in the first ball rental discharge path 646. There is.

As a result, when the first sprocket 622 rotates in the direction of arrow A and exceeds the first release point RPA, the game ball naturally falls due to gravity even if the rotation of the first sprocket 622 stops at that position. Then, the movement in the first prize ball discharge path 642 is continued, and the first prize ball discharge path 608 is discharged. Also, the game ball is the first release point RPA
Beyond that, be sure to use the prize ball SW1 (31)
To be detected.

On the other hand, when the first sprocket 622 rotates in the direction of arrow B and exceeds the second release point RPB,
Even if the rotation of the first sprocket 622 is stopped at that position, the game ball naturally falls due to gravity, continues to move in the first ball rental discharge route 646, and is discharged to the discharge route 608. Also, it is always detected by the ball rental SW1 (33).

The same applies to the side of the second sprocket 624, and detailed description thereof will be omitted. As described above, in the prize ball case 606, the rotation direction of one prize ball motor 37,
Only by controlling the rotation angle, payout of game balls is realized while distinguishing prize balls from ball rentals.

Returning to the explanation of FIG. 2, the symbol control board 7 is
Based on the data signal transmitted from the main board 1 and the strobe signal, a special symbol display device (special symbol LCD)
47 and normal symbol display device (ordinary symbol 7 segment LC
D) 49 is used to display the special symbol of the game and the normal symbol.

The voice control board 9 outputs the sound related to the game using the speaker 51 based on the data signal transmitted from the main board 1 and the strobe signal. The lamp control board 11 generates an illumination pattern related to the game by using the illumination 53 such as an LED / lamp based on the data signal transmitted from the main board 1 and the strobe signal.

The launch control board 13 inputs a 1-bit launch control signal from the prize ball control board 3 and outputs the touch plate 61.
, Is connected to the firing stop SW 63 and the firing motor 65, and controls the firing of the game ball. The main board 1, the prize ball control board 3, the symbol control board 7, the voice control board 9, the lamp control board 11, and the launch control board 1 which are outlined above.
3 is a reset signal line RSW from the power supply board 15.
, + 5V power supply line DGW5 and + 12V power supply line DGW12 are connected. A + 32V power supply line DGW32 is connected to the main board 1 and the firing control board 13, and a + 24V power supply line DGW24 is connected to the lamp control board 11.

The reset signal line RSW includes a main board 1, a prize ball control board 3, a symbol control board 7, and a voice control board 9.
The lamp control board 11 and the firing control board 13 are collectively reset from the power supply board 15, and are mainly used for initialization at the start of power supply.

From the power supply board 15, the power failure signal line TS
W, backup power supply line BKW, clear signal line CS
W is connected to the main board 1 and the prize ball control board 3. Power failure signal line TSW and backup power line BKW
The main board 1 to which the clear signal line CSW is supplied and the prize ball control board 3 are both provided with a well-known microcomputer for a game machine in consideration of security. This microcomputer includes a CPU, ROM, RAM
Is provided. RAM is the backup power line BK
The backup power supply supplied by W retains data even after the power of the + 5V power supply supplied by the + 5V power supply line DGW5 is reduced. Here, the power supply board 15 that supplies power to the backup power supply line BKW has the ability to supply backup power for 20 hours or more after the power supply to the gaming machine 5 is cut off.

Next, based on FIG. 1, the power supply board 15 and
A configuration for performing power supply and signal supply among the main board 1, the prize ball control board 3, the symbol control board 7, the voice control board 9, the lamp control board 11, and the launch control board 13 will be described. To do. The detailed description of the configuration is omitted.

The power supply board 15 supplies power and signals to the main board 1, the prize ball control board 3, the symbol control board 7, the voice control board 9, the lamp control board 11, and the launch control board 13. In order to perform the above, the clear SW 121, the power failure signal creation circuit 123, the reset signal creation circuit 125, the main board and prize ball control board backup power supply creation circuit 12
7, + 5V, + 12V power supply generation circuit 131, +24
And a + 32V power supply generation circuit 133.

The clear SW 121 is a push button switch structure attached to a position operable from the back side of the gaming machine 5, and is attached on the power supply board 15. Instead of the push button structure, a key switch structure operated by a predetermined key may be used. Clear SW1
A clear signal line CSW is connected to 21. The clear signal line CSW is connected to the main board 1 and the prize ball control board 3. Details of the connection destination will be described later.

The power failure signal generating circuit 123 is configured to operate the power failure signal line T
It is connected to the SW and outputs a power failure signal described later to the main board 1 and the prize ball control board 3. Reset signal generation circuit 125
Is connected to a reset signal line RSW, and sends a reset signal to be described later to the main board 1, the prize ball control board 3, the pattern control board 7, the voice control board 9, the lamp control board 11, and the launch control board 13. Output to.

The main board and award ball control board backup power supply generation circuit 127 is connected to the backup power supply line BKW and outputs a backup power source, which will be described later, to the main board 1 and the award ball control board 3. The + 5V and + 12V power supply generation circuit 131 is connected to the + 5V power supply line DGW5 and the + 12V power supply line DGW12, and the + 5V power supply and the + 12V power supply, which will be described later, are the main board 1, the prize ball control board 3, and
It outputs to the symbol control board 7, the voice control board 9, the lamp control board 11, and the firing control board 13.

+ 24V, + 32V power supply generation circuit 133
Is + 24V power supply line 24 and + 32V power supply line D
It is connected to the GW 32, supplies a + 24V power source described later to the lamp control board 11, and outputs a + 32V power source to the main board 1 and the firing control board 13. The main board 1, which is supplied with power (+ 5V, + 12V, + 32V), reset signal, etc. from the power board 15, includes a micro control unit (MPU) 71 including a CPU, a ROM, a RAM, and the like.
System reset circuit 141 connected to U71, power failure signal receiving circuit 143, and clear signal receiving circuit 145
, Port circuit 147, and strobe signal transmission circuit 14
9 and a data signal transmission circuit 150.

The MPU 71 has a RESET terminal 151,
NMI terminal 153, PORT terminal 157, DATA
And a terminal 159. Note that the line indicating the low enable, which is the line above the character “NMI” like the NMI terminal 153, is described only in the drawings, and is not described in the specification. The symbols used to describe the terminals of the MPUs 71 and 83 comply with the standard of the microprocessor indicated by the trademark "Z80" of Zilog Corporation in the United States unless otherwise specified.

The system reset circuit 141 connected to the reset signal line RSW is connected to the RESET terminal 151, and the reset signal is input via the system reset circuit 141. The operation of the MPU 71 will be described later. The NMI terminal 153 is connected to the power failure signal receiving circuit 143 connected to the power failure signal line TSW, and inputs the power failure signal via the power failure signal receiving circuit 143.

The PORT terminal 157 is connected to the clear signal line CS.
The clear signal receiving circuit 145 connected to W is connected, and the clear signal is input via the clear signal receiving circuit 145. The DATA terminal 159 is connected to the port circuit 147.
By outputting data to the strobe signal transmission circuit 149 and the data signal transmission circuit 150 via
Prize ball control board 3, symbol control board 7, and voice control board 9
And a strobe signal for controlling the lamp control board 11 and a data signal. The strobe signal is
The data signal output to the strobe signal line STBW is
It is output to the data signal line DATAW.

From the power supply board 15 to the power supply (+ 5V, +12
V) and reset signal etc. prize ball control board 3
Is a micro control unit (MPU) 83 including a CPU, ROM, RAM, etc., a system reset circuit 161 connected to this MPU 83, and a power failure signal receiving circuit 16
3, a strobe signal receiving circuit 165, a data signal receiving circuit 167, a port circuit 169, a firing control signal output circuit 171, and a clear signal receiving circuit 177.

The MPU 83 has a RESET terminal 173,
NMI terminal 175, PORT terminal 181, CLK /
A TRG2 terminal 179 and a DATA terminal 183 are provided. The RESET terminal 173 is a reset signal line RSW.
Is connected to the system reset circuit 161 and inputs a reset signal via the system reset circuit 161. The operation of the MPU 83 will be described later.

The NMI terminal 175 is connected with the power failure signal receiving circuit 163 connected to the power failure signal line TSW,
A power failure signal is input via the power failure signal receiving circuit 163. The strobe signal receiving circuit 165 connected to the strobe signal line STBW is connected to the CLK / TRG2 terminal 179, and the strobe signal is input via the strobe signal receiving circuit 165.

The DATA terminal 183 is connected to the data signal line DA
A data signal is input through the data signal receiving circuit 167 connected to the TAW and the port circuit 169. or,
The data signal branched by the port circuit 169 is connected to the firing control signal output circuit 171.

From the power supply board 15 to the power supply (+ 5V, +12
V) and the design control board 7 which receives the supply of the reset signal etc.
Includes a micro control unit (MPU) 181 including a CPU, ROM, RAM, etc., a system reset circuit 184 connected to this MPU 181, a strobe signal receiving circuit 185, and a data signal receiving circuit 187.

The MPU 181 has a RESET terminal 189.
And an INT0 terminal 191 and a PORT terminal 193. The RESET terminal 189 is connected to the reset signal line R
The system reset circuit 184 connected to SW is connected, and inputs a reset signal via the system reset circuit 184. The operation of the MPU 181 will be described later.

The INT0 terminal 191 is connected to the strobe signal receiving circuit 185 connected to the strobe signal line STBW, and inputs the low enable strobe signal via the strobe signal receiving circuit 185. PO
The RT terminal 193 inputs the data signal via the data signal receiving circuit 187 connected to the data signal line DATAW.

From the power supply board 15 to the power supply (+ 5V, +12
V) and a voice control board 9 that receives a reset signal, etc.
Includes a micro control unit (MPU) 231 including a CPU, ROM, RAM, etc., a system reset circuit 233 connected to this MPU 231, a strobe signal receiving circuit 235, and a data signal receiving circuit 237.

The MPU 231 has a RESET terminal 239.
And an INT1 terminal 241 and a PORT terminal 243. The RESET terminal 239 is connected to the reset signal line R
The system reset circuit 233 connected to SW is connected, and inputs a reset signal via the system reset circuit 233. The operation of the MPU 231 will be described later.

The INT1 terminal 241 is connected to the strobe signal receiving circuit 235 connected to the strobe signal line STBW, and inputs the strobe signal via the strobe signal receiving circuit 235. PORT terminal 243
Inputs a data signal via the data signal receiving circuit 237 connected to the data signal line DATAW.

From the power board 15 to the power supply (+ 5V, +12
V, + 24V) and a reset signal are supplied to the lamp control board 11, and a micro control unit (MPU) 201 including a CPU, a ROM, a RAM, and the MPU 2 are provided.
01, the system reset circuit 203, the strobe signal receiving circuit 205, and the data signal receiving circuit 20.
7 and 7.

The MPU 201 has a RESET terminal 209.
And an INT1 terminal 211 and a PORT terminal 213. The RESET terminal 209 is connected to the reset signal line R
A system reset circuit 203 connected to SW is connected, and a reset signal is input via the system reset circuit 203. The operation of the MPU 201 will be described later.

The INT1 terminal 211 is connected to the strobe signal receiving circuit 205 connected to the strobe signal line STBW, and inputs the strobe signal via the strobe signal receiving circuit 205. PORT terminal 213
Inputs a data signal via the data signal receiving circuit 207 connected to the data signal line DATAW.

From the power supply board 15 to the power supply (+ 5V, +12
V, + 32V), the reset control signal, and the like are supplied to the firing control board 13, and the firing control circuit 25 includes an electronic control circuit.
1, a reset circuit 253 connected to the firing control circuit 251, and a firing control signal input circuit 255.

The firing control circuit 251 uses the reset signal line R
The reset signal is input via the reset circuit 253 connected to SW, and the emission control signal is input via the emission control signal input circuit 255 connected to the emission control signal line HSSW. Next, with the clear SW 121 of the power supply board 15,
Power failure signal creating circuit 123 and reset signal creating circuit 12
5, a backup power supply creation circuit 127 for the main board and the prize ball control board, and a + 5V, + 12V power supply creation circuit 131
And an example of a specific circuit configuration for providing the + 24V and + 32V power supply generation circuit 133 will be described with reference to FIGS. 3 and 4.

As shown in FIG. 3, the power supply board 15 is an AC board.
A rectifier unit 301 that receives and rectifies a 24V power source, and a DC power source output from the rectifier unit 301 is smoothed to + 5V.
A DC-DC converter unit 303 for converting to a + 12V DC power supply, a power failure signal / reset signal creation unit 305 for generating a power failure signal and a reset signal, an output buffer unit 307 for outputting a power supply and a signal, and FIG. Output terminal section 30
9 and 9. 3 and 4 show the power supply board 15 in a divided manner. FIG. 3 shows the configuration of the output buffer unit 307 on the input side, and FIG. 4 shows the configuration of the output buffer unit 307 on the output side.

In the rectifying section 301, the received AC 24 V is rectified by the bridge rectifier 315 and then output as it is +2.
The 4V output part 311 and the + 32V output part 313 which outputs via the smoothing circuit 317 are provided. The output of the bridge rectifier 315 of the rectifying unit 301 is DC-DC.
It is supplied to the first smoothing unit 321 and the second smoothing unit 322 of the converter unit 303.

The power supplied to the first smoothing section 321 is converted to + 5V by the regulator 325 and supplied to the backup capacitors 327 and 329. The backup capacitor 327 is the + 5V-a output unit 33.
1 and the + 5V-b output section 333 are supplied with the backup + 5V power, and the backup capacitor 32 is provided.
9 was backed up to the + 5V-b output unit 333 +
Supply 5V power.

The power supplied to the second smoothing section 322 is converted to + 12V by the regulator 325 and supplied to the backup capacitor 328. The backup capacitor 328 supplies the backed up + 12V power to the + 12V output unit 335.

The power failure signal / reset signal generation unit 305
A commonly used reset IC (341) (MITSUBISHI
ELECTRIC M5297P is a power supply monitoring IC (34
7) and the like, based on the output states of the bridge rectifier 315 and the regulator 325, the ΣACD L terminal 3
A power failure signal described later in detail is output to 43, and a reset signal described below in detail is output to the ΣREL terminal 345.

The power failure signal output to the ΣACDL terminal 343 and the reset signal output to the ΣREL terminal 345 are the three-state buffer IC of the output buffer unit 307.
It is supplied to the output terminal unit 309 via (351). The output terminal portion 309 is a lamp / voice connector 3
61, a connector for design 363, and a connector for firing 36
5, a prize ball connector 367, and a main board connector 36
9, the power failure signal is supplied to the prize-power failure signal terminal 371 of the prize ball connector 367 and the main-power failure signal terminal 373 of the main board connector 369, and the reset signal is supplied to the lamp / voice connector 361. Error reset signal terminal 381, the sound-reset signal terminal 382, the figure-reset terminal 383 of the symbol connector 363, the launch-reset terminal 385 of the launch connector 365, the prize-reset terminal 387 of the prize ball connector 367, and the main It is supplied to the main reset terminal 389 of the board connector 369.

The clear SW 121 has a push button switch structure attached to a position operable from the back side of the gaming machine 5, and has a normally open contact 395 pulled up by a + 5V-a power source, which is a 3-state buffer IC (351). ) Is connected to the prize-clear signal terminal 391 of the prize ball connector 367 and the main-clear signal terminal 393 of the main board connector 369.

The output terminals (1Y1 to 2Y4) 352 of the 3-state buffer IC (351) and the output terminal section 309.
Between the protective resistor R1 having a resistance value of 220 ohms
9, R20, R21, R22, R23, R24, R2
5, R26, R27, R28 are inserted. The protection resistors R19 to R28 are used to prevent the 3-state buffer IC (351) from being destroyed when static electricity enters from the output terminal portion 309 which is the output signal line of the power supply board 15.

This prevents static electricity from invading the output signal line of the power supply board 15 and destroying the IC of the power supply board 15 while the power supply board 15 is being transported or handled. The output line protection resistor is also attached to the main board 1, the prize ball control board 3, the pattern control board 7, the voice control board 9, the lamp control board 11, and the firing control board 13 in the same manner. Has been.

Further, the lamp / voice connector 361 of the output terminal portion 309 is + 5V-a although a detailed description thereof is omitted.
+ 5V-a power source output from the output unit 331, +12
+ 12V power output from the V output unit 335, + 24V
The + 24V power source output from the V output unit 311 is connected. Although detailed description is omitted, the symbol connector 363 has + 5V-a output from the + 5V-a output unit 331.
-A power source and +1 output from + 12V output section 335
2V power supply is connected. Although detailed description is omitted, the firing connector 365 has a + 5V-a power source output from the + 5V-a output unit 331 and a + 12V output unit 335.
+ 12V power output from the, and + 32V output unit 313
It is connected to the + 32V power source output from. For the prize ball connector 367, a detailed description is omitted, but + 5V
+ 5V-a power source output from the -a output unit 331, +
The + 5V-b power supply output from the 5V-b output unit 333 and the + 12V power supply output from the + 12V output unit 335 are connected. Although not described in detail, the main board connector 369 has a + 5V-a power supply output from the + 5V-a output section 331, a + 5V-b power supply output from the + 5V-b output section 333, and a + 12V output section. The + 12V power source output from the 335 and the + 32V power source output from the + 32V output unit 313 are connected.

The lamp / voice connector 361, the symbol connector 363, the firing connector 365, the prize ball connector 367, and the main board connector 369 of the output terminal portion 309 are the same as those shown in FIGS. As shown, main board 1
It is connected to the prize ball control board 3, the symbol control board 7, the voice control board 9, the lamp control board 11, and the launch control board 13, and supplies a power supply, a power failure signal, a reset signal, and the like.

As described above, the main board 1 which receives the power supply, the power failure signal, the reset signal and the like from the output terminal section 309 is
As shown in FIGS. 5 and 6, the connector 401 uses a power / signal harness (not shown) to connect the main board connector 3
It is connected to 69, performs a predetermined process on the input power failure signal or reset signal, and then supplies it to the MPU 71. 5 and 6 show the main substrate 1 divided into two parts.
Shows mainly the configuration for inputting data to the MPU 71, and FIG. 6 mainly shows the configuration for outputting data from the MPU 71.

Next, a portion for subjecting the signal supplied to the MPU 71 to predetermined processing will be described. Connector 40 shown in FIG.
The main-clear signal terminal 403 of No. 1 passes through the noise filter / waveform shaping unit 405, the CLRSW line 407, an input buffer not shown, and the D6 line of the DATA (0.7) harness 409 shown in FIG. DATA of MPU71
It is connected to the D6 terminal of the terminal 159. This allows
When the clear SW 121 is turned on, a low-level clear signal is supplied to the D6 terminal.

The clear signal supplied to the D6 terminal is
It is monitored in a process described later to start the initialization of the RAM. The main-power failure signal terminal 411 of the connector 401 shown in FIG. 5 is connected to the NMI terminal 153 of the MPU 71 via the noise filter / waveform shaping unit 413.
Further, the NMI terminal 153 is pulled up to + 5V by the pull-up resistor 415 supplied with the + 5V-a power supply. The noise filter / waveform shaping unit 413
The EMI filter element 417, the RC low-pass filter 419, and the two Schmitt inverters 42.
1, 423, and performs waveform shaping processing of the power failure signal input from the connector 401.

As a result, the power failure signal input from the power supply board 15 is hardly delayed, does not include noise, and is binarized into the 0 level and the +5 V level, and the MPU 71
Of the NMI terminal 153. The main reset signal terminal 431 of the connector 401 is connected to the noise filter 433.
And the delay / waveform shaping unit 435, and is connected to the reset signal generation unit 437. Noise filter 43
Reference numeral 3 includes an EMI filter element 439 and an RC low-pass filter 441.

The delay / waveform shaping unit 435 includes a waveform shaping unit 447 composed of two Schmitt inverters 443 and 445 and two Schmitt inverters 451 and 453.
And a delay circuit section 457 including a directional charging / discharging circuit 455 inserted between the Schmitt inverters 451 and 453, and an AND which outputs an AND of these outputs.
And a circuit 459.

As a result, the delay / waveform shaping section 435 is
When the AC 24V supplied to the power supply board 15 goes down, the reset signal becomes a low level and becomes a high level when the supply of the AC 24V is restarted, and the following operation is performed. The waveform shaping section 447 transmits the reset signal as it is to the AND circuit 459 with a slight delay.

The delay circuit section 457 adds a delay of a predetermined time to the reset signal and supplies it to the AND circuit 459, as will be described later in detail. The AND circuit 459 outputs the signal A output from the waveform shaping unit 447 and the signal output from the delay circuit unit 457.
The ND signal is supplied to the reset signal generator 437 and the buffer IC (461) shown in FIG.

As a result, the delay / waveform shaping unit 435 outputs a signal that becomes low level almost simultaneously when the reset signal becomes low level and becomes high level after a predetermined delay time when the reset signal becomes high level. And is supplied to the reset signal generator 437 and the buffer IC (461).

The delay circuit section 457 which constitutes the delay / waveform shaping section 435 adds a predetermined delay to the reset signal, but this delay is a design matter and is based on the specifications and design concept of the gaming machine. , Is set appropriately. The principle of adding this delay will be described with reference to FIG.

FIG. 7A shows the delay / waveform shaping section 435.
FIG. 7B is a detailed circuit diagram of the delay circuit unit 457. The waveform shaping section 447 of the delay / waveform shaping section 435 is provided with the Schmitt inverters 443, 4 only for adding the delay time based on the threshold value and the hysteresis characteristic.
Two 45 are connected in series. Therefore, the reset signal applied to the point a is transmitted to the point e with a slight delay.

The delay circuit section 45 of the delay / waveform shaping section 435.
The directional charge / discharge circuit 455 of No. 7 has a Schmitt inverter 45 while the reset signal applied to the point a is at a high level.
The output impedance of 1 becomes low and the capacitor C8
The electric charge stored in is discharged via the Schmitt inverter 451 and the point b becomes low level. The time constant T = C8 · R8 of the discharge circuit in this case is approximately equal to the discharge time Th and is about 300 ms.

The discharge time Th here is the minimum time Thmin, and the resistance value is 39% with an accuracy of 5 percent.
Minimum time constant Tmin = 390K * of 0KΩ resistor R8 and 1μF capacitor with 20% accuracy
It is calculated as a value that substantially matches 0.95 * 1μ * 0.8 = 296.4 ms.

The delay circuit section 45 of the delay / waveform shaping section 435.
The directional charge / discharge circuit 455 of No. 7 has a Schmitt inverter 45 while the reset signal applied to the point a is at a low level.
The output impedance of 1 becomes high, and the power supply voltage Vcc (+ 5V-a) is output. As a result, the power supply voltage Vcc is stored in the capacitor C8 via the diode D4 and the resistor R7. In this case, the time constant T = C8 · R7 of the charging circuit substantially matches the charging time Tc and becomes about 1 ms.

The charging time Tc here has a resistance value of 1
Time constant T of KΩ resistor R1 and 1 μF capacitor
= 1K * 1μ = 1ms is calculated as a value that substantially matches. The reset signal subjected to the delay processing (delay processing) as described above becomes a signal which rises with a delay of the reset signal by the AND circuit 459, a fall, and a predetermined time (about 300 ms) after the rise of the reset signal. To be converted.

When the reset signal falls due to a power failure, charging of the capacitor C8 is started, but this charging is completed in about 1 ms. Therefore, even if the power failure occurs only for a moment, when the power supply is restarted from the momentary power failure, the charging of the capacitor C8 has already been completed, and the capacitor C8 takes about 300 ms from the rising of the reset signal. Is discharged.

Therefore, the discharge of the capacitor C8 is about 300 m regardless of whether the power failure is a long time or a momentary interruption.
It is guaranteed that the reset signal rises by about 300 ms after any power failure.

As described above, the reset signal whose rising edge is delayed by about 300 ms is the reset signal generator 437 shown in FIG.
Is supplied to the S / L terminal (shift / load terminal) 465 of the shift register 473, and as shown below, the shift register 473 converts the signal into a reset signal for the MPU 71 and outputs the signal from the QH terminal 469 to the RES of the MPU 71.
It is supplied to the ET terminal 151.

The shift register 473 of the reset signal generator 437 divides the signal input from the 12 MHz oscillator circuit 475 into a CK terminal (clock input terminal) 481 and outputs a signal of a predetermined frequency from the frequency divider circuit 471. Input the preset data from the parallel input terminal 483, and input the serial signal from the QH terminal 469 to MP.
Output to U71.

As a result, the reset signal generator 437 is
Supplies a reset signal having a predetermined serial code to the RESET terminal 151 when the reset signal rises.
As a result, the MPU 71 is reset. That is, the delay time (about 300 times) added by the delay circuit unit 457 from the rising edge of the reset signal output from the power supply board 15.
ms), the MPU 71 of the main board 1 is reset,
Will be restarted.

Although illustration of a specific circuit is omitted, the MPU 83 of the prize ball control board 3 and the MPU 1 of the symbol control board 7
81, the MPU 231 of the sound control board 9, the MPU 201 of the lamp control board 11, and the MPU of the firing control board 13.
Although a reset signal is also applied to the power supply board 151, the components corresponding to the delay circuit unit 457 are not provided to the power supply substrate 251, and the MPUs 83, 181, 231 and 201, 251
Added to.

Therefore, with the MPU 83 of the prize ball control board 3,
MPU181 of the symbol control board 7 and M of the voice control board 9
PU231, MPU201 of the lamp control board 11,
The MPU 251 of the firing control board 13 is the MPU of the main board 1.
It will be possible to reset about 71 seconds earlier than 71.

As a result, by the time the main board 1 is activated and the data signal and strobe signal are output, the prize ball control board 3
The pattern control board 7, the voice control board 9, the lamp control board 11, and the firing control board 13 are in an operating state, without leaking the data signal or strobe signal output from the main board 1. You are ready to enter.

After resetting as described above, the data signal and strobe signal output from the MPU 71 are the port circuit IC 481 shown in FIG. 6 and another port circuit I not shown.
It is divided into output destinations (for example, for the prize ball control board 3 and the pattern control board 7) by C or the like, and then passes through a buffer IC, a latch IC, a protection resistor, a protection circuit, and the like (not shown), and a connector (not shown). Award ball control board 3
The pattern control board 7, the voice control board 9, the lamp control board 11, and the emission control board 13 are output.

The reset signal output from the buffer IC (461) is the RE signal of the port circuit IC 481 shown in FIG.
SETN terminal 484 and other port circuit IC not shown
To the RESETN terminal of the above to reset them. In the main board 1 of FIG. 5, the EMI filter elements NF1 and NF are provided between the connector 401 for inputting power and data from the power board 15 and the power and data input circuit.
2, NF3, NF6, 417, 439 are inserted to prevent noise from entering the main board 1.

EMI filter elements NF1 and NF2
Is installed to prevent noise from the + 5V power supply, and is + 5V-a
Noise is prevented from mixing into the power supply and the + 5V-c power supply. EMI filter element NF3 is + 12V
It is installed to prevent noise from the power supply and prevents noise from entering the + 12V power supply. The EMI filter element NF6 prevents noise from being mixed into the clear signal. The EMI filter element 417 prevents noise from entering the power failure signal, and the EMI filter element 439 prevents noise from entering the reset signal.

This EMI filter element is similarly attached to the power supply and data input parts such as the prize ball control board 3, the pattern control board 7, the voice control board 9, the lamp control board 11, the launch control board 13 and the like. The noise that is mixed with the power supply and the data signal and invades.

Further, in the main board 1, an electrolytic capacitor C4OSC having a low ESR (equivalent series resistance) and an excellent temperature characteristic is provided in an input circuit for inputting power from the power supply board 15.
C3OSC, C2OSC, C1OSC (O made by SANYO
S-CON, a capacitor impregnated with an organic semiconductor crystal instead of an electrolytic solution, and an electric conductivity of 300 to 3000 ms / cm)
Is attached to prevent noise from entering the main board 1 from the power supply.

Further, the electrolytic capacitors C4OSC, C3
The OSC, C2OSC, and C1OSC have ideal frequency characteristics of impedance, have high electric conductivity, and their electric conductivity does not change even when the temperature rises. Therefore, the noise mixed in the power source is well absorbed. ,
This noise absorption characteristic hardly deteriorates even if the temperature rises.

The electrolytic capacitor C4OSC is attached to prevent noise from the + 32V power supply and prevents noise from being mixed into the + 32V power supply. Electrolytic capacitor C3OS
C is attached as a noise countermeasure for + 12V power supply,
Prevents noise from entering the 12V power supply. The electrolytic capacitors C2OSC and C1OSC are attached to prevent noise from the + 5V power supply, and the + 5V-a power supply and the + 5V-c power supply are installed.
Prevent noise from entering the power supply.

This low ESR electrolytic capacitor includes a prize ball control board 3, a symbol control board 7, a voice control board 9,
The lamp control board 11 and the firing control board 13 are similarly attached to the power supply input portion to remove noises that enter the power supply and enter. Detailed illustration and description of the output side of the MPU 71 are omitted.

Next, the operating states of the power supply and signals output from the power supply board 15 will be described. FIG. 8 is a timing chart of starting and stopping the power supply board 15. Input power of the power supply board 15,
Output power supply and output signal AC24V, + 24V, +
The specifications and specifications of the power supply board 15 are set so that 32 V, +12 V, +5 V, the backup power supply, the reset signal, and the power failure signal show the states as shown in Table 1 in the state description of FIG.

[0141]

[Table 1]

As shown in FIG. 8, when 150 ms elapses after AC24V is supplied at, the power failure signal changes from a low level (valid) to a high level (invalid). After a further 10 ms, the reset signal changes from low level (valid) to high level (invalid).

AC24V power supply is 10ms
In the following momentary interruptions, it is assumed that there was no power outage.
As shown by, when the AC24V power is not supplied for 10 ms or more, the power failure signal changes from the high level to the low level. As shown by, when the power failure signal changes from the high level to the low level and AC24V is not supplied for 70 ms or more, the reset signal changes from the high level to the low level.

7 before the reset signal changes to low level
The power supply of + 12V and + 5V is maintained for 0 ms. As indicated by, the backup power supply is maintained for 20 hours after the reset signal is changed to the low level.

FIG. 9 is a timing chart of starting and stopping the power supply board 15. When the power failure of AC24V is 10 ms or more,
The state is shown in the case where the AC 24V is restored within 70 ms of the power outage process (in FIG. 8, "at the time of power outage of 10 ms or more and less than 70 ms"). Input power supply of the power supply board 15, output power supply, and output signals AC24V, + 24V, +32
As for V, + 12V, + 5V, backup power supply, reset signal, and power failure signal, as shown in Table 2 with the state explanation in FIG. 9 to the circled numeral 11, the power supply board 15 has specifications and specifications set. Has been done.

[0146]

[Table 2]

As shown in FIG. 9, the power failure signal changes from the high level to the low level 10 ms after the supply of 24V AC is stopped. 24V AC power supply is 1
If it is not more than 0 ms, as shown in (7), 70 ms for power failure processing is forcibly executed, and the reset signal is changed from the high level to the low level when 70 ms has elapsed. However, before the reset signal goes low, the AC
When the supply of the 24V power is restored, as shown in, after the reset signal goes low for 150 ms, the power failure signal is first changed from low to high.
After 10 ms, the reset signal is changed from low level to high level. It should be noted that "150 ms" shown in ~ is a time for monitoring whether or not the power supply is stable, and does not necessarily mean that "150 ms" must be "150 ms".

FIG. 10 is a timing chart of starting and stopping the power supply board 15, showing the state of each control board in a series of operations. Input power supply of the power supply board 15, output power supply, and output signals AC24V, + 24V, + 32V, + 12V, +
5V, backup power supply, reset signal, power failure signal,
Description of state in FIG. 10 ~ As indicated by a circled number 12 as shown in Table 3, each control board is a main board 1, a prize ball control board 3, a pattern control board 7, a voice control board 9, a lamp control. Specifications and specifications of the board 11 and the firing control board 13 are set.

[0149]

[Table 3]

As shown in FIG. 10, the main board 1 is started after 300 ms or more has passed since the reset signal became invalid (high level) as shown in, and the other prize ball control boards 3 and the symbols. The control board 7, the voice control board 9, the lamp control board 11, and the firing control board 13 are activated by 300 ms after the reset signal is invalidated.

That is, when the supply of the 24V AC power source to the gaming machine 5 is started, the delay circuit unit 457 provided in the main board 1 and adding a delay of 300 ms to the reset signal.
Thus, first, the other substrates than the main substrate 1, that is, the prize ball control substrate 3, the pattern control substrate 7, the voice control substrate 9, the lamp control substrate 11, and the launch control substrate 13 are activated, and the main substrate 1
Preparation for receiving data such as a command command sent from is completed, then the main board 1 is completed to start, and the main board 1 transmits a command command to each board.

As shown by, the power failure signal changes from the high level to the low level 10 ms after the supply of 24V AC is stopped. 24ms AC power supply for 10ms
If not, as shown in, 70
ms is forcibly executed, and when 70 ms has elapsed, the reset signal is changed from the high level to the low level. After that, as shown in, the backup period in which the backup power is supplied is started.

In this state, when the supply of 24V AC power is restored, as shown in, after 150 ms has elapsed,
As indicated by the circled numeral 10, the power failure signal is first changed from valid (low level) to invalid (high level), and 10 ms after that, the reset signal is valid (low level) to invalid (high level).
To be

FIG. 11 is a timing chart of the operation transition of each substrate when the power is turned on. 11, the state of the power failure signal, the state of the reset signal, the state of the main board 1, the state of the prize ball control board 3, the state of the symbol control board 7, the state of the voice control board 9, The state of the lamp control board 11 is shown.

As described with reference to FIGS. 8 to 10, in the gaming machine 5, when the power failure occurs and the power failure signal becomes high level, the reset signal becomes high level after about 10 ms. Thereby, the main board 1, the prize ball control board 3, the symbol control board 7, the voice control board 9, and the lamp control board 11
Starts operating in a state as shown in FIG.

In the main board 1, since the reset signal is delayed by about 300 ms by the function of the delay circuit section 457, another prize ball control board 3, the symbol control board 7, the voice control board 9, Compared to the lamp control board 11, the start of operation is delayed by about 300 ms.

A detailed description is omitted, but the main substrate 1
When the reset signal is input, the prize ball control board 3 has a security check time in which a security check is first performed, and then initialization setting or power failure recovery processing is performed to start command transmission (main board 1). , Or command reception (prize ball control board 3). Before the main board 1 starts the command transmission, the prize ball control board 3 is set with the specifications of the delay circuit unit 457 (here, the delay time is about 300 ms) so that the command can be surely received. ing.

As a result, the safety function and the reliability of the main board 1 and the prize ball control board 3 are improved, and the signal is reliably transmitted from the main board 1 to the prize ball control board 3. This guarantees the reliability of information transmission. Further, when the reset signal is input, the symbol control board 7, the voice control board 9, and the lamp control board 11 first perform initial settings and can receive commands. That is, the symbol control board 7, the voice control board 9, and the lamp control board 11, before the main board 1 starts command transmission,
The command can be surely received.

FIG. 12 is a flowchart of the power-on processing routine executed by the main board 1 when the power is turned on. This power-on processing routine is performed by the MPU 71 (for example, LE208 manufactured by LEETEC) at the rising edge of the reset signal (when the low level state is changed to the high level state).
0A-PA), and generally determines whether the clear signal is valid or invalid, performs the processing when the power is turned on, initializes the RAM, and restores the state when the power is turned off. To do.

This power-on process is activated by starting the system from 0000H after performing a security check after the system reset occurs due to the rise of the reset signal. In this power-on process, first, 8000H is set in the stack pointer (S10
0), then the interrupt mode for setting maskable interrupts is set (S110), and then the CPU built-in RAM (M
Access to the RAM provided in the PU 71 is permitted (S12
0), then MPU71 (eg LE2 manufactured by LEE Tech)
The watchdog timer of the watchdog timer with a built-in 080A-PA is initialized (S130). Incidentally, S
In the maskable interrupt setting of 110, the CTC interrupt is set and the maskable interrupt is generated every 2 ms. As a result, the timer I at the predetermined address described later
The NT processing is started every 2 ms. The non-maskable interrupt is generated when the power failure signal is input to the NMI terminal 153, and the power failure detection processing at a predetermined address described later is activated.

When setting the watchdog timer, the WDT
By setting a predetermined value (for example, 87H) in the mode register, the user reset is generated when the restart cannot be performed within the set timeout time.
When this user reset occurs, the processing will be 0000H.
Move to. That is, the power-on process of FIG. 12 is started.

After setting the watchdog timer (S13
0), then check the main clear signal (S14
0), OFF, that is, if the clear signal is valid, R
When it is determined that the user wants to clear the AM, the process proceeds to the process of clearing all the RAM (S180).

Also, the main clear signal is checked (S14
If it is determined in step 0) that the power supply is not OFF, that is, if the clear signal is invalid, the power-off occurrence information is checked next (S150). If not normal, that is, the power-off occurrence information is stored in the RAM. If is not set, it is determined that the power is turned on, and a process of clearing all the RAM (S18)
0).

By checking the information on the occurrence of power failure (S1
50), if it is determined to be normal, then RAM
Checksum is calculated (S160), and it is checked whether it is normal (S170). If not normal, it means that the power is restored, but the contents of RAM are not completely protected, and a part of A process of clearing all the RAM after judging that the RAM cannot be returned to the state when the power was cut off (S1)
80).

If the checksum of the RAM is also normal, it is determined that the power-off state can be restored, and the power-off processing (S220 to S300) described below is executed. When it is determined in S140 to S170 that the process of clearing all the RAMs (S180) needs to be performed, an initial value is set in the RAM (S190) after executing the clearing process, and then CPC is set to 2 ms. After setting the CPU peripheral device such as setting the interval timer of the cycle and setting the interrupt vector address for using interrupt mode 2 (S200), and setting the interrupt permission to use the maskable interrupt (S210) ,
The processing shifts from the power-on processing of FIG. 12 to the game start processing shown in FIG.

That is, when it is not possible to return to the state at the time of power-off, or when it is not necessary to return it, R
Only processing such as AM initialization is performed, and the game is started from the completely initialized state. On the other hand, if it is possible or necessary to perform the process of returning to the state at the time of power-off, first the stack pointer at power-off is restored (S220), and then the command to the prize ball control board 3 is issued. The process of returning the state to the state at the time of power-off, that is, the process of returning the ports of the output data and the control signal to the state at the time of power-off (S2
30), and then the pattern control board 7 and the voice control board 9
Then, a process for creating a command for power-off recovery for recovering the lamp control board 11 and transmitting the command is performed (S240).

As a result, as shown in the timing chart for explaining the state of confirming the return of the main board 1 by the prize ball control board 3 of FIG. 24, the transmission data output to the port of the main board 1 is, for example, immediately before a power failure. Time point TZ1 is "05H"
If it is, it becomes "00H" at the time point TZ2 when the power is backed up. Also, at this time TZ2
Then, it is stored in the built-in RAM that "05H" was output to the port.

In this state, when the power is turned on again at the time point TZ3, the main board 1 sets the port to "05H" as shown at the time point TZ4. The state of this port is referred to by the prize ball control board 3 as will be described later with reference to FIG.
It is used to confirm that the recovery of the main board 1 from the power failure due to is completed.

Returning to FIG. 12, the ordinary electric accessory and the first-class special electric accessory are then returned to the state when the power supply was cut off (S25).
0), the power-off occurrence information that stores that the power has been turned off is cleared (S260). By clearing the power-off occurrence information, the record of information related to power-off is deleted.

After the power-off occurrence information is cleared, the CPU peripheral device is initialized almost in the same manner as the processing of S200 described above (S270), and then the CPU register is restored by the restored stack pointer. (S28
0) Check the interrupt enable / disable state at power-off (S290). If the interrupt is enabled at power-off, enable the interrupt (S300). In this case, the processing is directly transferred to the address when the power is cut off.

As a result, the state of the gaming machine 5 is returned to the state when the power was cut off, and the subsequent processing when the power was cut off is executed. By the power-on process of FIG. 12 described above, when it is possible to return to the state at the time of power off, or when it is necessary to return to the state, the state of the gaming machine 5 is up to the state at the time of power off When it is returned and the continuation is executed, on the other hand, it is not possible to return to the state at the time of power off, or when it is not requested to return, the execution of the game is started from the initialized state.

Next, the game start processing will be described with reference to FIG. When the process shifts to the game start process of FIG. 13,
First, the built-in watchdog timer built into the CPU of the MPU 71 is cleared (S400), and the input switch (input S
W) 16, supply ball shortage switch (supply ball shortage SW) 2
3. The detection information from the OFF state to the ON state of the switch such as the lower pan full switch (lower pan full SW) 25 is stored (S
410), the created command is transmitted (S42).
0).

Next, as shown below, when the states of the lower tray, the supply balls, and the number of prize balls change, a process of creating an abnormality detection lamp designation command and an abnormality cancellation lamp designation command according to the changed state is executed. Do (S430-S
460). Specifically, "Lower saucer full, supply ball shortage,
If the state is neither "excessive or insufficient in number of prize balls" to "any state of lower pan full, supply ball shortage, excess or insufficient number of prize balls" (S430), an abnormality detection lamp designation command is created ( S440).

[0174] Further, the state of "the lower tray is full, the supply ball is insufficient, the number of prize balls is exceeded or insufficient" is changed to "the state where neither the lower tray is full, the supply ball is insufficient, the number of prize balls is exceeded, or is insufficient". After that (S450), an abnormality cancellation lamp designation command is created (S460). By the processes of S430 to S460, it is possible to notify that the lower tray is full, the supply balls are insufficient, the number of prize balls is excessive and insufficient.

Next, based on the state of the input switch (input SW) 16, the number of prizes is counted for each number of prize balls (S47).
0), as shown below, when the state of the lower tray full, the supply ball shortage changes, create a payout operation designation command and a payout stop designation command according to the changed state, and the normal symbol operation shown in FIG. A process of shifting to the process is performed (S480 to S510).

More specifically, if the state is changed from "the lower tray is not full or the supply balls are insufficient" to "the lower tray is full or the supply balls are insufficient" (S480), a payout stop designation command is created ( S490), it moves to the normal symbol operation processing shown in FIG. In addition, in the case where the state is changed from "the state where the lower tray is full or the supply balls are insufficient" to "the state where neither the lower tray is full nor the supply balls are insufficient" (S500), a payout operation designation command is created (S510), and then FIG. It moves to the normal symbol operation processing shown.

By the processing of S480 to S510, whether the payout is possible or not is performed based on the full lower tray and the shortage of supply balls. Next, check the number of prizes, "0"
If not (S520), a command for designating the number of prize balls corresponding to the number of prize balls is created (S530), and the number of winning prizes is "1".
After the subtraction (S540), the process of shifting to the normal symbol operation process shown in FIG. 14 is performed. If the number of winnings is "0" (S520), the process proceeds to the normal symbol operation process shown in FIG. 14 as it is. As a result, when the payable condition is satisfied, a command for designating the number of prize balls corresponding to the number of prize balls is created.

Next, the normal symbol operation process will be described with reference to FIG. When the process shifts to the normal symbol operation process of FIG. 14, first, it is determined whether the normal symbol operation gate switch detects passage (S600), and when the passage is detected, the normal symbol operation holding number is "4". If not (S61
0), after adding "1" to the number of ordinary symbol operation suspensions (S6
20), a process for storing a random number for determining a normal symbol is performed (S630). In addition, after the processing of S630, or when the passage is not sensed (S600), or when the normal symbol operation pending number is "4" (S610), then it is determined whether the fluctuation of the normal symbol is waiting. By doing so (S640), it is determined whether to shift to the standby state or the changing state. When the determination in the standby state is established, after the transition setting (S650 to S700), the process proceeds to the normal electric auditors product operation process of FIG. Perform processing.

The specific contents of the shift setting (S650 to S700) are as follows. First, it is judged whether the number of ordinary symbol operation suspension is "0" (S650). If "0", the ordinary electric accessory operation of FIG. If the process shifts to "0", then the normal symbol operation holding ball number is subtracted by "1" (S660), the hit determination is made, and after storing the result (S670), the stop symbol, the variation pattern. Is set (S680), a variation pattern standard designation command is created (S690), the state is switched to the changing state (S700), and then the process of shifting to the ordinary electric auditors product operation process of FIG. 15 is performed.

If it is determined in S640 that the process is not in standby, it is determined whether the fluctuation time is to be monitored next or the process being determined is to be performed (S710 to S740). The specific contents of the fluctuation time monitoring (S710 to S740) are as follows: first, it is judged whether the fluctuation is occurring (S710). If the fluctuation is occurring, it is judged whether the fluctuation time has further elapsed (S720).
If the variable time has elapsed, an all symbol stop common command is created, and after switching to the fixed state, the process of shifting to the normal electric auditors product operation process of FIG. 15 is performed. As a result, the fluctuation of the normal symbol is stopped. On the other hand, if the variation time has not elapsed (S720), the process directly proceeds to the normal electric auditors product operation process of FIG.

Even during standby (S640), it is changing (S71).
If it is not 0), it is then determined whether the confirmation is in progress (S750). If the fixed time has passed, it is determined whether the fixed time has passed (S760). If the fixed time has passed,
The hit determination is performed (S770), and if the result is a hit (S780), after switching to the hitting state (S790),
A process of shifting to the normal electric auditors product operation process of FIG. 15 is performed.

Further, the process proceeds to the normal electric auditors product operation process of FIG. 15 as it is until the fixed time elapses (S760) even if the decision is not being made (S750). On the other hand, if it is not determined that the hit is (S78
0), after switching to the standby state (S800), a process of shifting to the ordinary electric auditors product operation process of FIG. 15 is performed.

As a result, it is possible to normally provide a winning symbol. Next, the normal electric auditors product operation processing will be described with reference to FIG. When the process shifts to the normal electric auditors product operation process of FIG. 15, it is first determined whether or not the hit is in progress (S900),
If this judgment is not a hit, the process proceeds to the special symbol operation process shown in FIG. 16 as it is, and if it is a hit, it is judged whether or not the normal electric auditors product operation is started (S910), and the judgment is the normal electric auditors hand. In the case where the object operation is started, a process of shifting to the special symbol operation process shown in FIG. 16 is performed after switching to the normal electric accessory operation.

On the other hand, if it is determined in S910 that the operation of the ordinary electric accessory is not started, it is further determined whether the ordinary electric accessory is in operation (S930). The special symbol operation process shown in is performed. If it is in operation, the number of winning prizes for the normal electric auditors is counted next (S940), it is judged whether the count is "7" (S950), and if it has not reached "7" yet. , See if the maximum operating time has elapsed (S
960), if the maximum operation time has elapsed, or if the number of winning prizes for normal electric auditors has already reached "7", after switching to standby, shift to the special symbol operation process shown in FIG. Perform processing to Further, the count does not reach "7", and until the maximum operation time elapses, the process of shifting to the special symbol operation process shown in FIG. 16 is performed.

Thus, in the case of winning, the ordinary electric accessory can be operated until the number of winnings reaches "7" or the maximum operation time elapses. Next, based on FIG. 16, the special symbol operation process will be described. When the process shifts to the special symbol operation process of FIG. 16, first, the winning of the first type starting opening switch is sensed (S1000), and when the winning is sensed, the special symbol operation holding number is "4". Whether or not it is determined (S1010) and "4" has not been reached, the special symbol operation holding ball number is incremented by "1" (S1020), and processing for storing the special symbol big hit determination random number is performed (S103).
0).

After the processing of S1030, and when the winning of the first type starting opening switch is not sensed (S1000),
If the number of special symbol operation holding balls is "4" (S1010), the process then shifts to a determination as to whether it is in a waiting state or a customer waiting demonstration (S1040), and is waiting or a customer waiting demo. If it is in the middle, it is further determined whether the special symbol operation holding sphere number is other than "0" (S1050), and if the special symbol holding sphere number is "0", a certain time has elapsed from the standby state. It is determined whether or not (S1060), and if a certain period of time has elapsed since the standby, a process for switching to the customer waiting demonstration is performed (S1070). As a result, when there is no prize in the first-class starting opening switch, the process of waiting and then the customer waiting demonstration is performed.

After the processing for switching to the customer waiting demonstration is performed in S1070, or when a certain period of time has not passed since the standby (S1060), the process shown in FIG.
Processing for shifting to the first type special electric auditors product operation processing is performed.
In S1050, if the special symbol holding ball number is not "0", then the special symbol operation holding ball number is "1"
Subtract (S1080), perform a big hit determination, store the result (S1090), then set a stop symbol and variation pattern (S1100), create a variation pattern special designation command (S1110), and are changing. (S1120), the process proceeds to the first type special electric auditors product operation process of FIG. Thereby, the variation pattern of the special symbol is commanded.

If it is determined in S1040 that neither the standby nor the customer waiting demonstration is in progress, it is further determined whether or not it is fluctuating (S1130), and if it is fluctuating, it is determined whether or not the fluctuating time has elapsed. (S1140), if the variable time has elapsed, after creating the all symbol stop special designation command (S115
0), switching during confirmation (S1160), and processing for shifting to the first type special electric auditors product operation processing of FIG. 17 is performed. As a result, a command to stop the symbol is issued when the variable time has elapsed.

[0189] Even during the waiting and customer waiting demonstration (S104
0) If it is determined that it is not changing (S1130), then it is determined whether it is finalizing (S1170), and if it is finalizing, it is determined whether a fixed time has elapsed (S118).
0) If it is determined that a certain period of time has passed during determination, a big hit determination is made next (S1190). If the result of this determination is a big hit (S1200), the state is set to the low-probability state. (S1210), the process is switched to the big hit (S1220), and the process of shifting to the first-class special electric auditors product operation process of FIG. 17 is performed. As a result, the jackpot is determined, and the jackpot in the low-probability state is set.

In addition, it is neither in the standby state nor in the customer waiting demonstration (S1040), in the fluctuation (S1130), in the confirmation (S1170), or in the confirmation.
If a certain period of time has not passed yet, the process shown in FIG.
Processing for shifting to the first type special electric auditors product operation processing of No. 7 is performed.

On the other hand, if the jackpot determination result is out of position (S1200), it is determined whether the probability is higher (S123).
0) If the probability is not high, then the number of state transitions is decremented by "1" (S1240), and as a result, the number of state transitions is "0".
(S1250), if it becomes "0", the state is set to the low probability state (S1260), and the low probability state lamp designation command is created (S127).
0), after the creation of the probability variation end designation command (S128
0), switching to the standby state (S1290), and processing for shifting to the first-class special electric auditors product operation processing of FIG. 17 is performed. As a result, the low probability state is displayed.

If it is out (S1200) and is in the high probability state (S1230), or if the state is not in the high probability and the number of state transitions is not "0", the process for switching to the waiting state is executed. Go (S1290), first in FIG.
Processing for shifting to the seed special electric auditors product operation processing is performed.

Next, the first type special electric auditors product operation processing will be described with reference to FIG. When the process shifts to the first-class special electric auditors product operation process of FIG. 17, first, it is determined whether or not a big hit is in progress (S1300), and if it is a big hit, it is further determined whether or not a big hit operation is started (S1310). If it is determined that the operation is started, after switching to the first interval screen display (S1320), the process of shifting to the game start process described in FIG. 13 is performed.

If it is not a big hit (S1300),
As it is, the processing for shifting to the game start processing described in FIG. 13 is performed. On the other hand, if the big hit (S1300) and the big hit operation is not started (S1310), it is further determined whether the first interval screen is being displayed (S1330). If the first interval screen is being displayed, the display time has elapsed. It is determined whether or not (S1340), and if it has elapsed, after performing the process of switching to the special winning opening opening (S1350),
Processing for shifting to the game start processing described in FIG. 13 is performed.

While the first interval screen is being displayed (S
1330), and until the display time elapses, the process of directly shifting to the game start process described in FIG. 13 is performed.
On the other hand, if the initial interval screen is not being displayed (S13
30) and further judge whether the special winning opening is open (S1
360), if the special winning opening is open, it is determined whether it is the final round (S1370), and processing for storing the detection result of passing through the specific area (S1380) is performed until the final round is reached. A process for counting the number of winning holes is performed (S1390).

Next, it is judged whether or not the number of big winning awards has reached 10 (S1400). If the number has not yet reached 10, it is further judged whether or not the maximum opening time has elapsed (S14).
10) If the maximum opening time has not elapsed, the process for directly shifting to the game start process described in FIG. 13 is performed.

Further, when the number of winning a prize holes becomes "10" (S1400) or when the maximum opening time has elapsed (S1410), after switching to the closing of the winning a prize holes (S).
1420), processing for shifting to the game start processing described in FIG. 13 is performed. As a result, detection of passage of a specific area and control of opening of the special winning opening are performed.

If the big hit (S1300), the first interval screen is not displayed (S1330), and the big winning opening is not open (S1360), it is determined whether the big winning opening is closed (S1430). ), If the special winning opening is closed, it is then determined whether it is the final round (S1440), and if it is not the final round, it is further determined whether the specific area effective time has elapsed (S1450). If the specific area effective time has not elapsed, the detection result of passage through the specific area is stored (S1460), it is then determined whether the closing time has elapsed (S1470), and if the closing time has elapsed, further identification is performed. It is determined whether the area is sensed (S148
0) If the specific area is not sensed, after switching to the end interval screen display (S1490), the process of shifting to the game start process described in FIG. 13 is performed.

Until the closing time elapses (S147
0), the process of directly shifting to the game start process described in FIG. 13 is performed, while the closing time has elapsed (S147).
0) and when the specific area is sensed (S148
0), after performing the process of switching during the special winning opening (S
1500), the process for shifting to the game start process described in FIG. 13 is performed.

If it is determined in S1440 that it is the last round, or if it is determined in S1450 that the specific area effective time has elapsed, the closing time elapses without executing the processing of storing the detection result of the specific area passage in S1460. The process shifts to the determination (S1470). As a result, whether or not to continue the big hit game is controlled depending on whether or not the specific area has passed.

If the big hit (S1300), the first interval screen is not displayed (S1330), and the special winning opening is not open (S1360), or the special winning opening is not closed (S1430), further end interval It is determined whether the screen is being displayed (S1510), and if the end interval screen is being displayed, it is determined whether the display time has elapsed (S1520). If the display time has elapsed, after switching to standby ( (S1530), processing for shifting to the game start processing described in FIG. 13 is performed.

In addition, during the big hit (S1300), the first interval screen is not displayed (S1330), the special winning opening is not open (S1360), the big winning opening is not closed (S1430), and the end interval screen is displayed. If not (S1510), or the end interval screen is being displayed (S1510), until the display time elapses (S1520), switch to standby (S1510).
1530) without performing the process, the process directly proceeds to the game start process described in FIG.

Next, the power-off process will be described with reference to FIG. When the power-off process of FIG. 18 is started, first the CP
The U register is saved (S1600), and then it is determined whether power-off occurrence information is set (S161).
0), if it is already set, shift to the standby routine,
If the information about the occurrence of power failure has not been set, next,
The following processes are sequentially executed, and the process shifts to the standby routine to wait until the power supply is cut off.

That is, first, the stack pointer is stored (S1620), then the first-class special electric accessory is closed and the normal electric accessory is reduced (S1630), and then the prize ball counting back side switch and the prize. Sphere counting front switch 70m
It monitors for s (S1640), stores the information on the occurrence of power failure (S1650), calculates and stores the checksum of RAM (S1660), and sequentially prohibits access to RAM with built-in CPU (S1670).

As a result, when the AC24V power failure occurs, the state at the time of the power failure can be stored and saved, and when the power is supplied again, the state at the time of the power failure can be restored. FIG. 19 is a flowchart of a power-on process routine executed by the prize ball control board 3 when the power is turned on. This power-on process routine is performed by the MPU 83 (for example, LE208 manufactured by LEETEC) at the rising edge of the reset signal (when the low level state is changed to the high level state).
0A-PA), and generally determines whether the clear signal is valid or invalid, performs the processing when the power is turned on, initializes the RAM, and restores the state when the power is turned off. To do.

This power-on process is started by the system reset caused by the rising edge of the reset signal, a security check, and the process starting from 0000H. In this power-on process, first, 8000H is set in the stack pointer (S20
00), and then the interrupt mode for setting maskable interrupt (S2010)
Allows access to (RAM of MPU83) (S
2020), and then the CTC is set as an interval timer of 1 ms cycle, the interrupt vector address is set for using the interrupt mode 2, and the PIO is set as an input port, and the CPU peripheral device is initialized (S2030).

In S2010 to S2030, the CTC interrupt is set by the maskable interrupt setting and 1 m
A maskable interrupt is generated every s. As a result, the timer INT process at the predetermined address is activated every 1 ms. The non-maskable interrupt is NM
It occurs when a power failure signal is input to the I terminal 175,
A power failure detection process at a predetermined address, which will be described later, is activated.

Next, the prize-clear signal is checked (S2
040), OFF, that is, if the clear signal is valid, it is determined that the RAM is desired to be cleared, and the process proceeds to the process of clearing all the RAM (S2080). If it is determined in the prize-clear signal check (S2040) that it is not OFF, that is, if the clear signal is invalid, the power-off occurrence information is checked next (S205).
0), if it is not normal, that is, if the power-off occurrence information is not set in the RAM, it is determined that the power is on,
The process moves to the process of clearing all the RAM (S2080).

[0209] By checking the information about the occurrence of power failure (S2
050), if it is determined to be normal, then RA
The checksum of M is calculated (S2060), and it is checked whether it is normal (S2070). If it is not normal, it means that the power is restored, but the contents of RAM are not completely protected. Is destroyed and it cannot be returned to the state when the power was cut off, and the process proceeds to the process of clearing all the RAM (S2080).

If the checksum of the RAM is also normal, it is judged that the power-off state can be restored, and the power-off processing (S2100 to S2160) described later is executed. When it is determined in S2040 to S2070 that the process of clearing all the RAMs (S2080) needs to be performed, after executing the clearing process, the interrupt permission is set to use the maskable interrupt (S209).
0), the processing shifts to the payout control start in FIG.

That is, if it is not possible to return to the state at the time of power-off, or if it is not necessary to return it, R
Only the processing such as AM initialization is performed, and the payout control is started from the completely initialized state. On the other hand, if it is possible or necessary to perform the process of returning to the power-off state, the stack pointer at power-off is first restored (S2100), and then the payout stop state is set (S2110). ), The power-off occurrence information is cleared (S2120), it is determined whether the state of the port (84H) is the same as the state stored when the power was turned off (S2130), and the state of the port (84H) is the same as when the power was turned off. Wait until

That is, as shown in FIG. 24, the main substrate 1
Returns to the state of the port immediately before the power failure at time TZ4 and sets the transmission data to "05H", for example. The port of the prize ball control board 3 is the same as the port (84H) that was input and stored in the power-off process which will be described later with reference to FIG. For example, it is determined that the state of the port (84H) is the same as the state stored when the power was cut off. Then, the process proceeds to the next process.

Further, in contrast to the state of the stored port (84H), if they are not the same, the standby state of S2130 is continued. In this case, if the built-in watchdog timer has the enable timeout time set to "1425 ms" as shown in Table 4, for example, a user reset will occur when the enable timeout time has elapsed.

[0214] Also, in the restart in this case, FD02
For example, "55H" is written in the WDT clear register at the address H.
The control words are written in the order of “AAH” and “33H”, the watchdog timer is cleared and restarted. That is, when there is a problem in either the main board 1 or the prize ball control board 3 when returning from a power failure, and a mismatch occurs between the main board 1 and the prize ball control board 3, the watchdog timer By the action of, the prize ball control board 3 is reset and processed according to the command from the main board 1.

[0215]

[Table 4]

There is no inconsistency between the main board 1 and the prize ball control board 3, and the main board 1 and the prize ball control board 3 are normally functioning together when the power failure is recovered from the power failure. Then, when the port returns to the power-off state, the CPU registers are restored using the stack pointer that was restored next (S2140), and the interrupt enable / disable state at power-off is checked (S2150). If the interrupt is enabled, the interrupt is enabled (S2160), and if the interrupt is disabled when the power is turned off, the interrupt is allowed to continue.
Transfer the processing to the address when the power was cut off.

As a result, the state of the prize ball control board 3 is returned to the state when the power is cut off, and the subsequent processing when the power is cut off is executed. By the power-on process of FIG. 19 described above, when it is possible or necessary to restore the power-off state, the state of the prize ball control board 3 is the power-off state at that time. If it is not possible to return to the state when the power was cut off, or if it is not requested to return, the game is restarted from the initialized state. Is started.

Next, the payout control start processing will be described with reference to FIG. When the processing shifts to the payout control start processing of FIG. 20, first, the built-in watchdog timer built in the CPU of the MPU 83 is cleared (S2200), the command transmitted from the main board 1 is acquired, and in response to this command. The payout / stop state or the total number of game balls for winning prize balls is stored (S2210).

Next, it is judged whether or not the prepaid card unit is connected (S2220), and if the prepaid card unit is connected, the firing control signal is turned off.
By setting the level to (low level), processing for permitting firing is performed (S2230). If the prepaid card unit is not connected, the firing control signal is turned on (high level) to stop the firing (S2).
240).

As a result, the gaming machine 5 to which the prepaid card unit is not connected cannot launch the game ball. Next, the payout operation / stop state is determined (S22
50) If it is in the payout operation state, it is further determined whether or not a ball lending signal is received from the prepaid card unit (S2260). If a ball lending signal is received, a ball lending control process described later in FIG. 21 is performed. Perform processing to transfer control to.

As a result, balls are lent by the prepaid card unit. When payout is stopped (S225
0), and when the ball lending signal is not received from the prepaid card unit (S2260), it is further determined whether or not the total number of game balls acquired is "0" (S2280), and "0".
If not, processing for shifting the control to prize ball control processing described later in FIG. 22 is performed.

As a result, the prize balls are paid out.
When the payout is stopped (S2250) or the total number of acquired game balls is "0", the following error display processing is sequentially executed (S2290 to S2390). That is, first, it is determined whether the prepaid card unit is not connected (S2290), the ball lending counting switch is abnormal (S2300), the prize ball counting switch is abnormal (S2310), and the prize ball motor is abnormal (S2320). Then, it is sequentially judged whether or not the payout is stopped (S2330), and if all are denied, "0" display processing indicating that there is no abnormality in the error display LED of the status display 46 is performed (S2340).

If it is determined that the prepaid card unit has an abnormality due to non-connection (S2290), "5" is displayed on the error display LED of the status indicator 46 (S2350). When it is determined that the ball lending counting switch is abnormal (S2300), the error display L of the status display 46 is displayed.
Display processing of "4" is performed on the ED (S2360).

When it is determined that the prize ball counting switch is abnormal (S2310), "3" is displayed on the error display LED of the status display 46 (S2370). When it is determined that the prize ball motor is abnormal (S2320), "2" is displayed on the error display LED of the status display 46 (S238).
0).

When it is determined that the payout is stopped (S
2330), "1" is displayed on the error display LED of the status display 46 (S2380). After executing the error display process (S2290 to S2390), the process returns to the beginning of the payout control start process of FIG. 20 and is repeatedly executed.

As a result, the error display is changed to the status display 46.
Can be done. FIG. 21 is a flowchart of the ball lending control process. When the ball lending control process of FIG. 21 is started, first, a process of storing detection information from OFF to ON of the switches of the lending balls SW1, SW2 (31, 32) and the like is performed (S2400), and the prize ball motor 37. Is driven to the lending sphere side (S2410), and the number of lent balls is counted (S242
0), and the subsequent processes from S2400 are repeated until the number of lent balls reaches “25” (S2430).

If the prize ball motor 37 is continuously driven toward the lending ball, the prize ball motor 37 is heated, and the following cooling operation is performed. The cooling operation will be described based on the explanatory view of the cooling operation shown in FIG. The prize ball motor 37 is
For example, in the case of paying out one game ball YK by the first sprocket 622, driving in the arrow range shown in FIG. 28 is performed.

When driving in the range shown below,
The first sprocket 622 is rotated for 24 ms from the initial position to the position. Then, at the position of, the rotation is stopped for 12 ms. During this time, the cooling time is reached. Next, it takes 24 ms to rotate from the position to the position.

When the gaming balls YK are continuously paid out by the first sprocket 622, the rotation is stopped for 12 ms at the position. By this control, driving in the arrow range of is required for 60 ms, and it takes 72 ms for paying out one game ball YK. Since the sprocket unit 614 is a two-stage type, it is possible to pay out two game balls YK per 72 ms.

By repeating the above steps 1 to 3, continuous operation while cooling is performed. In this way, the prize ball motor 37
When the number of rented balls reaches "25" while continuously operating
Processing for shifting to the payout control start processing described in FIG. 20 is performed. As a result, the ball lending is actually executed.

FIG. 22 is a flowchart of the prize ball control processing. When the prize ball control process of FIG. 22 is started, first, the switches of the prize balls SW1 and SW2 (33, 34) are turned off.
Processing for storing the detection information from ON to ON (S25
00), and drives the prize ball motor 37 to the prize ball side (S251
0), the number of prize balls is counted (S2520), and the processes from S2500 onward are repeated until the number of prize balls reaches the total number of won game balls (S2530). The prize ball motor 37
Is continuously operated with the cooling time of 12 ms interposed therebetween as described above.

When the number of prize balls reaches the total number of game balls to be won, the process of shifting to the payout control start process described above with reference to FIG. 20 is performed. As a result, the prize balls are actually paid out.
In the payout control start processing of FIG. 20, S2300 to S2
Even if a failure or abnormality is detected at 330 or the like, the ball lending control process of FIG. 21 and the prize ball control process of FIG. 22 do not perform a process of stopping, interrupting, or stopping, and payout by a process not shown. A process of giving an interval of 3 seconds is performed. For example, in FIG. 21, S
If "NO" in 2430, a timer of 3 seconds is added, and after the lapse of 3 seconds, S2400 is executed.

Further, in FIG. 22, if "NO" in S2530, a timer of 3 seconds is added, and after the lapse of 3 seconds, S2500 is executed. By doing so, an interval of 3 seconds is taken every time one gaming ball is paid out, and fraud is added to the gaming machine 5, or an abnormality or failure occurs, and the prize ball control board Even if a command for paying out game balls is illegally input to 3, the game balls are paid out to the minimum, and it is possible to minimize unexpected payouts and illegal payouts.

Instead of adding an interval of 3 seconds, the rotation speed of the prize ball motor 37 may be slowed down. For example, in S2510 and S2410, the prize ball motor 37 is driven so that one payout is performed in 72 ms, but this may be performed in about 3000 ms. Note that 3000 ms is an example, and a similar action can be obtained if the time is about several seconds.

In this way, the payout of the prize balls output from the main board 1 is instructed by adopting a countermeasure against fraud by sandwiching the interval of 3 seconds or slowing the driving speed of the prize ball motor 37. Command is always executed, and the unpaid amount is stored, so it is possible to prevent omission of game balls and loss of information, and it is not a malfunction or abnormality, but it is erroneously judged to be abnormal By doing so, it is possible to prevent accidentally deleting the command or information for paying out the game balls, and prevent the player from being damaged.

Next, the power-off processing will be described with reference to FIG. When the power-off processing in FIG. 23 is started, the CPU registers are first saved (S2600), and then it is determined whether power-off occurrence information is set (S261).
0), if it is already set, shift to the standby routine,
If the information about the occurrence of power failure has not been set, next,
After storing the stack pointer (S2620), it is determined whether the prize ball motor is in the normal position (S263).
0), if not normal position, prize ball motor 37 to normal position
Is driven (S2640), and if it is already in the normal position, the prize ball motor 37 is left as it is, and then the prize ball counting back side switch and the prize ball counting front side switch (prize balls SW1, SW2 (3
Monitoring the passage of (1, 32)) (S2650),
The power-off processing in FIG. 23 is started by monitoring the passage of the ball lending counting back side switch and the ball lending counting front side switch (ball lending SW1, SW2 (33, 34)) (S2650). It is repeatedly executed until about 70 ms have passed since then (S2670). This prevents omission of detection of prize balls or ball lending paid out immediately before a power failure. Incidentally, S26
In the operation of driving the prize ball motor 37 to the normal position by 40, since it is not the continuous operation of continuously discharging the game balls, the operation including the cooling period of 12 ms is not performed, and the prize ball motor 37 is moved to the normal position. Operate continuously.

As a result, even if the driving in the arrow range shown in FIG. 28 is performed, the prize ball motor 37 is driven by 4 times.
Only drive for 8ms. Therefore, during normal operation, it took 60 ms to drive the range indicated by arrow, but at the time of power failure, it is sufficient to drive for a maximum of 48 ms. Therefore, by adopting the driving method omitting the cooling operation, the backup time can be shortened as compared with the case of adopting the driving method sandwiching the cooling operation, and as a result, the backup capacity of the power supply board 15 is reduced. Can be planned. That is, the cost of the device can be reduced and the device can be downsized.

After the payout of the prize balls or the ball lending is detected, the following processes are sequentially executed to shift to the standby routine to wait for the power supply to be cut off. That is, first the port (84
The state of (H) is stored (S2680), then the information on the occurrence of power failure is stored (S2690), the checksum of the RAM is calculated and stored (S2700), and the access prohibition of the RAM with built-in CPU is sequentially performed (S2710). .

As a result, when the AC 24V power failure occurs, after detecting the payout state, the power supply to + 5V and + 12V to the prize ball control board 3 is stopped, and the MPU 83 shifts to the stop state. . Built-in RAM
The stored contents are held by the backup power supply.

Until the MPU 83 shifts to the stop state and the power failure process of the MPU 83 is completed, the power supply of + 5V and + 12V by the power supply lines DGW5 and DGW12 is secured. After this, the power supply line DGW
5. Even after the power supply from the DGW 12 is cut off, the stored contents are retained for 20 hours or more by the backup power supply supplied from the backup power supply line BKW.

As described above, the prize ball control board 3 that has transitioned to the power failure state continues the processing from the position where the processing is interrupted when the reset signal output from the power supply board 15 is input to the RESET terminal 151 when the power is restored. To do. The main board 1, the prize ball control board 3, and the power board 15 of the gaming machine 5 described above output a power failure signal from the power board 15 when the power supply to the gaming machine 5 is stopped. RAM of main board 1
And the power supply line DGW until the contents stored in the RAM of the prize ball control board 3 are not changed and the state is stopped.
5, the power supply of + 5V and + 12V by the DGW 12 is maintained, and then the stored contents are held by the backup power supply.

As a result, the current status of the main board 1 of the gaming machine 5 and the prize ball control board 3 at the time of the power failure is preserved even during the power failure. As a result, after the power failure is restored, the power supply voltage returns to an appropriate value, and when the power supply board 15 supplies the reset signal to the main board 1 and the prize ball control board 3, the prize ball control board 3 is activated first. Then, after a delay of about 300 ms, the main board 1 is put into operation, and based on the stored contents of the RAM, the gaming machine 5
The main board 1 and the prize ball control board 3 are returned to the states before the occurrence of the power failure.

The symbol control board 7 which receives the reset signal from the power supply board 15 is based on the command received from the main board 1, and is a special symbol display device 47 and a normal symbol display device 4.
A predetermined symbol is displayed at 9 and. Here, in accordance with the received command, the special symbol display device 47 displays when the power is turned on, a customer waiting demonstration display, a game symbol display, a big hit symbol display, a V display, and a display of the number of times the special winning opening is opened. Big hit end display, prize ball number abnormality display, lower pan full abnormality display, supply shortage abnormality display, prize ball SW31
Display of disconnection / short-circuit abnormality, non-display of prize ball number abnormality, non-display of lower pan full abnormality, non-display of insufficient supply number abnormality, prize ball S
Non-display of disconnection / short-circuit abnormality of W31, display of power failure recovery are performed, and display at the time of power-on and variation pattern are normally displayed on the symbol display device 49.

The symbol control board 7 has a power supply line DGW5,
When the power supply of + 5V and + 12V is received by the DGW 12, and the power supply of AC24V to the gaming machine 5 is stopped, + 5V and + 12V are activated by spontaneous discharge as Low output. Stop.

When the supply of 24V AC power to the gaming machine 5 is resumed, the + 5V and + 12V power supplies are received again and the image is displayed again. The voice control board 9 which receives the reset signal from the power supply board 15, based on the command received from the main board 1, is silent, the voice corresponding to the variation pattern of the special symbol, the voice of the stop of the special symbol, the voice of the jackpot start, It outputs the sound of opening the special winning opening, the sound of the interval between opening the special winning openings, and the sound of ending the big hit.

The voice control board 9 which receives the reset signal from the power supply board 15 is supplied with power of + 5V and + 12V by the power supply lines DGW5 and DGW12, and the supply of AC24V to the gaming machine 5 is stopped. In this case, the + 5V and + 12V power supplies go low due to spontaneous discharge.
The operation is stopped as it becomes an output.

When the supply of 24V AC power to the gaming machine 5 is resumed, the + 5V and + 12V power supplies are received again, and the sound is output again. The lamp control board 11 which receives the reset signal from the power supply board 15 causes the electric decoration 53 such as an LED to be displayed on the basis of the command received from the main board 1.
Stand-by light pattern, light pattern corresponding to game pattern, light pattern corresponding to stop of special pattern, light pattern of big hit start, light pattern of big winning opening, big winning opening interval Illumination pattern, jackpot end illumination pattern, award ball number abnormal illumination pattern, award ball number return illumination pattern, special pattern hold LED light pattern, normal pattern hold LED light pattern, probability fluctuation Execute the illumination pattern of the lamp.

The lamp control board 11 is connected to the power supply line DGW.
5, when the power supply of + 5V and + 12V is received by the DGW 12, and when the power supply of AC24V to the gaming machine 5 is stopped, the + 5V and + 12V power supplies become low output due to spontaneous discharge. , Stop working.

When the supply of 24V AC power to the gaming machine 5 is resumed, the + 5V and + 12V power supplies are received again, and the illumination pattern is displayed again. The firing control board 13 that receives the reset signal from the power supply board 15 uses the power supply lines DGW5, DGW12, and DGW32 to set + 5V.
When the power supply of + 12V and + 32V is received and the power supply of AC24V to the gaming machine 5 is stopped,
L by natural discharge of + 5V, + 12V, + 32V power supply
The operation is stopped as the output becomes ow.

When the power supply of 24V AC to the gaming machine 5 is restarted, the + 5V, + 12V and + 32V power supplies are received and the firing control is started again. In addition, when the low of the power failure signal is input to the award ball control board 3, the award balls and the rental balls paid out at the same time as the award balls SW31, 32 and the ball rental SW33, 3,
It takes about 70 ms at maximum to pass 4, but it is not limited to this, and depending on the payout mechanism of the prize ball payout device (not shown), the mounting position of the switch, etc.
It may be appropriately changed within a range that does not hinder other processing.

Further, the timing charts of the start and stop of the power supply board 15 shown in FIGS. 8 to 10, the timing chart at the time of power failure, the time described in the description of the timing chart of each control board state, etc. are the same for each gaming machine. It may be appropriately changed according to the processing capacity. The delay / waveform shaping unit 43 shown in FIG.
In 5, the delay process is adjusted by the discharge time of the capacitor C8, but instead of this, a circuit that performs the delay process by the charge time of the capacitor may be used. In this case, a circuit is added to shorten the discharging time compared to the charging time of the capacitor.

Next, the process of generating the special symbol big hit determination random number stored in the process of S1030 described above will be described. The special symbol big hit determination random number is obtained from an initial value update type random number processing routine (not shown) that is repeatedly executed by the MPU 71 of the main board 1 when the first type starting opening SW senses a winning. The value of this special symbol big hit determination random number, it is determined whether or not a big hit.

In this initial value updating type random number processing routine,
An integer counter in the range of 0 to a predetermined maximum value is used, and the value of the integer counter is incremented every predetermined time. Further, the initial value at the start of incrementing is changed at each start of counting. Therefore, different initial values are used each time the count is started.

Since the initial value update type random number processing routine for setting the initial value at the start of counting is executed by the MPU 71, the R of the MPU 71 is executed by the processing of S180 described above.
When AM is cleared or initialized, it starts from the initial state. Therefore, every time the RAM of the MPU 71 is cleared or initialized, the integer counter starts counting from "0". This is the same even if the RAM clear is intentionally executed from the outside. Therefore, as it is,
By intentionally causing the RAM to be cleared, it is possible to carry out a fraudulent act that causes a big hit.

[0255] Therefore, a structure for eliminating such a room for fraudulent activity or for facilitating detection of fraudulent activity is shown below.

[0256]

[Table 5]

(1) When the RAM of the main board 1 is cleared, for example, when the processing of S180 is executed, the measures shown in Table 5 are taken. That is, from the main board 1 to the voice control board 9,
A RAM clear notification command (not shown) is transmitted to the lamp control board 11 (S420) to make the notification. For example, when the voice control board 9 receives the RAM clear notification command, the voice control board 9 executes a sound indicating RAM clear or an announcement (RAM clear notification sound) on the speaker 51 for 30 seconds to 1 minute, and then performs normal operation. Return to the playing state. Similarly, when the lamp control board 11 receives the RAM clear notification command, the lamp control board 11 displays the RA
After the electric decoration pattern (controlling blinking of a specific decoration lamp) for displaying M clear is executed for 30 seconds to 1 minute, the normal game state is restored.

Incidentally, when another command is received from the main board 1 while the speaker 51 is informing the sound indicating the RAM clear or the announcement, the following action is taken. When the sound indicating the RAM clear by the RAM clear informing command or another command of the content that the announcement is erased is received, the sound indicating the RAM clear or the announcement is prioritized and the other commands are invalidated.

RA by RAM clear notification command
If a sound indicating M clear, or a content that does not affect the announcement, for example, a sound indicating RAM clear, or another command of a content that is not erased while the execution of the announcement is continued is received, the other received command Execute the contents corresponding to.

Alternatively, when the same RAM clear notifying command is received again while the sound or announcement indicating the RAM clearing by the RAM clear notifying command is being executed, from the time the new RAM clear notifying command is received. , A sound indicating a new RAM clear or an announcement is executed.

Further, while the illumination pattern for displaying RAM clear is being executed on the illumination 53 for 30 seconds to 1 minute,
When another command is received from the main board 1, it responds as follows. R by RAM clear notification command
When another command having the content of erasing the electric decoration pattern indicating AM clear is received, the display of the electric decoration pattern indicating RAM clear is prioritized and the other commands are invalidated.

Further, the contents which do not affect the electric decoration pattern by the RAM clear notification command, for example, the display of the electric decoration pattern indicating the RAM clear such as the memory number display command is continued and another command whose contents are not erased is received. If so, the contents corresponding to the other received command are executed.

Alternatively, when the same RAM clear notifying command is received again while the electric decoration pattern display indicating the RAM clearing by the RAM clear notifying command is being executed, from the time when the new RAM clear notifying command is received. , Display of an electric decoration pattern indicating a new RAM clear is executed.

(2) When the RAM of the main board 1 is cleared, for example, when the process of S180 is executed, as shown in FIG. 29, a RAM clear information signal is sent to a board external terminal board (not shown) for a certain period (about 100 m). Second) ON output to notify the hall computer that the RAM has been cleared.

(3) Since the initial value is initialized to "0" when the RAM is cleared, it is possible to prevent the special symbol big hit determination random number from being easily hit from the outside of the main board 1. Take the following techniques. When the RAM is initialized, the initial value update type random number processing routine or the initial value is not initialized.

As a result, the initial value does not start from "0" when the RAM is cleared, and it cannot be guessed from the outside. The initial value of the integer counter of the initial value update type random number processing routine is stored in a non-volatile memory provided outside the MPU 71, and when the RAM is cleared or initialized, the initial value is stored in the non-volatile memory. Make something.

A high-speed counter that operates independently of the MPU 71 is provided outside the MPU 71, and when the RAM is cleared or initialized, the initial value is determined based on the value of the external high-speed counter. MP the integer counter of the initial value update type random number processing routine
It is not provided in the RAM of U71, but is provided in a register of MPU71, for example, an IX register in the case of a microchip based on Z80 manufactured by Zilog. In this case, the IX register or the like used for the integer counter is prohibited from being used for other purposes.

Signals for clearing and initializing the RAM such as a power failure signal and a reset signal are generated inside the main board 1. This makes it difficult to illegally clear the RAM from the outside. Next, the correspondence between the configurations of the claims and the embodiments of the invention will be described.

The description of the subordinate parts is omitted. The gaming machine according to claim 1, the gaming machine 5, the main control means, the main board 1, the sub-control means, the prize ball control board 3, the operation start means, the reset signal generation circuit 125, the delay means,
The directional charge / discharge circuit 455 corresponds to the delay / waveform shaping unit 435 (in particular, the delay circuit unit 457) and the delay circuit reset unit.

In order to perform the delay processing according to the discharge time for discharging the capacitor of the second aspect with the predetermined discharge characteristic, the capacitor is the capacitor C8, and the charging characteristic of the capacitor C8 is the resistance of the resistor R7 and the capacitor C8. The function of the time constant and the discharge characteristic correspond to the function of the time constant of the resistor R8 and the capacitor C8.

The claim 3 is the same as the claim 2. A fifth aspect of the present invention is the resistance R8 (390 of the discharge circuit of the capacitor C8)
kΩ), the resistance R7 (1
This corresponds to the fact that kΩ) is smaller.

Claims 4 and 6 correspond to the preceding Shosho. The main control means of claim 7 is the main board 1, the sub-control means is the prize ball control board 3, and the power supply means is the power supply board 1.
5. The power failure signal creation circuit 123 corresponds to the voltage drop detection means and the voltage drop signal output means. Blackout signal creation circuit 12
3, the voltage drop detecting means corresponds to the function of the power failure signal / reset signal generating unit 305 centering on the reset IC (341) and the power supply monitoring IC (347). The voltage drop signal output means is a reset IC 341.
And a circuit centered on the output buffer unit 307 correspond to each other.

The operation starting means of claim 8 is the power supply board 15
The reset signal generation circuit 125 of 1 corresponds. More specifically, the reset signal generating circuit 125 corresponds to the function of the power failure signal / reset signal generating unit 305. The noise filter function of claim 9 is the Schmitt inverter 451,
The low-pass binarization filter configuration of 453, resistor R8, and capacitor C8 corresponds.

A main backup storage means of claim 10 is
It corresponds to the backup RAM of the MPU 71. The main control state restoring means is realized by the MPU 71 and a program built in the MPU 71.
The contents performed by the processes of 0 to S300 correspond.

According to the eleventh aspect of the sub backup storage means,
The backup RAM of the MPU 83 corresponds. The processing of S2130 corresponds to the means for determining whether or not the power supply has dropped. The signal input state backup storage means according to claim 12 is S2.
The processing of 680 corresponds to the backup RAM of the MPU 83. When the power supply is low, the signal input state recovery judgment means is S
The determination of YES in 2130 corresponds.

The signal input state backup storage means of claim 13 corresponds to the process of S2680 and the backup RAM of the MPU 83. The input return standby means is S213.
The process of 0 corresponds. Claim 14 corresponds to the watchdog timer incorporated in the MPU 83 that monitors the processing of S2130.

The fifteenth aspect corresponds to the watchdog timer incorporated in the MPU 83 that monitors the processing of S2130, and the function of user reset when the watchdog timer times out.

[Brief description of drawings]

FIG. 1 is a block regarding an interface between a main board 1, a prize ball control board 3, a symbol control board 7, a voice control board 9, a lamp control board 11, a launch control board 13, and a power supply board 15. It is a figure.

FIG. 2 is a block diagram of an electric control system of the gaming machine 5.

FIG. 3 is a clear SW 121 of the power supply board 15, a power failure signal generation circuit 123, a reset signal generation circuit 125,
Backup power supply circuit 1 for main board and prize ball control board
27, + 5V, + 12V power generation circuit 131, +2
This is a circuit configuration that provides a 4V, + 32V power supply generation circuit 133.

FIG. 4 is a clear SW 121 of the power supply board 15, a power failure signal generation circuit 123, a reset signal generation circuit 125,
Backup power supply circuit 1 for main board and prize ball control board
27, + 5V, + 12V power generation circuit 131, +2
This is a circuit configuration that provides a 4V, + 32V power supply generation circuit 133.

FIG. 5 is a configuration for inputting data to the MPU 71.

FIG. 6 is a configuration for outputting data from the MPU 71.

7A is a circuit diagram of the delay / waveform shaping unit 435, and FIG. 7B is a detailed circuit diagram of the delay circuit unit 457.

FIG. 8 is a timing chart of starting and stopping the power supply board 15.

FIG. 9 is a timing chart of starting and stopping the power supply board 15.

FIG. 10 is a timing chart of starting and stopping of the power supply board 15, which is a state of each control board in a series of operations.

FIG. 11 is a timing chart of the operation transition of each substrate when the power is turned on.

FIG. 12 is a flowchart of a power-on processing routine executed by the main board 1 when the power is turned on.

FIG. 13 is a flowchart of a game start processing routine.

FIG. 14 is a flowchart of a normal symbol operation processing routine.

FIG. 15 is a flowchart of a normal electric auditors product operation processing routine.

FIG. 16 is a flowchart of a special symbol operation processing routine.

FIG. 17 is a flowchart of a first type special electric auditors product operation processing routine.

FIG. 18 is a flowchart of a power-off process routine.

FIG. 19 is a flowchart of a power-on process routine.

FIG. 20 is a flowchart of a payout control start processing routine.

FIG. 21 is a flowchart of a ball lending control processing routine.

FIG. 22 is a flowchart of a prize ball control processing routine.

FIG. 23 is a flowchart of a power-down processing routine.

FIG. 24 is a timing chart for explaining a state of the return confirmation of the main board 1 by the prize ball control board 3.

FIG. 25 is a configuration diagram showing a schematic configuration of a prize ball payout device 600.

FIG. 26 is a configuration diagram of a prize ball case 606.

FIG. 27 is an explanatory diagram of an operation of the prize ball case 606, (A) is an explanatory diagram of a prize ball payout operation, and (B) is an explanatory diagram of a ball rental operation.

FIG. 28 is an explanatory diagram of a cooling operation.

FIG. 29 is a timing chart illustrating an operating state of a RAM clear information signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main board, 3 ... Prize ball control board, 5 ... Gaming machine, 7 ... Design control board, 9 ... Voice control board, 11 ... Lamp control board,
13 ... Launch control board, 15 ... Power supply board, 16 ... Input S
W, 18 ... Output SOL, 21 ... Board external terminal board, 23 ...
Insufficient supply balls SW, 25 ... Lower saucer full SW, 31 ... Award balls SW1, 32 ... Award balls SW2, 33 ... Ball rental SW1, 34 ...
Ball-renting SW2, 35 ... Award ball motor control SW, 37 ... Award ball motor, 37A ... Shaft, 41 ... Frame external terminal plate, 43 ... Gold frame opening SW, 45 ... Inner frame opening SW, 46 ... Status indicator, Four
7 ... Special symbol display device, 49 ... Normal symbol display device, 51
… Speaker, 53… Illumination, 61… Touch plate, 63
... Launch stop SW, 65 ... Launch motor, 71, 83 ... MP
U, 121 ... Clear SW, 123 ... Power failure signal generation circuit,
125 ... Reset signal creation circuit, 127 ... Main board and prize ball control board backup power supply creation circuit, 131 ... + 5
V, + 12V power generation circuit 133, + 24V, +32
V power generation circuit, 141 ... System reset circuit, 14
3 ... Blackout signal receiving circuit, 145 ... Clear signal receiving circuit,
147 ... Port circuit, 149 ... Strobe signal transmitting circuit, 150 ... Data signal transmitting circuit, 151 ... RESET
Terminals, 153 ... NMI terminals, 157 ... PORT terminals, 1
59 ... DATA terminal, 161 ... System reset circuit,
163 ... Blackout signal receiving circuit, 165 ... Strobe signal receiving circuit, 167 ... Data signal receiving circuit, 169 ... Port circuit, 171 ... Launch control signal output circuit, 173 ... RES
ET terminal, 175 ... NMI terminal, 177 ... Clear signal receiving circuit, 179 ... CLK / TRG2 terminal, 181 ... PO
RT terminal, 183 ... DATA terminal, 184 ... System reset circuit, 185 ... Strobe signal receiving circuit, 187
... Data signal receiving circuit, 189 ... RESET terminal, 19
1 ... INT0 terminal, 193 ... PORT terminal, 203 ... System reset circuit, 205 ... Strobe signal receiving circuit, 207 ... Data signal receiving circuit, 209 ... RESET
Terminals, 211 ... INT1 terminals, 213 ... PORT terminals,
233 ... System reset circuit, 235 ... Strobe signal receiving circuit, 237 ... Data signal receiving circuit, 239 ... R
ESET terminal, 241 ... INT1 terminal, 243 ... POR
T terminal, 251 ... Launch control circuit, 253 ... Reset circuit, 255 ... Launch control signal input circuit, 301 ... Rectifier section,
303 ... DC-DC converter unit, 305 ... Power failure signal
Reset signal creation unit, 307 ... Output buffer unit, 309
... Output terminal part, 311 ... + 24V output part, 313 ... +3
2V output section, 315 ... Bridge rectifier, 317 ... Smoothing circuit, 321 ... First smoothing section, 322 ... Second smoothing section, 325
… Regulator, 327… Backup capacitor,
328 ... Backup capacitor, 329 ... Backup capacitor, 331 ... + 5V-a output section, 333
... + 5V-b output section, 335 ... + 12V output section, 341
... Reset IC, 343 ... Σ ACDL terminal, 345 ... Σ
REL terminal, 347 ... Power supply monitoring IC, 351 ... 3-state buffer IC, 361 ... Lamp / voice connector,
363 ... Design connector, 365 ... Firing connector, 3
67 ... Connector for prize ball, 369 ... Connector for main board, 3
71 ... Award-power failure signal terminal, 373 ... Main-power failure signal terminal,
347 ... Power supply monitoring IC, 381 ... Error reset signal terminal, 382 ... Sound-reset terminal, 383 ... Figure-reset terminal, 385 ... Emission-reset terminal, 387 ... Award-reset terminal, 389 ... Main-reset terminal, 391 ... Award-clear signal terminal , 393 ... Main-clear signal terminal, 395 ... Normally open contact, 401 ... Connector, 403 ... Main-clear signal terminal, 405 ... Noise filter / waveform shaping section, 407 ...
CLRSW line, 409 ... Harness, 411 ... Main / power failure signal terminal, 413 ... Noise filter / wave shaping section, 415
... pull-up resistor, 417 ... EMI filter element, 419 ... low-pass filter, 421 ... Schmidt inverter, 431 ... main-reset signal terminal, 433 ... noise filter, 435 ... delay / waveform shaping section, 437 ... reset signal generation section, 439 ... EMI filter element, 441 ... Low-pass filter, 443, 445 ... Schmidt inverter, 447 ... Waveform shaping section, 451, 45
3 ... Schmidt inverter, 455 ... Directional charge / discharge circuit, 457 ... Delay circuit section, 459 ... AND circuit, 461
... buffer IC, 469 ... QH terminal, 471 ... divider circuit section, 473 ... shift register, 475 ... oscillator circuit section, 4
81 ... Port circuit IC, 484 ... RISETN terminal, 4
83 ... Parallel input terminal, 600 ... Prize ball payout device, 60
2 ... Ball receiving tank, 604 ... Ball conveying path, 606 ... Prize ball case, 608, 608A-D ... Discharge path, 610 ... Prize ball motor mounting chamber, 612 ... Sprocket chamber, 614 ... Sprocket unit, 620 ... Mounting claw, 622 ... 1st sprocket, 624 ... 2nd sprocket, 632 ... 1st supply path, 634 ... 2nd supply path, 642 ... 1st prize ball discharge path, 6
44 ... 2nd prize ball discharge path, 646 ... 1st ball rental discharge path, 64
8 ... 2nd ball rental discharge path, 652 ... Transport start position, 654 ...
Mounting recess, BKW ... Backup power supply line, CSW ... Clear signal line, DATAW ... Data signal line, DGW12 ... 1
2V power supply line, DGW 24 ... 24V power supply line, DG
W32 ... 32V power supply line, DGW5 ... 5V power supply line, RPA ... First release point, RPB ... Second release point, RSW ... Reset signal line, STBW ... Strobe signal line, TSW ... Power failure signal line, BKW ... Backup power supply Line, C8 ... Capacitor, CSW ... Clear signal line, D4 ... Diode, DATAW ... Data signal line, H
SSW ... Launch control signal line, R1, R7, R8 ... Resistor

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hidekatsu Takeuchi             15-14 Nishi 2-chome, Higashino-cho, Kasugai City, Aichi Prefecture (72) Inventor Makoto Yanagawa             2-102 Mino-cho, Kasugai City, Aichi Prefecture F-term (reference) 2C088 BC54 BC58 BC70 CA09 CA13                       CA31

Claims (15)

[Claims] 1. A gaming machine for providing a game, wherein main control means for inputting information from the gaming machine and performing processing for the gaming machine to provide the game, and a command from the main control means. Sub-control means for receiving and controlling each part of the gaming machine, operation starting means for starting the operation of the gaming machine, and delay processing for delaying the time when the main control means starts operation by the operation starting means. The delay means to perform and the delay means whose state has been changed by the delay processing,
A game machine comprising: delay circuit resetting means for returning to a state before the delay processing is performed in a shorter time than the time spent for the delay processing. 2. The game according to claim 1, wherein the delay means performs the delay process according to a charging time for charging the capacitor with a predetermined charging characteristic or a discharging time for discharging the capacitor with a predetermined discharging characteristic. Machine. 3. The gaming machine according to claim 2, wherein the delay circuit resetting means charges the capacitor with a predetermined charging characteristic when the capacitor performs delay processing by discharging. 4. The gaming machine according to claim 2, wherein the delay circuit resetting means discharges the capacitor with a predetermined discharge characteristic when the capacitor performs delay processing by charging. 5. The gaming machine according to claim 3, wherein the time constant of the charging circuit of the capacitor is smaller than the time constant of the discharging circuit of the capacitor. 6. The gaming machine according to claim 4, wherein the time constant of the discharging circuit of the capacitor is smaller than the time constant of the charging circuit of the capacitor. 7. A power supply means for supplying power to the main control means and / or the sub-control means, a voltage drop detection means for detecting whether the voltage of the power supply means has dropped for a predetermined time, and When the voltage drop detection means detects a voltage drop,
The game machine according to any one of claims 1 to 6, wherein a voltage drop signal output means for outputting a voltage drop signal to the main control means and / or the sub control means is added. 8. The gaming machine according to claim 7, wherein the operation starting means is provided in the power supply means. 9. The delaying means has a noise filter function for shielding noise contained in a signal supplied from the power supply means to the main control means, according to any one of claims 1 to 8. A game machine described in Crab. 10. A main backup storage means for storing the state of the main control means at the time when the power supplied to the main control means drops, and a main backup storage means for storing the state of the main backup storage means at the start of operation of the main control means. 10. A gaming machine according to claim 1, further comprising: a main control state returning means for returning the state of the main controlling means to a state at the time when the power source is lowered, based on a memory. . 11. A sub-backup storage means for storing the state of the sub-control means at the time when the power supplied to the sub-control means drops, and a sub-backup storage means for starting the operation of the sub-control means. When it is determined that the sub-control unit has become the same as the state at the time when the power supply is lowered, based on the memory,
11. The gaming machine according to any one of claims 1 to 10, further comprising power-down time point return determination means for determining that the sub-control means has returned to the state at the time of power supply reduction. 12. A signal input state backup storage means for storing an input state of a signal to the sub control means at the time when the power supplied to the sub control means decreases, and at the start of operation of the sub control means, Based on the storage of the signal input state backup storage means, when it is determined that the signal input to the sub control means is the same as the state at the time when the power supply is lowered, the input state of the signal of the sub control means is The game machine according to any one of claims 1 to 10, further comprising power-down time signal input state return determination means for determining that the power supply has returned to the state at the time of power reduction. 13. A signal input state backup storage means for storing an input state of a signal to the sub control means at the time when the power supplied to the sub control means decreases, and at the start of the operation of the sub control means, Based on the storage of the signal input state backup storage means, it waits until it is determined that the signal input to the sub control means becomes the same as the state at the time when the power supply is lowered, and the signal to the sub control means is When the input state becomes a signal at the time when the power source of the sub control means is lowered, an input return standby means for returning the state of the sub control means to the state of the time point when the power source is lowered is added. The gaming machine according to any one of claims 1 to 10. 14. A power supply drop time recovery judgment means monitors for a predetermined time whether a judgment is made that the power supply has returned to the state at the time of power supply drop, and when the power supply goes down by the predetermined time, 12. A gaming machine according to claim 11, further comprising a watchdog timer for initializing the sub-control means when it is not judged that the state has returned. 15. If the input state of the signal to the sub-control means does not become the signal at the time when the power source of the sub-control means drops even if the input recovery waiting means exceeds a predetermined time, the sub-control means 14. The gaming machine according to claim 13, wherein the control means is initialized.