JP2006175067A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To exactly prevent the inputting of the illegal signal from outside the game control board by a method wherein the contents of the respective memory means in the game control means and in the put-out control means are initialized exactly to transmit the information indicating the detection of the putting out of the prize game media to the game control means from the put-out control means. <P>SOLUTION: When the software delay processing or the like is executed responding to the inputting of the reset signal, the game control means outputs the put-out start command to check the detection signal of a clear switch 921. When the inputting of the put-out start command is confirmed, the put-out control means checks the detection signal of the clear switch 921. When the putting out of the game balls is detected by a number of put-out balls counting switch 301 and if the detection is decided to correspond to the putting out of the prize balls, the put-out control means also turns on the prize ball counting signal for a prescribed period of time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is a game machine such as a pachinko gaming machine or a slot machine in which a player can play a predetermined game using a game medium and pays out the game medium to the player based on the fact that a payout condition is established. About.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Furthermore, there is provided a variable display unit capable of changing the display state, and configured to give a predetermined game value to the player when the display result of the variable display unit is in a predetermined specific display mode. is there.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. In other words, or a condition for winning a prize ball is easily established.

  In a pachinko gaming machine, the combination of a predetermined display mode with a display result of a variable display unit that displays a special symbol is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win.

  Game progress in the gaming machine is controlled by game control means including a game control microcomputer. When the payout control means including the payout control microcomputer for controlling the prize ball payout is mounted on a payout control board different from the main board on which the game control means is mounted, the progress of the game is transferred to the main board. Since it is controlled by the mounted game control means, the number of winning balls based on winning is determined by the game control means, and a control signal indicating the number of winning balls is transmitted to the payout control board. Then, the payout control means performs a process of paying out the number of prize balls based on the winning based on the control signal from the game control means. Further, when there is a ball lending request from the prepaid card unit, the payout control means performs a process of paying out the number of lending balls based on the request.

  In the gaming machine, a count switch for detecting the paid-out lending ball and detecting and outputting it to the pay-out control means, and detecting and outputting the paid-out prize ball to the game control means and the pay-out control means. Some of them are provided with a count switch (for example, see Patent Document 1). In the gaming machine configured in this way, the game control means and the payout control means have not paid out based on the detection signal from the count switch that detects the payout of the prize ball transmitted to the game control means and the payout control means. The number of prize balls is managed.

  Further, in the gaming machine, even when the power supply to the gaming machine is stopped, the backup power source is set so that the contents of the RAM provided in the game control means and the contents of the RAM provided in the payout control means are saved. A detection signal from a power supply monitoring means for detecting a drop in power supply voltage is input to the main board and the payout control board, and the game control means and the payout control means execute processing for storing information in the RAM. (For example, refer patent document 2). In the gaming machine configured as described above, a clear switch for clearing the contents of the stored RAM is provided, and when the power supply to the gaming machine is started, the game control is performed when the clear switch is pressed. The means and the payout control means are configured to clear the contents of the RAM.

  Further, in order to prevent a situation in which the payout control means cannot receive a control signal (command) transmitted from the game control means to the payout control means when power supply to the gaming machine is started, the game control means There is a case where a delay means is provided for delaying the timing at which the payout control means starts up (becomes able to execute the game control device control process) than the timing at which the payout control means starts up (becomes able to execute the payout control process).

JP 2001-187250 A (paragraphs 0065, 0069, 0152 to 0161, FIGS. 7 and 26) JP 2002-136754 A (paragraphs 0010-0014, 0021-0023, FIG. 1, FIG. 3, FIG. 5)

  As described above, in the gaming machine described in Patent Document 1, the payout control means pays out the number of prize balls based on the winning based on the control signal from the game control means, and from the count switch that detects the payout of the prize ball The detection signal is input to the game control means and the payout control means, and the game control means and the payout control means can both manage the number of unpaid balls based on the input detection signal from the count switch. Has been. In such a case, it is necessary to provide a count switch for detecting the payout of the lending ball that outputs a detection signal only to the payout control means separately from the count switch for detecting the payout of the prize ball. End up.

  Further, in the gaming machine described in Patent Document 2, when the power supply to the gaming machine is started, the timing at which the game control means starts up is set to be later than the timing at which the payout control means starts up. When the clear switch is pressed by a game clerk or the like when power supply to the gaming machine is started to clear the contents of the RAM, if the timing of pressing is delayed or the pressing time is short, the payout control means Can recognize the press of the clear switch, but the game control means may not be able to recognize the press of the clear switch. The reason for pressing the clear switch is to clear and initialize data stored when the power supply to the gaming machine is stopped, that is, data related to the control state when the power supply is stopped. When a situation occurs in which the payout control means can recognize the press of the clear switch but the game control means cannot recognize the press of the clear switch, the control state of the payout control means is initialized, but the game control means The control state remains the control state when the power supply is stopped, the control states of both control means are not consistent, and normal control cannot be performed as a whole gaming machine. Also, even if the game control means does not have a structure for delaying the timing at which the game control means rises compared to the timing at which the payout control means rises, depending on how the clear switch is depressed, one control means can recognize the depression of the clear switch. However, there may be a situation where the other control means cannot recognize the pressing of the clear switch.

  Accordingly, the present invention aims to reduce costs in a gaming machine in which game control means and payout control means are provided separately, and to reliably transmit information indicating detection of payout of prize game media to the game control means. An object of the present invention is to provide a gaming machine that can be used. In addition, the present invention has a storage means that allows the game control means and the payout control means to store the stored contents for at least a predetermined period when power supply to the gaming machine is stopped, and initializes the stored contents of the storage means An object of the present invention is to make it possible to reliably initialize the contents of each storage means in the game control means and the payout control means based on the operation of the operation means.

  In the gaming machine according to the present invention, a player can play a predetermined game using a game medium (for example, a game ball), and a payout condition is satisfied (for example, occurrence of a prize, generation of a loan request from a player). ), And a game control microcomputer (for example, a CPU 56 including a CPU 56) that executes a game control process (for example, steps S41 to S56) for controlling the progress of the game. A game control board (for example, a game control board (main board) 31) equipped with a control microcomputer 560), a payout means (for example, a ball payout device 97) for paying out game media, and a payout control process for controlling the payout means Payout control microcomputer (for example, payout control CPU 371 including payout control CPU 371) that executes (for example, steps S753 and S756) A payout control board (e.g., payout control board 37) equipped with a computer 370) and a prize game medium (e.g., a prize ball) as a prize based on establishment of a payout condition by a game (e.g., winning a game ball in a prize area). A payout detecting means (for example, a payout detecting means for detecting a payout and payout of a rental game medium (eg, a rental ball) based on establishment of a payout condition by a loan request (eg, Y in step S623) and outputting a detection signal to the payout control microcomputer (eg, Payout number count switch 301), operation means (for example, clear switch 921) for outputting an operation signal (for example, clear switch signal) in response to an operation, and an effect device (for example, variable display device 9, lamp / LED, speaker 27, etc.) control signals from the game control microcomputer (eg, production control) And an effect control board (for example, the effect control board 80) on which an effect control microcomputer (for example, the effect control microcomputer 100) is controlled according to the command), and the game control microcomputer is output to the effect control microcomputer. A relay board (for example, a centralized relay board 77) that relays the control signal, and the game control board is a signal direction regulating means (for example, a ramp circuit 36 or an output buffer circuit 67) that blocks input of signals from the relay board. The game control microcomputer stores the execution state of the game control process, and even if the power supply to the game machine stops, the game control variation data storage means (for example, the stored contents are retained for a predetermined period) RAM 55 that is backed up by power) and establishment of payout conditions by game (for example, occurrence of a prize) A payout control signal (for example, a prize ball number command) that can specify the number of premium game media to be paid out together with a take-in signal (for example, a prize ball REQ signal) for instructing the take-in of the command signal. The payout command signal output means (for example, the part for executing the processing of steps S251 to S255 and S203 in the gaming control microcomputer 560) and the power supply to the gaming machine are started, so that the gaming control process can be executed. A payout control start signal output means for outputting a payout control start signal (for example, a payout start command) together with a take-in signal (for example, a prize ball REQ signal) to the payout control microcomputer (for example, a step in the game control microcomputer 560) Portion for executing the process of S5) and payout control activation signal output means After outputting the payout control activation signal, game control operation signal confirmation means for confirming whether or not the operation signal is outputted from the operation means (for example, a part for executing the processing of step S7 in the game control microcomputer 560); When the game control operation signal confirmation means confirms that no operation signal is output, the game returns the execution state of the game control process based on the stored contents held in the game control variation data storage means. When the control execution state return means (for example, the portion of the game control microcomputer 560 that executes steps S91 to S94) and the game control operation signal confirmation means confirm that the operation signal is output. , The stored contents held in the game control variation data storage means are initialized, and the game control process is started from the initial state. Including a game control execution state initialization means (for example, a portion of the game control microcomputer 560 that executes the processes of steps S10 to S14), and the payout control microcomputer stores the execution state of the payout control process. , Fluctuation data storage means for payout control (for example, RAM that is backed up by power supply) that retains the stored contents for a predetermined period even when power supply to the gaming machine is stopped, and a capture signal is input from the gaming control microcomputer In response to this, the value of a specific register (for example, external interrupt request register) is updated to a predetermined value (for example, 80 (H)) (for example, an external interrupt request register performed by the internal mechanism of the payout control CPU 371) And the payout control process (for example, a prize ball REQ discount) Interrupt processing execution means (for example, realized by an internal mechanism of the payout control CPU 371 and a portion of the payout control microcomputer 370 that executes the prize ball REQ interrupt processing), Interrupt prohibition means for controlling to an interrupt prohibition state for prohibiting execution of interrupt processing by the interrupt processing execution means (for example, execution of an interrupt prohibition instruction by a program (for example, step S701) is prohibited. An internal mechanism of the payout control CPU 371) and a payout command signal input means for inputting a payout command signal from the payout command signal output means in the interrupt processing (for example, a prize ball REQ interrupt process in the payout control microcomputer 370). And the prize game designated by the payout command signal input by the payout command signal input means. The number of payouts of the body is stored in the payout control variation data storage means (for example, step S545), and the number of payout game media stored in the payout control variation data storage means is controlled to be paid out. The prize game medium payout control means for executing the payout process (for example, the portion of the payout control microcomputer 370 that executes the process of step S756), and the detection signal input from the payout detection means is the difference between the prize game medium and the rental game medium. A payout determination means for determining which payout is due (for example, a portion for executing steps S601 to S603 in the payout control microcomputer 370), and a detection signal is output by the payout determination means by the prize game medium payout control means. When it is determined that the payment is due (for example, step S6) (2) Y) Count signal output means (for example, payout) for outputting a prize game medium count signal (for example, a prize ball count signal) indicating detection of payout of the prize game medium by the prize game medium payout control means to the game control microcomputer The part of step S606 in the control microcomputer 370) and the internal state of the payout control microcomputer after the interruption prohibiting means controls the interruption prohibiting state when power supply to the gaming machine is started. The initial setting process is executed by the initial setting means (for example, the portion for executing steps S702 to S705 in the payout control microcomputer 370) and the initial setting means for executing the initial setting process (for example, steps S702 to S705). Register to check whether the value of a specific register is a predetermined value after When the confirming means (for example, the part for executing steps S720 to S723 in the payout control microcomputer 370) and the register confirming means confirm that the value of the specific register is a predetermined value, the payout control activation signal output means The payout control start signal input means for inputting the payout control start signal (for example, the part for executing steps S721 and S725 in the payout control microcomputer 370) and the payout control start signal input means input the payout control start signal. On condition, payout control operation signal confirmation means for confirming whether or not an operation signal is output from the operation means (for example, a part for executing the processing of steps S727 and S708 in the payout control microcomputer 370), payout The control signal confirmation means does not output an operation signal. When it is confirmed, the payout control execution state return means (for example, step in the payout control microcomputer 370) returns the execution state of the payout control process based on the storage contents held in the payout control variation data storage means. A portion for executing the processing of S708, S711 and the processing of setting the award ball unpaid number counter initial value (set in step S711) in step S713 in the award ball unpaid number counter) and the payout control operation signal confirmation means, When it is confirmed that the operation signal has been output, the payout control execution state initialization means (initializing the storage contents held in the payout control variation data storage means and starting the payout control process from the initial state ( For example, steps 707, S 712, S 71 in the payout control microcomputer 370. And the control state related to payout due to the establishment of a predetermined condition (for example, Y in step S808 or Y in step S811, that is, the occurrence of either a full tank error or a ball shortage error shown in FIG. 52) Error state setting means for shifting to a state (for example, a state in which the full flag error bit and the ball break error bit of the error flag are set) (for example, a part for executing steps S809, S812 and S621 in the payout control microcomputer 370) And an abnormality notification means (for example, a game control microcomputer 560) that outputs an abnormality detection signal (for example, a payout error signal) indicating that the error state setting means has shifted to an error state to the game control microcomputer. Step S828 in The effect control microcomputer includes an error notification means (for example, command analysis in the effect control microcomputer 100) for notifying that the control state related to payout has shifted to an error state. Including the process (the part that executes the error notification generation process of step S324), and the game control microcomputer notifies the effect control microcomputer of the abnormality in response to the input of the abnormality detection signal from the abnormality notification means. Including an abnormality notification signal output means (for example, a part for executing step S24b in the game control microcomputer 560: see FIG. 27) for outputting an abnormality notification signal (for example, an error occurrence notification command) for The error state is set by the error state setting means. Even when a prize game medium count signal is output (for example, when it is determined in the process of step S621 that the error bit of the error flag is set, the subsequent payout process is not performed, but the error bit is set). Even if it is determined that the process has been performed, the processing of steps S602, S603, and S606 is executed), and the effect control microcomputer uses the error notification means based on the abnormality notification signal from the abnormality notification signal output means. Will inform you that it has moved to an error state (for example, “An error has occurred! ”Or the like is displayed in the display area of the variable display device 9). As described above, the game control board is provided with the signal direction restricting means (for example, the ramp circuit 36 and the output buffer circuit 67) for blocking the input of the signal from the relay board. It is preferable that signal direction restricting means (for example, unidirectional circuits 74, 75, 76 shown in FIG. 8) for blocking the input of signals from the control board is provided.

  In addition, another gaming machine according to the present invention allows a player to play a predetermined game by firing a game medium (for example, a game ball) into the game area, and is provided in a predetermined prize area (for example, a game area). A prize game medium (for example, a prize ball) is paid out as a prize based on the fact that the game medium has won a prize in the fixed winning ports 29, 30, 33, 39 and the variable prize ball device 15), and a rental request from the player is made. Is a gaming machine that pays out a lending game medium (for example, a lending ball) to be lent to a player based on a lending request signal (for example, a BRDY signal, a BRQ signal) from a lending request receiving apparatus (for example, a prepaid card unit 50). , A launching means for launching the game medium toward the game area (for example, a hitting ball launching device including the launch motor 94), and a game control process for controlling the progress of the game (for example, a step). A game control board (for example, the game control board (main board) 31) on which a game control microcomputer (for example, the game control microcomputer 560) is executed, and a payout means for paying out game media For example, a ball dispensing device 97), an input unit (for example, an I / O port 372f) to which a lending request receiving device connection signal (for example, a VL signal) indicating that the lending request receiving device is connected to the gaming machine is input, A payout control microcomputer (for example, payout control microcomputer 370) that executes a payout control process (for example, steps S753 and S756) for controlling the payout means, and a loan request accepting apparatus connection signal from the lending request accepting apparatus are input. A photocoupler that transmits a connection signal to the payout control microcomputer For example, a payout control board (for example, payout control board 37) on which a photocoupler 151) and capacitors (for example, capacitors 153 and 154) connected between the input unit and the photocoupler are mounted, and a loan from the lending request reception device A loan request accepting device relay board (for example, interface board 66) that relays the request signal and outputs it to the payout control board, and launching that stops the operation of the launching means when the connection signal transmitted from the photocoupler is not input Based on stop means (for example, the AND circuit 155 mounted on the payout control board 37), payout of a prize game medium as a prize based on establishment of a payout condition by game (for example, winning of a game ball in a winning area), and by a lending request Based on the establishment of the payout condition (for example, Y in step S623), the payout of the rental game medium is detected, and the payout control marker is detected. Game control is provided with a payout detection means (for example, a payout number count switch 301) for outputting a detection signal to the microcomputer and an operation means (for example, a clear switch 921) for outputting an operation signal (for example, a clear switch signal) according to the operation. The microcomputer for the game stores the execution state of the game control process, and even if the power supply to the game machine is stopped, the game control variation data storage means (for example, the power-backed up RAM 55) retains the stored contents for a predetermined period. And a payout command signal (for example, a prize ball number command) that can specify the number of prize game media to be paid out based on the establishment of a payout condition by the game. A payout command signal output means (for example, a game control machine) that outputs to the payout control microcomputer together with the signal) The portion of the black computer 560 that executes the processing of steps S251 to S255 and S203, and when the power supply to the gaming machine is started and the game control processing can be executed, the payout control start signal (for example, the payout start command) ) And a payout control start signal output means (for example, a part for executing the processing of step S5 in the game control microcomputer 560) which outputs to the payout control microcomputer together with a take-in signal (for example, a prize ball REQ signal), and a payout control start. After the signal output means outputs the payout control activation signal, the game control operation signal confirmation means for confirming whether or not the operation signal is outputted from the operation means (for example, the processing of step S7 in the game control microcomputer 560 is executed) And the game control operation signal confirmation means output an operation signal. When it is confirmed that the game control is executed, the game control execution state return means (for example, the game control microcomputer 560) returns the execution state of the game control process based on the stored contents held in the game control variation data storage means. In which the processing of steps S91 to S94 is performed) and when the game control operation signal confirmation means confirms that the operation signal is output, the memory held in the game control variation data storage means Game control execution state initialization means for initializing the contents and starting the game control process from the initial state (for example, a part for executing the processing of steps S10 to S14 in the game control microcomputer 560), and a payout control micro The computer stores the execution state of the payout control process, and even if the power supply to the gaming machine stops In response to the input of a take-in control variable data storage means (for example, a RAM that is backed up by a power source) and a game control microcomputer for which a stored content is held for a predetermined period, a specific register (for example, The value of the external interrupt request register) is updated to a predetermined value (for example, 80 (H)) (for example, by setting the bit of the external interrupt request register performed by the internal mechanism of the payout control CPU 371) and the payout control process Interrupt processing execution means (for example, an internal mechanism of the payout control CPU 371 and a payout ball REQ interrupt process in the payout control microcomputer 370) that executes an interrupt process (for example, a prize ball REQ interrupt process). And the interrupt disabled state that prohibits execution of interrupt processing by the interrupt processing execution means. An interrupt prohibiting means (for example, an internal mechanism of the payout control CPU 371 prohibiting the generation of an interrupt based on execution of an interrupt prohibition instruction by a program (eg, step S701)) and a payout command signal from the payout command signal output means , A payout command signal input means (for example, a part of the payout control microcomputer 370 that executes the process of step S545 in the prize ball REQ interrupt process) and a payout command signal input means that are input by the payout command signal input means The number of payouts of the prize game medium designated by the command signal is stored in the payout control variation data storage means (for example, step S545), and the number of payout game media stored in the payout control fluctuation data storage means is paid out. Premium game medium payout control means (for example, payout control) A part for executing the process of step S756 in the microcomputer 370) and a payout determining means for determining whether the detection signal input from the payout detecting means is a payout of the prize game medium or the rental game medium (for example, payout control) Portion of the microcomputer 370 that executes steps S601 to S603) and when the payout determining means determines that the detection signal is due to the payout of the prize game medium by the prize game medium payout control means (for example, Y in step S602) Further, counting signal output means (for example, a payout control microcomputer) for outputting a prize game medium count signal (for example, a prize ball count signal) indicating detection of payout of the prize game medium by the prize game medium payout control means to the game control microcomputer. Step S in 370 606) and an initial setting process for initializing the internal state of the payout control microcomputer after the interruption prohibiting means controls the interruption prohibiting state when power supply to the gaming machine is started. Initial setting means for executing (for example, steps S702 to S705) (for example, a portion for executing steps S702 to S705 in the payout control microcomputer 370), and the initial setting processing by the initial setting means, the value of the specific register is When register confirmation means for confirming whether or not the value is a predetermined value (for example, a part for executing steps S720 to S723 in the payout control microcomputer 370) and the register confirmation means confirm that the value of the specific register is a predetermined value A payout control start signal output from the payout control start signal output means An operation signal is input from the operation means on the condition that the start signal input means (for example, the part for executing steps S721 and S725 in the payout control microcomputer 370) and the payout control start signal input means input the payout control start signal. The payout control operation signal confirmation means (for example, the portion of the payout control microcomputer 370 that executes the processes of steps S727 and S708) and the payout control operation signal confirmation means A payout control execution state return means (for example, payout control) for returning the execution state of the payout control process based on the stored contents held in the payout control variation data storage means when it is confirmed that no signal is output. Steps S708 and S711 in the microcomputer 370 In step S713, a portion for executing a process of setting the initial value of the award ball unpaid number counter (set in step S711) in the award ball unpaid number counter) and an operation signal confirmation means for payout control output an operation signal. When it is confirmed that the payout control fluctuation data storage means is initialized, the storage contents stored in the payout control variation data storage means are initialized, and the payout control execution state initialization means (for example, the payout control micros The portion of the computer 370 that executes the processing of steps 707, S712, and S713) and the establishment of a predetermined condition (for example, Y in step S808 or Y in step S811, that is, occurrence of either a full tank error or a ball break error shown in FIG. ) Indicates the control status related to payout as an error status (for example, full error bit of error flag) Error state setting means (for example, a part for executing steps S809, S812 and S621 in the payout control microcomputer 370) to be shifted to the state in which the ball break error bit is set) and the connection transmitted from the photocoupler Input state determination means for determining the input state of the connection signal according to the input state of the signal (for example, the connection state of the card unit 50 depending on the input state of the VL signal in the prepaid card unit control process (step S754) in the payout control microcomputer 370) When the input state determination means determines that the connection signal has not been transmitted, it notifies that the lending request acceptance device is not connected to the gaming machine. The connection error notification process for Connection error notification processing means (for example, a part for executing steps S574 to S576 in the payout control microcomputer 370: processing for displaying a prepaid card unit unconnected error on the error display LED 374 as shown in FIG. 52), and counting The signal output means outputs a prize game medium count signal even when the error state setting means has shifted to the error state (for example, it is determined that the error bit of the error flag is set by the processing of step S621). In some cases, the subsequent payout process is not performed, but even if it is determined that the error bit is set, the processes in steps S602, S603, and S606 are performed).

  A connection signal transmitted from the photocoupler is branched and input to a dispensing control microcomputer (for example, dispensing control microcomputer 370) and a launch board (for example, launch board 90) for transmitting a launch control signal for driving the launching means. (See FIG. 6).

  When a predetermined standby period has elapsed without inputting a payout control activation signal from the payout control activation signal output means (for example, Y in step S723), the payout control microcomputer enters a stopped state in which the control is stopped. Transition (for example, when the start disable flag is set (step S724) and when it is confirmed that the start disable flag is set (Y of step S714), by setting the start error bit (step S715), The control stop state is set (steps S541 and S621; the control stop state is also included by performing a loop process for repeatedly executing the process of confirming the input of the payout start command until the payout start command is input. ) May be configured.

  When the predetermined standby period has elapsed without inputting the payout control activation signal from the payout control activation signal output means (for example, Y in step S723), the payout control microcomputer has detected an abnormality related to communication. Communication abnormality detecting means (for example, the portion of the payout control microcomputer 370 that executes step S724), and when the communication abnormality detecting means detects that an abnormality has occurred, communication abnormality notifying means that notifies that fact. (For example, the processing (steps S574 to S576) for displaying “A” (see FIG. 52) on the error display LED 374 in the payout control microcomputer 370) may be included. Good.

  When power supply to the gaming machine is started, an allowable signal output means (for example, a power supply monitoring circuit 920) that outputs an allowable signal (for example, a reset signal) that makes the gaming control microcomputer and the payout control microcomputer operable. ) And when the payout control microcomputer and the game control microcomputer become operable based on the allowance signal from the allowance signal output means, than when the payout control microcomputer becomes operable. A delay means (for example, a part for executing the processing of steps S81 to S86 in the game control microcomputer 560 or the delay circuit 69) that makes the game control microcomputer operable by delaying for a specific period. (See FIGS. 17 and 58).

  A prize game medium payout notification means (for example, a prize ball lamp 51) for notifying that a prize game medium has been paid out by the prize game medium payout control means is provided, and the game control microcomputer receives a prize from the count signal output means. Process for notifying the prize game medium payout notification means in response to the input of the game medium count signal (for example, a prize ball notification process for outputting a prize ball payout confirmation designation command to the effect control microcomputer 100 (step S24a): (See FIG. 26).

  The payout control microcomputer is a lending game medium payout control means (for example, a payout control medium) that executes a lending process for controlling a payout means to pay out a predetermined number of lending game media based on establishment of a payout condition based on a loan request. The microcomputer 370 includes steps S623 to S628 in the payout start waiting process (step S610), a payout motor stop wait process (step S611), and a payout passing wait process (step S612). When neither a payout process by the game medium payout control means nor a lending process by the rental game medium payout control means is executed, a detection signal from the payout detection means is input (for example, a payout number count switch in step S601) When 301 turns on, step S 02 and step S603 are both N), it is determined that the detection signal is a payout of prize game media by the prize game medium payout control means (for example, the game ball paid out in step S602 is a prize ball) It may be configured to perform the same processing (steps S604 and S606) as the case where the determination is made.

  The payout control microcomputer is a rented game medium number data storage means (for example, a payout control microcomputer 370) for storing rented game medium number data indicating the number of rented game media to be paid out by the lending process by the rented game medium payout control means. And the payout determining means determine that the detection signal from the payout detecting means is due to payout of the rental game medium by the rental game medium payout control means (in step S603). Y) In response to this, the rental game medium number data subtracting means (for example, subtracting the rental game medium number data stored in the rental game medium number data storage means even when the error state setting means has shifted to the error state (for example, Step S605 in the payout control microcomputer 370 is executed. Min) and it may be configured to include.

  According to the first aspect of the present invention, there is provided payout detection means for detecting the payout of the premium game medium and the payout of the rental game medium, and outputting a detection signal to the payout control microcomputer. It is determined whether the detection signal input from the means is a payout of the prize game medium or the rental game medium, and when it is determined that the detection signal is a payout of the prize game medium, the game control microcomputer On the other hand, a prize game medium count signal indicating the detection of the payout of the prize game medium is output, and even if the control state related to the payout is an error state, when the detection signal from the payout detection means is input, the payout detection means If it is determined that the detection signal from the player is due to payout of the prize game medium, the prize game medium count signal is sent to the game control microcode. Since it is configured to output to a computer, it is not necessary to separately provide payout detection means for detecting payout of rental game media and payout detection means for detecting payout of premium game media, thereby reducing the cost of the gaming machine In addition, it is possible to reliably transmit a prize game medium count signal indicating detection of payout of prize game media to the game control means. When the game control microcomputer outputs a payout control start signal to the payout control microcomputer, it is checked whether an operation signal is output from the operating means, and the payout control microcomputer After the control, the payout control start signal output from the game control microcomputer is input when it is confirmed that the value of the specific register is a predetermined value, and the operation is performed on condition that the payout control start signal is input. Since it is configured to confirm whether or not an operation signal is output from the means, the fluctuation data storage in the other microcomputer is performed even though the contents of the fluctuation data storage means in one microcomputer are initialized. It is possible to prevent the situation that the contents of the means are not initialized and play based on the operation of the operation means. The contents of each variation data storage means in the control microcomputer and the payout control microcomputer can be reliably initialized. At that time, the payout control microcomputer can normally execute the initial setting process due to the interrupt process based on the signal from the game control microcomputer. In addition, since the game control board is provided with a signal direction restricting means for blocking signal input from the relay board, even if an illegal act is made on the relay board, an illegal signal is sent to the game control means. Can be prevented from being input, and it is possible to more reliably prevent an illegal signal from being input to the game control means from outside the game control board. Further, the payout control microcomputer outputs an abnormality detection signal indicating that the state has shifted to the error state to the game control microcomputer, and the game control microcomputer performs the effect control according to the input of the abnormality detection signal. An abnormality notification signal for notifying the microcomputer of an abnormality is output, and the production control microcomputer is configured to notify the fact that it has shifted to an error state based on the abnormality notification signal. The control microcomputer can recognize that an abnormality has occurred in the game medium payout control, and can make the player easily recognize that such an abnormality has occurred.

  In the second aspect of the invention, similarly to the first aspect of the invention, it is not necessary to separately provide payout detection means for detecting payout of rental game media and payout detection means for detecting payout of premium game media. The machine cost can be reduced, and the prize game medium counting signal indicating the detection of the payout of the prize game medium can be reliably transmitted to the game control means, and the contents of the fluctuation data storage means in one microcomputer It is possible to prevent the occurrence of a situation in which the contents of the variable data storage means in the other microcomputer are not initialized even though the other microcomputer is initialized, and a game control microcomputer and a payout control microcomputer based on the operation of the operation means It is possible to reliably initialize the contents of each variation data storage means. In addition, since the photocoupler for transmitting the lending request accepting device connection signal from the lending request accepting device and the capacitor connected between the photocoupler and the input unit are mounted on the dispensing control board, the lending request accepting device and It is no longer necessary to mount a capacitor connected to the photocoupler that transmits the lending request acceptance device connection signal on the relay board that relays the signal to and from the payout control board. It becomes easy to find out, and cheating can be prevented.

  In the invention described in claim 3, since the connection signal transmitted from the photocoupler is branched and input to the dispensing control microcomputer and the launch board for transmitting the launch control signal for driving the launching means, The driving of the launching means can be stopped according to the transmission state of the lending request accepting apparatus connection signal by the photocoupler.

  In the invention according to claim 4, when the predetermined waiting period elapses without inputting the payout control activation signal from the payout control activation signal output means, the payout control microcomputer stops the control. Therefore, it is possible to prevent the payout control process from being executed in a state where the game control process may not be started in the game control microcomputer.

  In the invention according to claim 5, an abnormality relating to communication has occurred when the predetermined waiting period has elapsed without the payout control microcomputer inputting the payout control start signal from the payout control start signal output means. Communication abnormality detecting means for detecting this, and communication abnormality notifying means for notifying that when the communication abnormality detecting means detects that an abnormality has occurred, the payout control microcomputer starts the payout control. It is possible to reliably notify that the signal cannot be input.

  According to the sixth aspect of the present invention, when the power supply to the gaming machine is started, the permission signal output means for outputting the permission signal for making the game control microcomputer and the payout control microcomputer operable, and the permission When the payout control microcomputer and the game control microcomputer become operable based on the permission signal from the signal output means, the delay is delayed by a specific period from the time when the payout control microcomputer becomes operable. Since the game control microcomputer is provided with delay means for enabling the game control microcomputer, the game control microcomputer outputs a payout command signal output to the payout control microcomputer by the game control microcomputer. Can be input reliably.

  According to the seventh aspect of the invention, the game control microcomputer is configured to perform processing for informing the prize game medium payout notifying means in response to the input of the prize game medium count signal. It is possible to eliminate the need for the payout control microcomputer to control the payout notification means, and the control burden of the payout control microcomputer is reduced, and the prize game medium is paid out in accordance with the actual payout of the prize game medium. This can be notified to a player, a game shop clerk or the like.

  In the invention described in claim 8, the payout control microcomputer executes a lending process in which the payout control microcomputer executes a lending process in which a predetermined number of lending game media are discharged by controlling the payout means based on the establishment of a payout condition based on the lending request. A detection signal from the payout detection means is input when the payout determination means includes the control means, and neither the payout process by the prize game medium payout control means nor the lending process by the rental game medium payout control means is executed. Since the detection signal is determined to be due to the payout of the prize game medium, the prize game medium count signal is transmitted to the game control microcomputer even when an irregular payout is made, and the game control is performed. The microcomputer can perform appropriate processing.

  According to the ninth aspect of the present invention, the rental game medium number data storage means for storing the rental game medium number data indicating the number of loaned game media to be paid out by the payout control microcomputer by the rental game medium payout control means. And the rental game medium even when the error state setting means shifts to the error state in response to the determination by the payout determination means that the detection signal input from the payout detection means is due to the payout of the rental game medium Since the rented game medium number data subtracting means for subtracting the rented game medium number data stored in the number data storage means is included, the unpaid number of rented game media can be managed reliably. .

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Each time there is a valid start prize, the display color changes (for example, changes from blue display to red display), and the start storage display area is increased by one. Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, since the symbol display area and the start memory display area are provided separately, the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. Further, the display of the start memory number may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9. However, a display (special symbol start memory display) for displaying the start memory number may be provided separately from the variable display device 9. Good.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing a large winning opening (variable winning ball apparatus). Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area: special area) is detected by the V count switch 22, and the winning ball from the opening / closing board 20 is counted. 23. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of game balls to the winning holes 29, 30, 33, 39 is performed by winning hole switches 29a, 30a, 33a, 39a, respectively. Detected. Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break LED 52 that is lit when the supply ball has run out is located in the vicinity of the right frame lamp 28c. Is provided. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, a prepaid card unit (hereinafter referred to as “card unit”) that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1 (not shown in FIG. 1). .

  The card unit includes, for example, a use indicator lamp that indicates whether or not the card unit is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, When checking the card insertion indicator lamp indicating that the card is inserted, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock is provided to release the unit.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning port 14 and is detected by the start port switch 14a, the special symbol starts variable display (variation) on the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When a game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the variable display device 9 at the time of stopping is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 2, on the back side of the pachinko gaming machine 1, a ball storage tank 38 is provided on the top of the mechanism plate in the outer frame 2A, and the pachinko gaming machine 1 is installed on the gaming machine installation island. A game ball is supplied to the ball storage tank 38 from above. The game balls in the ball storage tank 38 pass through the guide basket 39 and reach the ball payout device covered with the prize ball case 40A.

  Further, on the back side of the gaming machine, a variable display control unit 49 including an effect control board 80 on which an effect control microcomputer for controlling the variable display device 9 is mounted, and a game on which a game control microcomputer and the like are mounted. A control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed.

  The effect control means for performing variable display control of the variable display device 9 is realized by an effect control microcomputer mounted on the effect control board 80 or a VDP. Further, the gaming machine drives a frame side lamp driver board 35 on which circuits for driving a top frame lamp 28a, a left frame lamp 28b, a right frame lamp 28c, etc. provided on the frame side are mounted, and a speaker 27. A voice control board 70 on which a circuit to be mounted is mounted.

  Further, a power supply board 910 and other boards (not shown) on which power supply circuits for creating DC30V, DC21V, DC12V, and DC5V are mounted are provided. A central relay board 77 is provided for relaying signals output from the main board 31 to other boards.

  The electrical component control boards (payout control board and effect control board) are each equipped with electrical component control means (payout control means and effect control means) including an electric component control microcomputer. The payout control means and the effect control means control electrical components (game device: ball payout device 97, variable display device 9 and the like) provided in the gaming machine according to a command signal (control signal) from the game control means. Further, the light emitters such as lamps and LEDs provided on the frame side, and electrical components such as the speaker 27 are mounted on the frame side lamp driver board 35 and the sound control board 70 in accordance with a control signal from the effect control means. Driven by circuit components. Furthermore, game machines include a board on which a switch is mounted and a board on which a light emitting body such as a lamp or LED (hereinafter also referred to as a lamp / LED) is mounted. The substrate is a printed wiring board on which electrically driven electrical components, circuit components, connection components such as connectors and terminals, and the like are mounted.

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 includes at least a ball break terminal for introducing the output of the ball break detection switch 167 and outputting it externally, a prize ball terminal and a ball for outputting prize ball information (prize ball control signal) to the outside. A ball lending terminal for externally outputting lending information (ball lending number signal) is provided. Near the center, an information terminal board (information output board) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed.

  The game balls stored in the ball storage tank 38 pass through the guide rod 39 and reach the ball payout device covered with the payout case 40A via the curve bag 39. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion (the storage tank 38 In the vicinity of the When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  Hereinafter, the electrical component control board on which the microcomputer is mounted and the board for inputting a signal from the main board 31 may be collectively referred to as a peripheral board.

  FIG. 3 is a front view (FIG. 3 (A)) and a cross-sectional view (FIG. 3 (B)) showing the ball dispensing device 97 covered with the dispensing case 40A. The ball payout device 97 is fixed to the lower part of the passage body installed between the ball break switch 187 and the ball payout device 97. The passage body has a ball passage for flowing down two rows of game balls whose flow-down direction is converted into the left-right direction by a curve saddle. A ball break switch 187 is installed on the upstream side of the ball passage. In practice, a ball break switch is installed in each ball passage. The ball break switch 187 detects the presence or absence of a game ball in the ball passage. When the ball break switch 187 no longer detects a game ball, the ball discharge device 97 has a payout motor (not shown in FIG. 3). Rotation is stopped and game ball payout is immobilized.

  Further, the ball break switch 187 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball passage.

  In the ball payout device 97, a payout motor (not shown) using a stepping motor rotates, for example, a cam, thereby paying out one winning ball or one game ball based on a ball lending request. Further, below the ball payout device 97, for example, a payout number count switch 301 using a proximity switch is provided. Each time one game ball falls from the ball payout device 97, the payout number count switch 301 is turned on. That is, the payout number count switch 301 detects a game ball actually paid out from the ball payout device 97. Therefore, the payout control means can count the number of game balls actually paid out by the detection signal of the payout number count switch 301. In this example, the payout number count switch 301 detects both the paid-out prize balls and rental balls. That is, the payout of prize balls and the payout of rental balls are detected by the same detection means. Therefore, the number of parts can be reduced, and the cost of the gaming machine can be reduced.

  In this embodiment, the ball payout device 97 is configured to perform both prize ball payout and ball lending. However, a ball payout device for paying out a prize ball and a ball payout device for lending a ball may be provided separately. When separately provided, the payout means is composed of a ball payout device for paying out a prize ball and a ball payout device for lending a ball. Furthermore, for example, it may be configured to change the direction of rotation of the cam or sprocket so as to separate the winning ball payout and the ball lending. The present invention can be applied to any structure other than the structure).

  FIG. 4 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 4 also shows a payout control board 37, an effect control board 80, and the like. A basic circuit (corresponding to game control means) 53 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The basic circuit 53 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, and a game control microcomputer 560 having a CPU 56 for performing control operations in accordance with the program. And an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 may be external or built-in. Further, the I / O port unit 57 may be incorporated in the game control microcomputer 560. In this case, the game control microcomputer 560 also includes an I / O port unit.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54. Therefore, hereinafter, the game control microcomputer 560 executes (or performs processing) specifically. Is that the CPU 56 executes control according to the program. The same applies to microcomputers mounted on substrates other than the main substrate 31. The game control means is realized by a basic circuit 53 including a game control microcomputer 560.

  The RAM 55 is a backup RAM as non-volatile storage means that is partly or wholly backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data (special symbol process flag, etc.) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. Note that the data according to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power supply is restored after a power failure or the like. . In this embodiment, it is assumed that the entire RAM 55 is backed up.

  The basic circuit 53 receives a power-off signal from the power supply board 910. The power-off signal is output from the power supply circuit when the power supply voltage supplied to each unit by the power supply circuit drops below a predetermined value.

  A reset signal from the power supply board 910 is input to the reset terminal of the CPU 56. When the reset signal changes from low level to high level, the CPU 56 starts operation. That is, the processing based on the program stored in the ROM 54 is started.

  The main circuit board 31 is supplied with signals from the gate switch 32a, the start port switch 14a, the V count switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and the clear switch 921 to the basic circuit 53. An input driver circuit 58 is also mounted, and the solenoid 16 that opens and closes the variable winning ball apparatus 15, the solenoid 21 that opens and closes the opening / closing plate 20, and the solenoid 21 </ b> A for switching the path in the big prize opening is driven according to a command from the basic circuit 53. A circuit 59 is also mounted.

  A switch common voltage (for example, + 12V) is supplied to each of the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a. A switch common monitoring circuit 71 for monitoring the voltage is mounted. When the switch common monitoring circuit 71 detects that the switch common voltage has decreased to a predetermined value, the switch common monitoring signal input to the basic circuit 53 is turned off.

  Further, on the main board 31, in accordance with data given from the basic circuit 53, jackpot information indicating the occurrence of jackpot, effective starting information indicating the number of starting winning balls used to start variable display of symbols in the variable display device 9, An information output circuit 64 is provided for outputting an information output signal such as probability variation information indicating that a probability variation has occurred to an external device such as a hall computer.

  Further, the main board 31 is provided with a decoration lamp 25 that is a light emitter provided on the panel side, a normal symbol display 10 that variably displays a normal symbol, and a lamp circuit 36 that drives a normal symbol start memory display 41. It has been. Note that an LED may be used as the decorative lamp 25.

  The hitting ball launching device that hits and launches the game ball includes a launch motor 94 controlled by a circuit on the launch board 90, and the launch motor 94 rotates to launch the game ball toward the game area 7. A drive signal (shooting motor signal) for driving the firing motor 94 is input from the main board 31 to an AND circuit mounted on the firing board 90. In addition, the touch sensor detects that the player is touching the operation knob (hitting ball handle) 5, and a control signal from the touch sensor is input to an AND circuit mounted on the launch board 90. The AND circuit outputs a drive signal to the firing motor 94 when the firing motor signal and the control signal from the main board 31 are input (when both the firing motor signal and the control signal are on). Accordingly, when the firing motor signal from the main board indicates the off state, or when the control signal from the touch sensor circuit indicates the off state, the driving of the firing motor 94 is stopped. Note that the operation knob 5 is provided with a touch ring that adjusts the resilience and is a part that the player contacts. In the gaming machine, the launch board 90 is disposed between the touch ring and the main board 31 and is disposed in the vicinity of the touch ring. Specifically, the wiring length between the touch ring and the launch board 90 is shorter than the wiring length between the launch board 90 and the main board 31.

  The basic circuit 53 (specifically, the game control microcomputer 560) mounted on the main board 31 transmits an effect control command to the effect control board 80 in accordance with the control state. Then, the effect control means (specifically, the effect control microcomputer) executes a process of receiving the effect control command, and controls the light emitter provided on the frame side via the frame side lamp driver board 35. At the same time, the sound output from the speaker 27 is controlled via the sound control board 70. Note that a microcomputer may be mounted on the frame side lamp driver board 35 and the sound control board 70. Further, a command may be directly transmitted from the game control means (specifically, the CPU 56) on the main board 31 to the frame side lamp driver board 35 and the sound control board 70.

  In this embodiment, the effect control means (effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the centralized relay board 77. Then, display control of the variable display device 9 for variably displaying special symbols is performed.

  Further, the CPU 56 used in this embodiment includes a non-maskable interrupt terminal (NMI terminal) used for generating a non-maskable interrupt (NMI) that cannot be set to interrupt prohibition by software, And an interrupt terminal (INT terminal) used for generating an external interrupt (external interrupt; maskable interrupt that can be disabled by software). However, this embodiment does not use non-maskable interrupts and external interrupts. Therefore, the NMI terminal and the INT terminal are pulled up to VCC (+5 V) through resistors. Therefore, the input levels of the NMI terminal and the INT terminal are always high, and the input level of the NMI terminal and the INT terminal falls from the high level to the low level due to noise, etc., compared to the case of the terminal open state, and an interrupt occurs The possibility of entering a state is reduced.

  In addition, the main board | substrate 31 is installed in the state accommodated in one board | substrate box in the back side of a gaming machine. The substrate box has a structure that cannot be easily opened.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, the payout control board 37 has a RAM (not shown) as storage means used as a work memory, a ROM (not shown) storing a payout control program, and controls according to the program. A payout control microcomputer (an example of an electrical component control microcomputer) 370 including a payout control CPU 371 to be executed is mounted. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer as long as it has at least a built-in RAM, and the ROM may be external or built-in. The payout control CPU 371, RAM, ROM, I / O port, and the like constitute a payout control means. That is, the payout control means is realized by a payout control microcomputer 370 including a RAM, a ROM, and a payout control CPU 371, and an I / O port. The I / O port may be built in the payout control microcomputer 370. At least a part of the RAM in the payout control microcomputer 370 is backed up by a backup power source mounted on the power supply board 910. In this embodiment, it is assumed that all RAM areas are backed up. Therefore, even when power is not supplied to the gaming machine, the storage contents of the RAM are preserved for a predetermined period (until the backup power supply cannot be supplied because the capacitor as the backup power supply is discharged).

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . The payout control microcomputer 370 mounted on the payout control board 37 receives a detection signal (non-secured detection signal) indicating a ball shortage state from the ball shortage switch 187, and also when a full signal from the full switch 48 is full. When a detection signal (storage detection signal) indicating the tongue state is input, the ball payout process is stopped.

  Further, a detection signal (storage detection signal) indicating a full state from the full tank switch 48 is branched at the payout control board 37 (see FIG. 6), and the payout control microcomputer 370 as a low level fullness signal. Each is input to the launch board 90. A drive signal (launch motor signal) from the game control microcomputer 560 to the launch motor 94 is transmitted to the launch motor 94 via the launch board 90. When the full tank signal is input to the launch board 90, transmission of the drive signal to the launch motor 94 on the launch board 90 is stopped, and the ball launch from the hitting ball launcher is stopped. The full signal branched by the payout control board 37 is inputted to one of the input sides of the AND circuit 91 mounted on the launch board 90, and the launch motor signal from the game control microcomputer 560 is sent from the AND circuit 91. Input to the other input side. Then, the output signal of the AND circuit 91 is input to the firing motor 94. That is, the output of the drive signal to the firing motor 94 is stopped while the full tank signal branched by the payout control board 37 is being output (while it is at the low level).

  In this example, the game control microcomputer 560 is configured to output a drive signal (launch motor signal) to the launch motor 94, but without receiving a signal from the game control microcomputer 560, The launch board 90 may be configured to always output a drive signal to the launch motor 94 as long as power is supplied. Even when the launch substrate 90 always outputs a drive signal, when the full signal is output by the AND circuit 91 or the like, or when the signal from the touch sensor circuit indicates an off state, etc. In that case, the drive signal to the firing motor 94 is stopped.

  When there is a winning at the winning opening, a prize ball control signal indicating the number of prize balls to be paid out is output (turned on) from the output circuit 67 of the main board 31 as a payout command signal. Also, when the game control microcomputer 560 is started up (when the operation is started), a payout start command (payout start command) is output. Then, a prize ball REQ signal (prize ball request signal) for instructing to take in a prize ball control signal or a payout activation command is output (turned on).

  In this embodiment, the winning ball control signal and the payout activation command are transmitted through the same signal line. The winning ball control signal and the payout activation command are composed of 5-bit data (binary 5-digit data) and are output through five signal lines. Note that the ON state of the signal, that is, the output state is a state where the signal is significant, and turning ON means that the signal receiving side is instructed to start some processing based on the signal. To do. For example, when the prize ball control signal indicating the number of prize balls and the prize ball REQ signal are turned on, this means that the dispense control means is instructed to recognize the number of prizes indicated by the prize ball control signal. To do.

  The prize ball control signal and the payout activation command are input to the I / O port 372e via the input circuit 373A. The prize ball REQ signal is input to a maskable interrupt terminal (hereinafter also simply referred to as an interrupt terminal) of the payout control CPU 371. The payout control CPU 371 inputs a prize ball control signal via the I / O port 372e in an interrupt process based on the prize ball REQ signal being inputted to the interrupt terminal, and the number of prize ball control signals indicated by the prize ball control signal. In order to pay out the game ball, the ball paying device 97 is controlled to be driven. A power supply confirmation signal (connection confirmation signal) indicating that the main board 31 is connected is also output from the output circuit 67 of the main board 31.

  In this embodiment, the payout control microcomputer 370 recognizes a prize ball for the main board 31 when the payout of one prize ball is confirmed based on the detection signal from the payout number count switch 301. Send a count signal. Further, the payout control means means an error related to game ball payout (an error indicating that the game ball payout process cannot be performed. When this occurs, a payout error signal is transmitted to the main board 31. The prize ball count signal and the payout error signal are transmitted to the main board 31 via the output port 372b and the output circuit 373B of the payout control board 37. Then, in the main board 31, the data is input to the game control microcomputer 560 via the input circuit 68 and the I / O port 57.

  In addition, a power-off signal indicating that the power supply voltage has dropped below a predetermined value and a clear signal indicating that the clear switch 921 for clearing the contents of the RAM has been operated are input from the power supply board 910 to the input port 372g. Is input.

  The payout control microcomputer 370 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of balls to be rented to a terminal board (frame external terminal board and board external terminal board). Output to 160). Although a driver circuit is installed outside the output port 372b, the description is omitted in FIG.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 by the 7 segment LED via the output port 372c. Further, a signal for instructing lighting / extinguishing is output to the ball break LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, upon detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, a prize ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  The payout control CPU 371 used in this embodiment generates a non-maskable interrupt terminal (NMI terminal) used for generating a non-maskable interrupt (NMI) and a maskable interrupt. And an interrupt terminal (INT terminal) used for the purpose. However, this embodiment does not use non-maskable interrupts. Therefore, the NMI terminal is pulled up to VCC (+5 V) through a resistor. The maskable interrupt is an interrupt that can be controlled so that no interrupt is generated by software. An interrupt based on a signal input to the interrupt terminal is also called an external interrupt.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even when a game ball corresponding to the amount of money is lent out in accordance with coin insertion.

  FIG. 6 is a block diagram illustrating a circuit configuration example for transmitting a signal transmitted and received between the card unit 50 and the payout control board 37. As shown in FIG. 6, the connection signal (VL signal) from the card unit 50 is input to the payout control board 37 via the interface board 66. The VL signal input to the payout control board 37 is input to the payout control microcomputer 370 via the photocoupler 151 mounted on the payout control board 37. A photocoupler is an element that transmits a signal using light as a medium by combining a light emitting element and a light receiving element. The structure consists of a light emitting diode and a phototransistor in one package. Since the input and output are electrically insulated, they are widely used for removing electrical noise. Note that passive elements such as a resistor 152 and capacitors 153 and 154 are connected to the photocoupler 151.

  In this example, the output signal from the photocoupler 151 is branched on the payout control board 37 and input to one of the input sides of the AND circuit 155, and is branched to the other input side of the AND circuit 155 at the payout control board 37. One of the full signals is input. The output of the AND circuit 155 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90. Therefore, when the output signal from the photocoupler 151 is at a low level, or when a low level full signal is output, it is connected to one of the input sides of the AND circuit 91 mounted on the launch board 90. A low level signal is input, and the output of the drive signal to the firing motor 94 is stopped regardless of the state of the firing motor signal input to the other input side of the AND circuit 91.

  A unit operation signal (BRDY signal) from the card unit 50 is input to the payout control board 37 via the photocoupler 66a mounted on the interface board 66, and is input to the payout control microcomputer 370. Similarly, a ball lending request signal (BRQ signal) from the card unit 50 is input to the payout control board 37 via the photocoupler 66b mounted on the interface board 66, and is input to the payout control microcomputer 370.

  Further, a ball lending completion signal (EXS signal) from the payout control microcomputer 370 is input to the card unit 50 via the photocoupler 66 c mounted on the interface board 66. Similarly, a pachinko machine operation signal (PRDY signal) from the payout control microcomputer 370 is input to the card unit 50 via a photocoupler 66 d mounted on the interface board 66.

  Since the photocoupler 151 for transmitting the VL signal transmitted from the card unit 50 to the payout control microcomputer 370 is mounted on the payout control board 37 as described above, the resistance connected to the photocoupler 151 Passive elements such as the condenser 152 and the capacitors 153 and 154 can also be mounted on the dispensing control board 37, and no capacitor can be mounted on the interface board 66. Therefore, when any illegal circuit is attached to the interface board 66 or when the interface board 66 is replaced with an illegal board, the illegal action can be easily detected. In other words, if there is a capacitor on the interface board 66 that should not be mounted at all, it can be determined that some kind of fraud is being performed, and therefore fraud can be easily detected. , Will be able to prevent fraud.

  In a conventional gaming machine, a capacitor is mounted on an interface board as described in, for example, Japanese Patent Application Laid-Open No. 2001-347054 (particularly FIG. 11). Therefore, when a fraudulent board having an illegal circuit for inputting an illegal signal to the payout control microcomputer is created on the interface board and the legitimate interface board is replaced with the illegal board, the board is replaced. There was a problem that it was difficult to discover.

  For example, a fraudulent board is equipped with a fraudulent circuit for inputting a signal for executing a payout operation to the payout control board even though no winning is made or a ball lending request is not made. A substrate is assumed. Then, the unauthorized interface board is illegally attached, and a signal output command is issued from the unauthorized interface board to the payout control board by an operation from the outside of the gaming machine (for example, button operation, wireless communication operation). ) May be illegally acquired to illegally acquire game media. When creating an illegal interface board, a capacitor is required to stabilize a circuit (or a signal output from the illegal interface board) mounted on the illegal interface board, and a passive element such as a capacitor is used. Will be mounted on the unauthorized interface board.

  On the other hand, in this example, since the capacitor is not mounted on the interface board 66 at all, it is easily determined whether or not the board is an illegal board only by checking whether or not the capacitor is mounted on the interface board. be able to. In addition, when the capacitors 153 and 154 of the VL signal line are mounted on the payout control board 37, the photocoupler 151 is also mounted on the payout control board 37, and therefore, between the interface board 66 and the payout control board 37. In this case, it is possible to eliminate unnecessary reciprocation of the signal path, and to save space and reduce the number of wires.

  In the example shown in FIG. 6, only the photocoupler 151 to which the resistor 152 and the capacitors 153 and 154 are connected is mounted on the payout control board 37. However, the card unit 50 and the payout control board 37 All the photocouplers 151 and 66a to 66d that transmit signals transmitted and received between them may also be mounted on the dispensing control board 37. With this configuration, when there is a photocoupler that should not be mounted at all on the interface board 66, it can be determined that some sort of fraud is being performed.

  Further, as described above, the output of the VL signal (lending request accepting apparatus connection signal) from the photocoupler 151 mounted on the payout control board 37 is branched, and the payout control microcomputer 370 and the launch motor 94 are driven. Since it is configured to be input to the firing substrate 90 that transmits the firing motor signal, the driving of the firing motor 94 can be stopped according to the transmission state of the VL signal by the photocoupler 151. As shown in FIG. 5, the VL signal transmitted by the photocoupler 151 branched by the payout control board 37 and transmitted to the launch board 90 and the launch motor signal from the main board 31 are input to the AND circuit 91. Is done. For this reason, in this example, when the VL signal transmitted by the photocoupler 151 is in the off state (low level state), or when the low level full signal is output, the firing motor from the main board 31 is output. Regardless of the signal state, the drive signal of the firing motor 94, which is the output signal from the AND circuit 91, is maintained in the OFF state. Therefore, when the photocoupler 151 is not transmitting the VL signal, the driving of the firing motor 94 is stopped.

  FIG. 7 is a block diagram illustrating a connection state of main boards provided in the gaming machine. In this embodiment, the signal from the main board 31 to the peripheral board (excluding the payout control board 37. The signal is not limited to being formed as a board but includes a terminal board in which a plurality of terminals are arranged). , And output via the central relay board 77. In the example shown in FIG. 7, signals to the information terminal board 34, the decorative lamp board 79 (not shown in FIG. 4) on which the decorative lamp 25 is mounted, and the effect control board 80 are output via the centralized relay board 77. The Note that the detection signals of the respective switches (such as the above-described prize opening switch) provided in the gaming machine are input to the main board 31 via the switch relay board 78.

  7 illustrates the information terminal board 34, the decorative lamp board 79, and the effect control board 80, but there are more boards as peripheral boards for inputting signals from the main board 31. FIG. For example, FIG. 7 shows one decorative lamp substrate 79, but a plurality of decorative lamp substrates are provided in accordance with the installation positions of the lamps or LEDs on the game board 6. For example, one or a plurality of decorative lamp substrates mounted with lamps / LEDs provided around the variable display device 9 are provided, and one or more mounted with lamps / LEDs provided around the winning prize opening A plurality of decorative lamp substrates are provided. Even if a larger number of peripheral boards are provided, it is preferable that the signal output from the main board 31 is output to all the peripheral boards via one centralized relay board 77 as illustrated in FIG. . That is, it is preferable that one central relay board 77 is provided for all peripheral boards. Further, a drive signal from a solenoid circuit 59 (see FIG. 4) that outputs a drive signal to a solenoid as an electrical component that is one of the gaming devices may be routed through the centralized relay board 77.

  Although not shown, the central relay board 77 is accommodated in a board box on the back side of the gaming machine. That is, the central relay board 77 is housed in a board box as a housing means and attached to the gaming machine. The board box has a structure in which a box body in which the central relay board 77 is accommodated is covered with a lid. The box body and the lid are formed of a synthetic resin or the like that can be visually recognized from the outside (for example, transparent). When the lid portion of the substrate box is closed and fixed to the mechanism plate, the surface side of the central relay substrate 77 can be visually recognized through, for example, a transparent lid portion. Further, in the state in which the lid portion of the substrate box is opened, the back surface side of the central relay substrate 77 can be visually recognized through the back surface of the transparent box body, for example. As described above, since the front and back surfaces of the central relay board 77 can be easily seen from the outside of the board box, it is possible to easily investigate whether the central relay board 77 is fraudulent.

  FIG. 8 is an explanatory diagram showing a signal output unit in the main board 31 and components mounted on the centralized relay board 77. As shown in FIG. 8, in the main board 31, the information output circuit 34 that outputs a signal from the basic circuit 53 (specifically, the output port of the game control microcomputer 560) to the information terminal board 34, and the decorative lamp board 79. The lamp circuit 36 that outputs a signal to the output signal and the output buffer circuit 67 (not shown in FIG. 4) that outputs a signal to the effect control board 80 allow the signal to pass only in the direction toward the central relay board 77 (the central relay board). No signal is allowed to pass in the direction from 77 to the main board 31). As the unidirectional circuit, a transistor or an IC circuit is used. Note that the unidirectional circuit may have a current amplification function.

  The signal output from the main board 31 to the central relay board 77 connects the connector 31A mounted on the main board 31, the connector 77A mounted on the central relay board 77, and the connector 31A and the connector 77A. The signal is transmitted to the central relay board 77 by a cable. The central relay board 77 is a signal direction regulating means that allows a signal input from the main board 31 to pass only in the direction toward the peripheral board (no signal is passed in the direction from the peripheral board to the central relay board 77). The unidirectional circuits 74, 75, and 76 are mounted. As the unidirectional circuits 74, 75, 76, for example, diodes or transistors are used. FIG. 8 illustrates a diode. Unidirectional circuits 74, 75, and 76 are provided for each signal.

  In the example shown in FIG. 8, the signal output to the information output circuit 64 is output via the connector 77 </ b> B mounted on the central relay board 77. A signal output to the decorative lamp substrate 79 is output via a connector 77C mounted on the central relay substrate 77. The signal output to the effect control board 80 is output via the connector 77D mounted on the central relay board 77.

  FIG. 8 shows an example in which a signal is output from the main board 31 to the centralized relay board 77 via a single connector, but centralized relaying from the main board 31 via a plurality of connectors and cables is shown. A signal may be output to the substrate 77. Further, in this embodiment, a signal between the main board 31 and the payout control board 27 does not pass through the central relay board 77, but as a signal between the main board 31 and the payout control board 27, from the main board 31. When there is only a signal directed to the payout control board 27, a signal from the main board 31 to the payout control board 27 may be configured to pass through the central relay board 77.

  In addition to the signal direction regulating means, noise removing components such as a noise filter may be mounted on the centralized relay board 77. That is, in the relay board, all the signals input from the game control board (or main signals such as production control commands and INT signals for which noise countermeasures are particularly required, that is, if they are not input correctly, the game progress is hindered. It is preferable that noise removing means is provided for the signal. By mounting the noise removing component, it is possible to reduce the possibility that noise is added to the signal reaching the peripheral board even if the wiring length between the main board 31 and the peripheral board is long. Further, the centralized relay board 77 may be equipped with an amplifying means for amplifying a signal (for example, a current for the signal) input from the game control board. In the case of such a configuration, amplification processing is performed on the relay board, so that the amplification circuit mounted on the game control board can be eliminated.

  FIG. 9 is a block diagram illustrating a circuit configuration example of the effect control board 80, the lamp driver board 35, and the sound control board 70. The lamp driver board 35 and the sound control board 70 are not equipped with a microcomputer. In the effect control board 80, the effect control CPU 101 in the effect control microcomputer 100 (an example of an electrical component control microcomputer) 100 operates according to a program stored in a ROM (not shown), and is connected via a centralized relay board 77. The effect control command is received via the input driver 102 and the input port 103 in response to the strobe signal (symbol control INT signal) from the main board 31 that is input. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the variable display device 9 using the LCD based on the effect control command. The VDP 109 is sometimes called a GCL (graphic controller LSI).

  Note that the input driver 102 passes the signal input from the centralized relay board 77 only in the direction toward the inside of the effect control board 80 (the signal in the direction from the inside of the effect control board 80 to the centralized relay board 77). It is also a unidirectional circuit as a signal direction regulating means.

  Further, the production control CPU 101 outputs sound number data to the sound control board 70 via the output port 104 and the output driver 110. A bus (including an address bus, a data bus, and a control signal line such as a write / read signal) that is input / output to / from the effect control CPU 101 is extended to the lamp driver board 35 via the bus driver 105.

  In the lamp driver board 35, a bus that is input to and output from the effect control CPU 101 is connected to the output port 352 via the bus receiver 351. A signal for driving each lamp output from the output port 352 is amplified by the lamp driver 354 and supplied to each lamp. A signal for driving each LED output from the output port 352 is amplified by the LED driving circuit 355 and supplied to each LED.

  In this embodiment, lamps / LEDs and effect driving means provided in the gaming machine are controlled by effect control means including effect CPU 101 mounted on effect control board 80. Further, data for controlling the variable display device 9, the normal symbol display 10, the lamp / LED and the like are stored in the ROM. The effect CPU 101 controls the variable display device 9, the normal symbol display 10, the lamp / LED, and the like based on the data stored in the ROM. Then, the lamp / LED and the driving means for presentation are driven via the output port 352 and each drive circuit mounted on the lamp driver board 35. Therefore, when changing the model, it is necessary to make a design change such as changing the number of ports for the lamp driver board 35, but for the effect control board 80, it is only necessary to replace the ROM storing the program. There is no need to make design changes.

  Although the production control board 80, the lamp driver board 35, and the sound control board 70 are independent boards, they are installed in a single box on the back of the gaming machine, for example. Further, the expansion port 353 is installed in consideration of the case where the number of lamps / LEDs and the like is increased when changing the model, but it may not be installed.

  In the voice control board 70, the sound number data from the effect control board 80 is input to the voice synthesis IC 703 by a digital signal processor, for example, via the input driver 702. The voice synthesis IC 703 reads data corresponding to the sound number data from the voice data ROM 704, generates voice and sound effects corresponding to the read data, and outputs them to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27.

  The data corresponding to the sound number data stored in the sound data ROM 704 is a collection of data indicating the sound effect or sound output mode in a predetermined time period (for example, a special symbol fluctuation period) in time series. When the voice number IC 703 receives the sound number data, the voice synthesis IC 703 performs sound output control according to the corresponding data in the voice data ROM 704. The sound output control according to the corresponding data is continued until the next sound number data is input. When the next sound number data is input, the speech synthesis IC 703 performs sound output control according to the data in the sound data ROM 704 corresponding to the newly input sound number data.

  In this embodiment, the sound and sound output from the speaker 27 are controlled by the effect control means including the effect control CPU 101, but the effect control means outputs the sound number data to the sound control board 70. . In the voice control board 70, the voice data ROM 704 stores a large amount of data for realizing voice and sound effects that can appear as the game progresses, and these data are associated with the sound number data. . Therefore, the production control means can realize sound output control only by outputting the sound number data. Note that the sound number data is, for example, 1-byte data, and is transferred to the sound control board 70 via a serial signal line or a parallel signal line.

  In this embodiment, one effect control means executes display control of variable display, lamp / LED (light emitting body) lighting control, and sound generation control from the speaker 27. That is, effect control The means realizes effect control means, light emitter control means, and sound control means. Therefore, the display effect by the variable display device 9, the effect using the lamp / LED, and the effect by sound can be easily synchronized. However, in order to lighten the burden on the effect control means, a light emitter control microcomputer and a sound control microcomputer are provided, which are game control means or effect control means (in this case, effect control means). The light emitter may be controlled and the sound may be controlled according to the command.

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the rectifier circuit 912 via the varistor 918 as an overvoltage protection circuit. In other words, power is supplied to the gaming machine.

  The power supply board 910 is installed independently of the electrical component control board (the main board 31 and the payout control board 37 and the like), and generates a voltage used by each board and mechanism component in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line for driving an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the +5 V line and the backup +5 V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL is a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of regulator ICs (two regulator ICs 924A and 924B are shown in FIG. 10), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Accordingly, when the power supply to the gaming machine from the outside is stopped, the DC voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 10, AC24V is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. The cable connected to the connector 922B is connected to the payout control board 37. Therefore, VBB is also supplied to the connectors 922A and 922B. The cable connected to the connector 922C is connected to the frame side lamp driver board 35. Each voltage is supplied to the effect control board 80 and the sound control board 70 via the frame side lamp driver board 35.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. When the clear switch 921 is pressed, a low level (on state) clear switch signal is output and transmitted to the payout control board 37 via the connector 922B. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided in a board other than the power supply board 910 such as the payout control board 37 or other places in the gaming machine.

  Further, the power supply board 910 has a system reset signal for each microcomputer mounted on each electric component control board (the microcomputer operation is prohibited at the reset level, and the microcomputer can be operated when the non-reset level is reached). Power supply monitoring circuit 920 that outputs a power-off signal, and a reset signal from the power-supply monitoring circuit 920 are amplified and output to the connectors 922A, 922B, and 922C, and the power-off signal is amplified. An output driver circuit 925 for outputting to the connector 922B is mounted. The system reset signal for the game control microcomputer 560 and the payout control microcomputer 370 is directly transmitted to the main board 31 and the payout control board 37, but the system reset signal for the effect control microcomputer and the sound control microcomputer. Is transmitted to the effect control board 80 and the sound control board 70 via the frame side lamp driver board 35. However, it may be directly transmitted from the power supply board 910 to each of the effect control board 80, the frame side lamp driver board 35, and the sound control board 70.

  The power supply monitoring circuit 920 is a circuit that realizes power supply monitoring means for outputting a power-off signal and reset signal generation means for generating a system reset signal. As the power supply monitoring circuit 920, a commercially available power failure monitoring reset module IC is used. be able to. The power supply monitoring circuit 920 outputs a power-off signal when a period during which a predetermined voltage (for example, + 24V) used in the gaming machine becomes equal to or lower than a predetermined value (for example, + 17V) continues for a predetermined time (for example, 56 ms). . Specifically, the power-off signal is turned on (low level). Further, the power supply monitoring circuit 920 enters a state where the system reset signal can be set to a low level when, for example, VCC becomes +4.5 V or less.

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the system reset signal to a low level when a predetermined period has elapsed since the power-off signal was output (set to a low level). Become. In addition, when the power supply to the gaming machine is started and VCC exceeds +4.5 V, for example, the system reset signal is set to high level. In this case, after the power-off signal is not output (set to high level). From the condition that the predetermined period has elapsed, the system reset signal is set to the high level.

  The power-off signal from the power monitoring circuit 920 is input to the payout control CPU 371 via the input port 372g in the payout control board 37 (see FIG. 5). Therefore, the payout control CPU 371 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the input signal of the input port 372g.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the voltage from the outside of the gaming machine (this implementation) is used as a detection condition related to the stoppage of the power supplied to the gaming machine from the outside. However, the detection condition is not limited to this, and other conditions can be used as long as it is possible to detect that power from the outside has been cut off These conditions may be used. For example, the AC wave itself may be monitored and the AC wave may be detected as a detection condition, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be stopped when the digital signal becomes flat. May be used as a detection condition.

  11 and 12 are explanatory diagrams showing an example of output port assignment in the game control means. As shown in FIG. 11, the output port 0 is an output port for prize ball control signals (CD0 to CD4) transmitted to the payout control board 37. Further, 8-bit data (CD0 to CD7) of the effect control command transmitted to the effect control board 80 is output from the output port 1.

  Further, from the output port 2, a solenoid (large winning port door solenoid) 21 for opening and closing the opening / closing plate 2 of the large winning port, a solenoid (large winning port guide plate solenoid) 21A for switching the route in the large winning port, and a variable A drive signal is output to a solenoid (normal electric accessory solenoid) 16 for opening and closing the winning ball apparatus 15. Further, an effect control INT signal (strobe signal) for the effect control command transmitted to the effect control board 80 is also output. The effect control INT signal is a signal for instructing the effect control means to take in the 8-bit data of the effect control command. Further, signals of respective phases supplied to the firing motor 94 by the stepping motor are output from the output port 2.

  Then, various information output signals from the output ports 3 and 4 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 13 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 13, bits 0 to 7 of the input port 0 are detected by the V count switch 22, the count switch 23, the gate switch 32a, the winning port switches 33a, 24a, 29a and 30a, and the start port switch 14a, respectively. A signal is input. In addition, bits 0 to 4 of the input port 1 respectively include a power-off signal from the power supply monitoring board 910, a detection signal from the clear switch 921 from the power supply board 910, a prize ball count signal from the payout control board 37, and a payout control. A payout error signal from the substrate 37 and a switch common monitoring signal from the switch common monitoring circuit 71 are input. The detection signal from each switch is logically inverted in the input driver circuit 58. The prize ball count signal and the payout error signal are logically inverted in the input circuit 68.

  Next, the operation of the gaming machine will be described. 14 and 15 are flowcharts showing the main process executed by the game control means on the main board 31. When the gaming machine is turned on and the input level of the reset terminal to which a reset signal is input becomes high, the CPU 56 performs a security check process that is a process for confirming whether the contents of the program are valid. After execution, the main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3).

  Next, a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software is executed. Specifically, first, the initialization wait number specification value 1 is set in the wait counter 1 (step S81). Also, the initialization wait number specification value 2 is set in the wait counter 2 (step S82). Note that general-purpose registers (HL register and BC register) built in the CPU 56 are used as the wait counters 1 and 2. Then, the value of the wait counter 2 is decremented by 1 until the value of the wait counter 2 becomes 0 (steps S83 and S84). When the value of the weight counter 2 becomes 0, the value of the weight counter 1 is decremented by 1 (step S85). When the value of the weight counter 1 is not 0 (step S86), the process returns to step S82. If the value of the wait counter 1 is 0, the software delay process is terminated.

  By the software delay processing as described above, the software delay processing is not executed substantially by [(initialization wait number specification value 1) × (initialization wait number specification value 2) × (processing time of steps S83, S84)]. Compared to the case, the start timing of the game control process can be delayed. In other words, the initialization weight count designation values 1 and 2 are determined so that the start timing of the game control process can be delayed by a desired time. Note that the values of the initialization wait times designation values 1 and 2 are set in the ROM 54. Further, the software delay processing described here is an example, and the software delay processing may be realized by other methods.

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) as built-in devices (built-in peripheral circuits). A clock / timer trigger input CLK / TRG 2 and 3 and two timer outputs ZC / TO 0 and 1 are provided.

  When the software delay processing is completed, the built-in device registers are initialized (settings such as input / output assignment of the built-in devices) and the built-in devices CTC (counter / timer) and PIO (parallel input / output port) Perform (step S4). The initialization of PIO is, for example, setting an off state value to all bits of the output port. The initialization of the CTC is a timer mode setting or the like.

  The CPU 56 used in this embodiment is provided with the following three modes as maskable interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 56 executes a payout start command transmission process for transmitting a payout start command (payout start command) to the payout control board 37 (step S5), and then sets the RAM 55 in an accessible state (step S6).

  Then, the CPU 56 confirms the state of the output signal of the clear switch 921 input via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes a normal initialization process (steps S10 to S15). When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. Note that in the input port 1, the clear switch signal is in the high level. Further, for example, the game clerk can easily execute the initialization process by starting the power supply to the gaming machine (for example, turning on the power switch 914) while turning the clear switch 921 on. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. If it is confirmed that such protection processing has been performed, the CPU 56 determines that there is a backup. When it is confirmed that such a protection process has not been performed, the CPU 56 executes an initialization process.

  Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is merely an example. For example, a flag indicating that the data protection process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that there is a backup, it may be determined that there is backup.

  If it is determined that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the processes of steps S10 to S15) executed when the power is turned on, not when the power supply is stopped. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The portion that should not be initialized is, for example, a portion in which data (such as a special symbol process flag) indicating a gaming state before stopping power supply or data indicating the number of unpaid prize balls is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and power is supplied to the sub boards (the payout control board 37 and the effect control board 80) according to the contents. Control is performed so that a control command indicating the recovery is transmitted (step S94). Then, the process proceeds to step S15.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by unauthorized means. Therefore, it is difficult to aim at the timing at which the count value of the counter matches the jackpot determination value. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12). By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total prize ball number storage buffer, a special symbol process flag, an award ball flag, a ball break An initial value is set for a flag for selectively performing processing according to a control state, such as a flag or a payout stop flag.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  In step S15, the CPU 56 sets a CTC register built in the CPU 56 so that a timer interrupt is periodically generated every predetermined time (for example, 4 ms). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18). The CPU 56 disables the interrupt when the display random number update process and the initial value random number update process are executed (step S16), and interrupts when the display random number update process and the initial value random number update process are finished. The permission state is set (step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. It is. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). Game control processing described later (a game control microcomputer controls a game device such as a variable display device 9, a variable winning ball device, a ball payout device, etc. provided in the gaming machine, or other In the process of transmitting a command signal to cause the microcomputer to control, also referred to as a gaming device control process), when the count value of the big hit determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set even when the display random number update process and the initial value random number update process are performed by the timer interrupt process described later. This is to avoid conflict with the processing in the timer interrupt processing. That is, if a timer interrupt is generated during the processing of steps S17 and S18 and the count value of the counter for generating the display random number and the initial value random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt disabled state is set during the processes of steps S17 and S18.

  FIG. 16 is a flowchart showing the payout activation command transmission process in step S5. In the payout activation command transmission process, the CPU 56 outputs [1, 0, 0, 0, 0] (the position of “1” is bit 4) to the lower 5 bits of the output port 0 (see FIG. 11) (step S51). ). That is, a payout activation command is output to the output port 0 as a 5-bit prize ball control signal. Next, bit 6 of the output port 0 is set to “0” (step S52). That is, the prize ball REQ signal is turned on. Then, a delay process for setting the ON time of the prize ball REQ signal is performed by software (step S53). In this delay processing, for example, a value corresponding to the delay time is set in a general-purpose register (HL register or BC register), and processing for decrementing the register value by −1 is repeatedly executed, so that the register value becomes zero. Then, the process ends. The delay time is set to a time sufficient for the payout control CPU 371 to recognize that the prize ball REQ signal has been input to the interrupt terminal.

  Then, bit 6 of the output port 0 is set to “1” (step S54). That is, the prize ball REQ signal is turned off. Thereafter, the lower 5 bits of the output port 0 are set to [0, 0, 0, 0, 0] (step S55). That is, all 0 is output as the prize ball control signal.

  FIG. 17 is a timing diagram showing how the microcomputer operates when power supply to the gaming machine is started and when power supply is stopped. When power supply to the gaming machine is started and the voltage of the DC + 24V power supply exceeds a predetermined value, the power-off signal is turned off. When the value of VCC exceeds a predetermined value, the reset signal becomes high level. As described above, the power supply monitoring circuit 920 sets the reset signal to high level after turning off the power-off signal. The reset signal is input to the main board 31 and the payout control board 37 and is input to the effect control board 80 via the lamp driver board 36. Then, it is input to the reset terminal of the payout control CPU 371 mounted on the payout control board 37 and the effect control CPU 101 mounted on the effect control board 80.

  When the reset signal input to the main board 31 is input to the reset terminal of the CPU 56 (when the input level of the reset terminal becomes high level), the CPU 56 is ready to operate (the microcomputer is reset and the program is executed). However, when the operation is enabled, the CPU 56 first executes a security check process for confirming whether or not the contents of the ROM are valid based on the security check program. When the security check process ends, a software delay process is executed. Thereafter, a payout activation command transmission process is executed, and then a check process of the output signal state of the clear switch 921 is performed, and then a game control process is started. If the output signal of the clear switch 921 indicates an on state, RAM clear processing or the like is performed.

  The payout control CPU 371 becomes operable when the reset signal becomes high level. When in an operable state, first, a part of the initial setting process is executed. Thereafter, it waits for the payout activation command to be transmitted from the main board 31. When the payout activation command is received, the state of the output signal of the clear switch 921 is checked, and then the game control process is started. If the output signal of the clear switch 921 indicates an on state, RAM clear processing or the like is performed.

  The CPU 56 transmits a payout start command immediately before performing the process of checking the output signal state of the clear switch 921, and the payout control CPU 371 checks the state of the output signal of the clear switch 921 after confirming the payout start command. . Further, when the CPU 56 starts the payout activation command transmission process by executing the security check process and the software delay process, the payout control CPU 371 waits for the payout start command to be transmitted.

  Therefore, for example, there may occur a situation in which the CPU 56 does not check the state of the output signal of the clear switch 921 even though the payout control CPU 371 checks the state of the output signal of the clear switch 921. Is prevented. Conversely, the CPU 56 prevents the situation where the payout control CPU 371 does not check the output signal state of the clear switch 921 even though the output signal state check processing of the clear switch 921 has been performed. Is done. That is, the contents of each variation data storage means in both the game control microcomputer 560 and the payout control microcomputer 370 can be reliably initialized based on the operation of the operation means.

  When the power supply to the gaming machine is stopped, the voltage of the DC + 24V power supply also gradually decreases. However, when the voltage of the DC + 24V power supply falls below a predetermined value, the power supply monitoring circuit 920 outputs a power-off signal (set to a low level). ). The power-off signal is input to the main board 31 and the payout control board 37. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37, according to the power-off signal being output, the power supply stop process (both power-off control process) Say). The power supply monitoring circuit 920 sets the reset signal to a low level when VCC falls below a predetermined value. The game control means mounted on the main board 31 and the payout control means mounted on the payout control board 37 are system reset in response to the reset signal becoming low level. That is, the CPU 56 and the payout control CPU 371 are not operated. The power supply monitoring circuit 920 sets the reset signal to a low level when a predetermined time elapses from the time when the power supply cutoff signal is output when the power supply voltage decreases.

  Next, the game control process will be described. FIG. 18 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, during the execution of the loop process of steps S16 to S19, the CPU 56 performs a timer interrupt process that is activated in response to the occurrence of the timer interrupt. A game control process is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Further, an excitation pattern output process for the firing motor 94 (output of the patterns of the firing motors φ1 to φ4 to the output port 0) is performed (step S21). In the firing motor control process in step S42, the excitation pattern is stored in the excitation pattern buffer that is a RAM area. In step S21, the CPU 56 performs a process of outputting the contents of the excitation pattern buffer to the upper 4 bits of the output port 2. Do.

  Next, the CPU 56 executes a firing motor control process (step S22). In the firing motor control process, the patterns of the firing motors φ1 to φ4 are stored in the excitation pattern buffer.

  Next, the CPU 56 inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a through the switch circuit 58, and determines their states. (Switch processing: step S23). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Further, the CPU 56 executes a process for notifying the player that the prize ball has been paid out in response to the reception of the prize ball count signal from the payout control board 37 (step S24a). Specifically, the CPU 56 executes a process of transmitting a prize ball payout confirmation designation command to the effect control board 80 for designating that the prize ball has been paid out (see FIG. 26). Further, the CPU 56 indicates that an error of out of ball and full of the lower pan (or either out of the ball or full of the lower pan) occurs according to the on / off state of the payout error signal from the payout control board 37. Is executed to notify the player (step S24b). Specifically, when the payout error signal from the payout control board 37 is turned on, the CPU 56 transmits an error occurrence notification command for notifying the occurrence of an error such as a ball break to the effect control board 80 (see FIG. 27). When the payout error signal from the payout control board 37 is turned off, an error release notification command for notifying that an error such as a ball break has been released is transmitted to the effect control board 80 (see FIG. 27). ).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating each determination random number such as a jackpot determination random number used for game control (step S25). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (steps S26 and S27).

  Further, the CPU 56 performs special symbol process processing (step S28). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, the CPU 56 performs normal symbol process processing (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the special symbol in a predetermined area of the RAM 55 and sending the effect control command (special symbol command control process: step S30). In addition, a process for setting an effect control command related to the normal symbol in a predetermined area of the RAM 55 and sending the effect control command is performed (normal symbol command control process: step S31).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S32).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S33). Specifically, a prize ball control signal indicating the number of prize balls is output to the payout control board 37 in response to detection of a prize based on the fact that the prize opening switches 29a, 30a, 33a, 39a, etc. are turned on. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to a prize ball control signal indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start winning memory | storage number (step S34). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S35). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to the solenoid in the RAM area of the output port 2 (see FIG. 11). Is output to the output port (step S36: solenoid output processing). Thereafter, the interrupt permission state is set (step S37), and the process ends.

  With the above control, in this embodiment, the game control process is started periodically (for example, every 4 ms). In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed. Further, the processing of steps S21 to S37 (excluding steps S32 and S35) corresponds to a game control process for controlling the progress of the game.

  19 and 20 are flowcharts illustrating an example of the power-off process in step S20. In the power-off process, the CPU 56 first checks whether or not a power-off signal is output (whether it is in an on state) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer formed in the RAM 55 is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop processing after step S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process (the power-off control process) for saving the game state is executed.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even if the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer formed in the RAM 55 is stored by the backup power source for a predetermined period even if the power supply to the gaming machine is stopped. Therefore, in step S8 in the main process, it is possible to confirm that the processing result of the power supply stop process is stored because the value of the backup monitoring timer is the same value as the determination value.

  In the power supply stop process, the CPU 56 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the value of the pointer is incremented by 1 (step S459), and the value of the checksum calculation count is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the internal RAM 55 cannot be accessed.

  Further, the CPU 56 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The CPU 56 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). When the power-off signal is turned off, the execution address at power-on (address in step S1) is set as the return address and the return command is executed (step S483). That is, the process returns to the main process. Specifically, a state in which a gaming device provided in the gaming machine is controlled (a concept including both controlling by itself and sending a command signal to cause another microcomputer to control). Return.

  When the power supply is stopped by the above process, the power supply stop process in steps S454 to S481 is executed, and data indicating that the power supply stop process has been executed (specified value with backup and checksum) Is stored in the backup RAM, the RAM access is disabled, the output port is cleared, and the timer interrupt for executing the game control process is disabled.

  In this embodiment, the entire area of the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when power supply to the gaming machine is stopped). Therefore, the checksum based on the contents of the RAM 55 when the power-off signal is output is stored in the RAM 55 together with the value of the backup monitoring timer by the processing in steps S452 to S479. After the power supply to the gaming machine is stopped, when the power supply is restored within a predetermined period, the game control means performs the data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S91 to S94 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S10 to S14 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in the entire area of the RAM 55). Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped. The entire area of the RAM 55 may not be backed up by power, but only the area for storing data for returning the gaming state to the state immediately before the power supply is stopped may be backed up.

  When the power-off signal is turned off, the process returns to step S1. In this case, since data indicating that the power supply stop process has been executed is set, the game state recovery process of steps S91 to S94 is executed. Therefore, when the detection signal from the power supply monitoring unit is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  The connection confirmation signal transmitted to the payout control board 37 is set to the off state by the process of clearing the output port. In the setting of the work area in steps 82 and S12, the content of the output port buffer corresponding to the connection confirmation signal is set to a value corresponding to the ON state of the connection confirmation signal. When the prize ball processing in step S31 is executed, the contents of the output port buffer are output to the output port, so that the connection confirmation signal to the payout control board 37 is turned on. Therefore, the connection confirmation signal is output (turned on) during the prize ball processing after the main board 31 rises. Note that the connection confirmation signal is also output when the power supply is recovered from an instantaneous power interruption or the like.

  Next, the switch process (step S23) in the main process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 21 is an explanatory diagram showing each 1-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 22 is a flowchart illustrating a processing example of the switch processing in step S23 in the game control processing. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 13) (step S101), and sets the input data in the port buffer (step S102). Next, an initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer (step S106). S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S14 and S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S14 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The CPU 56 further performs a logical product for each bit between the operation result of the exclusive OR and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined as (by the logical product operation) remains as “1”.

  Then, the CPU 56 sets the operation result of the logical product in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the operation result in step S108 is set in the previous port buffer (step S112). .

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Next, control signals transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 23 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means and a control signal input from the payout control means to the game control means. In this embodiment, a plurality of types of control signals are transmitted and received between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 23, the connection confirmation signal is output when the main board 31 rises (when the game control means starts the game control process), indicating that the main board 31 has risen with respect to the payout control board 37. This is a signal for notification (connection confirmation signal for the main board 31). The connection confirmation signal indicates that the winning ball can be paid out. In this embodiment, since the game control means transmits the payout activation command before starting the game control process, the connection confirmation signal need not be used. When the connection confirmation signal is not used, the payout activation command also serves as a signal indicating that the prize ball can be paid out.

  The prize ball REQ signal is a signal that is in an output state (= ON state) when a prize ball is requested to be dispensed or when a dispensing activation command is transmitted. In addition, the prize ball REQ signal is in a stopped state (off state) after a predetermined period after being in the output state. The award ball control signal is used as a signal (award ball number command) output for designating the number of game balls (1 to 15) for which a payout request is made.

  The award ball count signal is a signal that is turned on when the payout control means confirms the payout of one prize ball, and is turned off after a predetermined period of time has elapsed. The payout error signal is a signal that is turned on when an error state relating to payout occurs and is turned off when the error state is canceled.

  FIG. 24 is a block diagram showing signal lines and the like used for transmission / reception of each control signal shown in FIG. As shown in FIG. 24, the connection confirmation signal, the prize ball REQ signal, and the prize ball control signal are output by the CPU 56 via the output circuit 67 and input to the payout control CPU 371 via the input circuit 373A. The prize ball count signal and the payout error signal are output by the payout control CPU 371 via the output circuit 373B and input to the CPU 56 via the input circuit 68. Each of the connection confirmation signal, the prize ball REQ signal, the prize ball count signal, and the payout error signal is 1-bit data, and is transmitted through one signal line. The prize ball control signal designates 1 to 15 prize ball payouts, and is also used as a payout start command, so is composed of 5-bit data and transmitted through five signal lines.

  FIG. 25 is a timing chart showing an example of how to output a prize ball control signal. As shown in FIG. 25, the game control means transmits a payout start command (payout start command) to the payout control means in connection with the start of power supply to the gaming machine. Specifically, 10 (H) is output as the prize ball control signal, and the prize ball REQ signal is turned on.

  When the winning detection switch detects the winning of the game ball, the game control means turns on the winning ball REQ signal and sets the output state of the winning ball control signal according to the number of winning balls to be paid out according to the winning. To the state. In this embodiment, when a game ball is detected by the start port switch 14a, four prize balls are paid out, and when a game ball is detected by any one of the prize port switches 33a, 39a, 29a, 30a. Seven prize balls are paid out. When a game ball is detected by the V count switch 22 or the count switch 23, 15 prize balls are paid out. As described above, since the prize ball control signal is composed of 5 bits, the lower 5 bits of the prize ball number commands of 00 (H) to 0F (H) represented by 8 bits are A prize ball control signal is transmitted from the main board 31 to the payout control board 37. Hereinafter, the prize ball control signal may be expressed as “00 (H) to 0F (H) prize ball control signal”, but in reality, the prize ball control signal is represented by 8 bits. This corresponds to the lower 5 bits of 0F (H). When the prize ball control signal is used to transmit the number of prize balls to be paid out in accordance with winning, the most significant bit (bit 4) is 0.

  FIG. 26 is a timing chart showing an example of how to output a prize ball count signal. As shown in FIG. 26, when the payout number count switch 301 detects the payout of the game ball, the payout control CPU 371 checks whether or not the detection is the detection of the payout of the prize ball, and can detect the payout of the prize ball. For example, the prize ball count signal is turned on for a predetermined period (for example, 0.5 seconds). That is, each time a payout of one prize ball is confirmed, the prize ball count signal is turned on for a predetermined period. Therefore, for example, the payout count switch 301 detects the payout of seven game balls. If the detected game ball is a prize ball, the on / off of the prize ball count signal is repeated seven times.

  In each of the above-described prize ball notification processing (step S24a), the CPU 56 receives a prize ball payout confirmation designation control command (award ball payout) indicating that a prize ball has been paid out each time a prize ball count signal is received. Confirmation designation command) is transmitted to the effect control board 80 (see the prize ball notification process in step S24a). The production control microcomputer 100 mounted on the production control board 80 sends a command signal for controlling the driving (lighting) of the lamp to the frame side lamp driver board 35 based on the received prize ball payout confirmation designation command. (In the command analysis process in step S324, a command signal is output to the frame-side lamp driver board 35 in response to reception of a prize ball payout confirmation designation command). The lamp driver 354 of the frame side lamp driver board 35 executes control for lighting the prize ball lamp 51 for a predetermined period (for example, 0.5 seconds) every time a prize ball payout confirmation designation command is received.

  Note that the CPU 56 is not limited to a configuration that transmits a prize ball payout confirmation designation command indicating that the payout of one prize ball has been confirmed to the effect control board 80 every time a prize ball count signal is received. For example, when a predetermined number (for example, 7) of winning ball count signals indicating a predetermined number (for example, 7) of winning balls are received, confirmation of a predetermined number (for example, 7) of winning balls is confirmed. A prize ball payout confirmation designation command indicating that the game has been performed may be transmitted to the effect control board 80, and the payout of the first prize ball out of a predetermined number (for example, 7) prize balls to be paid out In response to receiving a prize ball count signal based on the detection of a prize ball, a prize ball payout confirmation designation command indicating that a predetermined number (for example, 7) of prize balls has been paid out is confirmed. Send to Unishi may be. In this case, the production control microcomputer 100 confirms the payout of one prize ball as described above when receiving the prize ball payout confirmation designation command indicating that the payout of the predetermined number of prize balls has been confirmed. It is preferable to execute control to turn on the prize ball lamp 51 for a longer period (for example, 3 seconds) than when the prize ball payout confirmation designation command indicating that the game has been received.

  FIG. 27 is a timing chart showing an example of how to output a payout error signal. As shown in FIG. 27, the payout control CPU 371 turns on the payout error signal when it shifts to the error state, and turns off the payout error signal when the error state is canceled. In this example, a payout error signal is output when an error state occurs due to the occurrence of an error related to payout of a game ball. Specifically, for example, a payout error signal is output when the lower pan is full or the ball is out.

  As shown in FIG. 27, when the CPU 56 mounted on the main board 31 receives an error signal from the payout control CPU 371 (when the error signal is turned on), the CPU 56 sends an effect control command to the effect control board 80. Send an error occurrence notification command. The error occurrence notification command is a command indicating that an error has occurred. Further, when the error signal from the payout control CPU 371 is stopped (when the error signal is turned off), the CPU 56 transmits an error release notification command as an effect control command to the effect control board 80. The error release notification command is a command indicating that the error state has been released.

  When receiving the error occurrence notification command from the CPU 56, the effect control CPU 101 mounted on the effect control board 80 displays the error display on the variable display device 9 and executes a process of notifying the error condition. To do. The notification of the error state is performed by displaying, for example, characters or figures such as “An error has occurred!” In the display area of the variable display device 9. In addition, when receiving the error release notification command from the CPU 56, the production control CPU 101 deletes the error display displayed on the variable display device 9 to notify that it is in an error state, and is in an error state. Is terminated. As described above, the error notification is made when an error state occurs, so that the player or the game clerk can be easily notified that the error has occurred.

  FIG. 28 is a flowchart illustrating an example of the prize ball processing in step S33. In the prize ball process, the CPU 56 executes a prize ball number addition process (step S201) and a prize ball control process (step S202). Then, the contents of the port 0 buffer formed in the RAM 55 are output to port 0 (step S203). The contents of the port 0 buffer are updated in the prize ball control process.

  In the winning ball number adding process, a winning ball number table shown in FIG. 29 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “7”) is set in the head address of the winning ball number table, and then the lower address of the switch-on buffer, and each switch of the winning opening that will pay out the winning ball by winning. The switch input bit determination value and the number of winning balls are sequentially set corresponding to each switch of the winning opening. The switch input bit determination value is a value corresponding to the bit to which the detection signal of each switch at the input port 0 is input (see FIG. 13). The upper address of the switch-on buffer is a fixed value (for example, 7F (H)).

  FIG. 30 is a flowchart showing the prize ball number adding process. In the winning ball number adding process, the CPU 56 sets the start address of the winning ball number table in the pointer (step S211). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S212). Next, the upper address (8 bits) of the switch-on buffer is set in the upper 1 byte of the 2-byte check pointer (step S213).

  Then, the pointer value is incremented by 1 (step S214), and the data of the prize ball number table pointed to by the pointer (in this case, the lower address of the switch-on buffer) is set in the lower 1 byte of the check pointer (step S215). The pointer value is increased by 1 (step S216). Next, the address data pointed to by the check pointer, that is, the contents of the switch-on buffer is loaded into the register (step S217), and the loaded contents and the data of the prize ball number table pointed to by the pointer (in this case, the switch input bit judgment value) ) And the logical product (step S218). As a result, 7 bits other than the bit corresponding to the detection signal of the switch to be inspected become 0 in the register loaded with the contents of the switch-on buffer. Then, the pointer value is incremented by 1 (step S219).

  If the calculation result in step S218 is 0, that is, if the detection signal of the switch to be inspected is on, the prize ball number table data pointed to by the pointer (in this case, the prize ball number) is used as the prize ball addition value. (Steps S220 and S221), and the prize ball addition value is added to the contents of the 16-bit total prize ball number storage buffer formed in the RAM 55 (step S222). The total winning ball number storage buffer is formed in the backup RAM. If a carry occurs as a result of the addition, the content of the total number of winning balls storage buffer is set to 65535 (= FFFF (H)) (steps S223 and 224). Further, “formed in RAM” means an area in the RAM.

  In step S225, the number of processes is reduced by 1. If the number of processes is 0, the process ends. If the number of processes is not 0, the process returns to step S214 (step S226). In step S220, when it is confirmed that the calculation result in step S218 is 0, that is, the detection signal of the switch to be inspected is in the OFF state, the process proceeds to step S225.

  FIG. 31 is a flowchart showing the prize ball control process in step S201. In the prize ball control process, the CPU 56 executes any one of steps S231 to S234 according to the value of the prize ball process code.

  FIG. 32 is a flowchart showing the prize ball waiting process 1 (step S231) executed when the value of the prize ball process code is zero. In the award ball waiting process 1, the CPU 56 sets the award ball waiting output value (30 (H)) in the port 0 buffer (step S243). When the prize ball waiting output value is set in the port 0 buffer, the contents of the port 0 buffer are output to port 0 in step S203, whereby the prize ball REQ signal is turned off, and the connection confirmation signal The on state is maintained (see FIG. 11). In addition, the prize ball control signal enters an invalid command (00 (H)). Next, it is confirmed whether or not the prize ball timer is 0 (step S244). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S245), and the process is terminated. The prize ball timer is a timer for measuring the time required for prize ball processing. At this stage, if the value of the prize ball timer is not 0, the next prize ball after the previous payout process is completed. Waiting time until the REQ signal is turned on (time for providing an interval between ON periods of a plurality of prize ball REQ signals when prize ball payout is continuously executed, 00 (H ) Means that the prize ball control signal is being output).

  The prize ball timer is set in step S275 of the prize ball waiting process 3 described later. In addition, after the execution of the prize ball process 3 in step S234 is completed and the previous payout process is completed, the process of steps S243 to S245 sets the prize ball REQ signal to the OFF state and the invalid command as the prize ball control signal. This is a process for outputting (00 (H)).

  If the value of the prize ball timer is 0, the CPU 56 confirms the contents of the total prize ball number storage buffer (step S247). If the value is 0, the process ends. If not, the value of the prize ball process code is set to 1 (step S248), and the process ends.

  FIG. 33 is a flowchart showing a prize ball transmission process (step S232) executed when the value of the prize ball process code is 1. In the prize ball transmission process, the CPU 56 checks whether or not the content of the total prize ball number storage buffer is smaller than the prize ball command maximum value (“15” in this example) (step S251). If the content of the total prize ball number storage buffer is equal to or greater than the prize ball command maximum value, the prize ball command maximum value is set in the prize ball number buffer (step S252). If the content of the total prize ball number storage buffer is smaller than the maximum value of the prize ball command, the content of the total prize ball number storage buffer is set in the prize ball number buffer (step S253).

  Thereafter, the CPU 56 sets the output value (10 (H)) during the prize ball REQ in the output port 0 buffer (step S254). When the output value in the prize ball REQ is set in the output port 0 buffer, the contents of the output port 0 buffer are outputted to the port 0 in step S203, so that the prize ball REQ signal is turned on and the connection confirmation is made. The on state of the signal is maintained (see FIG. 11). Further, the contents of the winning ball number buffer are set in the lower 4 bits of the output port 0 buffer (step S255). Further, a prize ball processing waiting time is set in the prize ball timer (step S256). The award ball processing waiting time is, for example, a time predetermined as a period sufficient for completing the award ball payout control on the payout control board 37. Thereafter, the value of the prize ball process code is set to 2 (step S257), and the process is terminated.

  In this embodiment, the maximum value of the prize ball command is “15”. Accordingly, a prize ball control signal designating the maximum number of payouts of “15” is transmitted to the payout control board 37.

  FIG. 34 is a flowchart showing the winning ball waiting process 2 (step S233) executed when the value of the winning ball process code is 2. In the award ball waiting process 2, the CPU 56 checks whether or not the award ball timer is 0 (step S263). If the prize ball timer is not 0, the value of the prize ball timer is decreased by 1 (step S264), and the process is terminated. If the value of the prize ball timer is not 0 at this stage, it means that the payout process of the number of prize balls instructed to the payout control means is not completed.

  If the value of the prize ball timer is 0, the CPU 56 determines that the prize ball payout for the number instructed to the payout control means has been completed, and from the contents of the total prize ball number storage buffer, the contents of the prize ball number buffer. The number of prize balls paid out instructed to the payout control means is subtracted (step S265). Then, the value of the prize ball process code is set to 3 (step S266), and the process is terminated. Whether or not the number of prize balls paid out to the payout control means has been completed is output for the number of prize balls paid out to the payout control means after outputting the prize ball REQ signal without using the prize ball timer. The determination may be made based on whether or not a prize ball count signal is received.

  In the prize ball transmission process shown in FIG. 33 and the prize ball waiting process 2 shown in FIG. 34, the game control means transmits the prize ball control signal and then receives a prize ball from the payout control means within a predetermined period. When the count signal is not received the number of times corresponding to the number specified by the prize ball control signal, it is configured to perform control for stopping the progress of the game, assuming that an abnormality in communication with the payout control means has occurred. May be.

  The game control means stores the current control state, for example, the output state of the output port, in the RAM 55 before stopping the progress of the game, and then clears the output state of the output port. Then, the progress of the game is stopped until the abnormality of communication with the payout control means is resolved. That is, even if a new event (game ball winning or the like) occurs, processing corresponding to the new event is not performed, for example, a newly generated event is stored. Note that the game control means transmits a communication error display command to the effect control means of the effect control board 80 in order to notify the occurrence of communication abnormality using the variable display device 9 or the like before stopping the progress of the game. It may be configured. When the communication abnormality is resolved, the game control means can restore the output port based on the control state stored in the RAM 55.

  FIG. 35 is a flowchart showing the prize waiting process 3 (step S234) executed when the value of the prize ball process code is 3. In the award ball waiting process 3, the CPU 56 sets the award ball REQ waiting time in the award ball timer (step S275). Then, the value of the prize ball process code is set to 0 (step S276), and the process is terminated.

  With the above processing, the game control means stores the total number of game balls as prize balls to be paid out based on the establishment of the payout condition in the total prize ball number storage buffer so as to be specified (see step S222). The total award ball number storage buffer corresponds to a prize game medium number storage means capable of storing stored contents for at least a predetermined period by a backup power source even when power supply to the gaming machine is stopped. Further, the game control means transmits a payout command signal designating a payout number of a predetermined number of prize balls to the payout control means based on the number of prize balls stored in the total prize ball number storage buffer (step S253). , S255, S203). Then, when the game control means transmits a payout command signal, it determines from the number of prize balls stored in the total prize ball number storage buffer after determining that the number of prize balls paid out to the number commanded to the payout control means has been completed. A subtraction process for subtracting the number of payouts specified by the payout command signal is performed (see step S265). It is to be noted that, after confirming whether or not the number of prize balls paid out to the number designated to the payout control means has been completed, the payout number is immediately calculated from the number of prize balls stored in the total prize ball number storage buffer. Subtraction processing for subtracting the number of payouts specified by the command signal may be performed. Further, before transmitting the payout command signal, a subtraction process may be performed in which the payout number specified by the payout command signal is subtracted from the number of prize balls stored in the total prize ball number storage buffer.

  In this embodiment, as the prize game medium number storage means for storing the total number of prize game media to be paid out based on the establishment of the payout condition, a total prize ball number storage buffer for storing the total number itself is exemplified. However, the prize game medium number storage means for storing the total number of prize game media in an identifiable manner stores the number of prizes received in each prize area or the number of prizes for each prize area (for example, 4). The number of winning holes 14 corresponding to the number of winning balls, the number of winning holes 33, 39, 29, 30 corresponding to the number of 7 winning balls, and the number of winning prizes corresponding to the number of 15 winning balls, , The number of winning prizes for which the winning ball payout has not ended yet) may be stored.

  Next, the operation of the payout control means (the payout control CPU 371 and peripheral circuits such as ROM and RAM) will be described. FIG. 36 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 36, the output port 0 is an output port for outputting a signal of each phase supplied to the payout motor 289 by the stepping motor. The output port 1 is an output port for outputting a ball break LED 52, an award ball signal output to the outside of the gaming machine, prize ball information, ball lending information, and a gaming machine error status signal.

  The output port 2 is an output port of each segment output of the error display LED 374 by 7 segment LED. The output port 3 is an output port for outputting an EXS signal and a PRDY signal to the card unit 50. The output port 3 is a port for outputting a prize ball count signal and a payout error signal.

  FIG. 37 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 37, a 5-bit prize ball control signal is input to bits 0 to 4 of the input port 0, and a connection confirmation signal from the main board 31 and a payout motor position are respectively input to bits 5 and 7. A detection signal of the sensor 295 is input. The prize ball REQ signal from the main board 31 is input to the interrupt terminal of the payout control CPU 371 without going through the input port. In addition, the detection signal of the payout number count switch 301, the operation signal from the error release switch 375, and the detection signal of the full switch 48 are input to bits 1 to 3 of the input port 1, respectively. The VL signal, the BRDY signal, the BRQ signal, and the detection signal of the ball break switch 187 from the card unit 50 are input to bits 4 to 7 of the input port 1, respectively. An output signal and a power-off signal from the clear switch 921 from the power supply board 910 are input to the input port 2.

  FIG. 38 is a timing chart for explaining communication between the payout control means of the gaming machine and the card unit 50. The payout control means turns on the PRDY signal when power supply to the gaming machine is started and a payout operation is possible. When the power supply is started, the card unit 50 turns on the VL signal as a connection signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit 50 outputs a BRDY signal to the payout control means. That is, the BRDY signal is turned on. When a predetermined delay time elapses from this point, the card unit 50 outputs a BRQ signal to the payout control means. That is, the BRQ signal is turned on.

  Then, when the payout control means turns on the EXS signal for the card unit 50 and detects the fall (off) of the BRQ signal from the card unit 50, the payout control unit 289 drives the payout motor 289 to set a predetermined number (for example, 25). Pay out the rental balls to the player. Then, when the payout is completed, the payout control means causes the EXS signal to the card unit 50 to fall. That is, the EXS signal is turned off.

  Next, the operation of the payout control means will be described. FIG. 39 is a flowchart showing main processing executed by the payout control means. When power is turned on to the gaming machine and the input level of the reset terminal to which a reset signal is input becomes high, the payout control CPU 371 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  The payout control CPU 371 initializes the built-in device register (step S704), and initializes CTC and PIO (step S705).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S704 and the process in step S705, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 2 ms, a value corresponding to 2 ms is set as an initial value in a predetermined register (time constant register).

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC.

  The interrupt based on CTC channel 3 (CH3) count-up is an interrupt generated when the CPU internal clock (system clock) is counted down and the register value becomes “0”, and is used as a timer interrupt. . Specifically, a clock obtained by dividing the operation clock of the CPU 371 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. The processing so far corresponds to a part of the initial setting processing shown in FIG.

  Next, the payout control CPU 371 sets a value corresponding to a monitoring time for confirming that a payout start command is transmitted from the main board 1 in a general-purpose register (HL register or BC register) (step S720). .

  The payout control CPU 371 is an external register that is a register that reflects the state and is one of the specific registers when a signal having a level (in this example, low level) that causes an interrupt is input to the interrupt terminal. A CPU having an interrupt request register. In this embodiment, it is assumed that bit 7 of the external interrupt request register is set to “1” when a signal of a level that causes an interrupt is input to the interrupt terminal. That is, the value of the external interrupt request register is updated to 80 (H). The setting / resetting of the bits of the external interrupt request register cannot be executed by software, but is performed by an internal mechanism of the CPU. It is assumed that bits 0 to 6 of the external interrupt request register are always 0. In addition, bit 7 of the external interrupt request register is set to "1" when a level that causes an interrupt is input to the interrupt terminal regardless of whether the interrupt is disabled or not. The

  The payout control CPU 371 checks whether the bit 7 of the external interrupt request register is set to “1” while decrementing the value of the general-purpose register by 1 (steps S721 to S723). If bit 7 of the external interrupt request register is set before the value of the general-purpose register becomes 0, that is, before the monitoring time elapses, the process proceeds to step S725. If the monitoring time elapses before bit 7 of the external interrupt request register is set, after setting a predetermined bit (which can be arbitrarily determined) of a predetermined general-purpose register used as an unstartable flag (step S724), The process proceeds to step S706. In this embodiment, the prize ball REQ signal from the main board 31 is input to the interrupt terminal of the payout control CPU 371. Therefore, if the monitoring time has elapsed before bit 7 of the external interrupt request register is set, it means that the game control means could not confirm that the payout start command was transmitted within the predetermined monitoring time. To do. Therefore, an inactivation flag indicating that is set.

  The fact that bit 7 of the external interrupt request register is set before the monitoring time elapses means that the prize ball REQ signal is turned on. That is, the game control means of the main board 31 means that the prize ball REQ signal is turned on in order to transmit the prize start command by the prize ball control signal. A prize ball control signal is inputted through 0 to 4 (step S725), and it is confirmed whether or not the inputted prize ball control signal is 10 (H) defined as a payout activation command (step S726). If it is 10 (H), it is determined that a payout activation command has been received, and the process proceeds to step S706. If it is not 10 (H), after setting a predetermined bit of a predetermined general-purpose register used as an activation disable flag (step S724), the process proceeds to step S706.

  In step S706, the RAM is set to an accessible state (step S706). Further, 0000 (H) is set as an initial value of the award ball unpaid number counter (step S707). Next, if the activation disable flag (see step S724) is not set (step S727), the state of the output signal of the clear switch 921 input via the input port 2 is confirmed only once (step S708). In the confirmation, when the on is detected, the payout control CPU 371 executes an initialization process (steps S712 to S715). If the clear switch 921 is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirmation is made (step S709). Whether or not the protection process has been performed depends on the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process described later according to the execution of the data protection process in the backup RAM area (for example, It is confirmed by whether or not 2). Note that such a confirmation method is an example. For example, a flag indicating that data protection processing has been executed is set in the backup flag area in the power supply stop processing, and the flag is set in step S709. If it is confirmed that there is a backup, it may be determined that there is a backup.

  If it is determined that there is a backup, the payout control CPU 371 performs a data check (parity check in this example) in the backup RAM area (step S710). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S710, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the payout control state recovery process is not executed, and the initialization process (the processes in steps S712 to S713) is executed.

  If the check result is normal, the payout control CPU 371 performs payout control state recovery processing. Specifically, the value of the award ball unpaid number counter formed in the backup RAM is set as the award ball unpaid number counter initial value (step S711). And then. The process after step S712 is executed.

  In the initialization process, the payout control CPU 371 first performs a RAM clear process (step S712). Also, initial values are set in the flags and counters of the RAM area (step S713). The process of step S713 includes a process of setting the initial value of the award ball unpaid number counter in the award ball unpaid number counter. Accordingly, when the payout control state recovery process (step S711) is executed, the value of the unsold prize ball number counter stored in the backup RAM is set again in the unsold prize ball number counter. In other words, the value of the award ball unpaid number counter stored in the backup RAM is used as it is. That is, when the process of steps S712 and S713 is executed without executing the process of step S711, the payout control process is started from the initial state. Further, when the process of step S711 is executed and the processes of steps S712 and S713 are executed, the execution state of the payout control process is returned to the state before the power supply is stopped.

  If the start disable flag is set in the process of step S724, the start error bit in the error flag formed in the RAM is set (steps S714 and S715). Next, a CTC register provided in the payout control CPU 371 is set so that a timer interrupt is periodically received (step S716). That is, a value corresponding to the timer interrupt generation interval is set as an initial value in a predetermined register (time constant register). Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S717). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, when the payout control CPU 371 receives a payout activation command from the game control means of the main board 13, it executes the check process of the detection signal of the clear switch 921 in step S <b> 708. As described above, the game control means executes the detection signal check process of the clear switch 921 when the payout activation command is transmitted. Therefore, the check timing of the detection signal of the clear switch 921 of the game control means and the check timing of the detection signal of the clear switch 921 of the payout control means are substantially the same. Therefore, it is possible to prevent a situation in which the content of the RAM in the other control means (for example, the payout control means) is not initialized even though the content of the RAM in one control means (for example, the game control means) is initialized Based on the operation of the clear switch 921, the contents of each RAM in the game control means and the payout control means can be reliably initialized.

  As described above, the built-in CTC of the payout control CPU 371 is set to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 executes a timer interrupt process after step S750.

  In the example shown in FIG. 39, when the payout control CPU 371 does not input a payout start command within a predetermined waiting period, the payout control CPU 371 sets an unstartable flag (see Y in step S723, S724). . Then, the payout control CPU 371 checks whether or not the unbootable flag is set (see step S714), and when it is confirmed that the unbootable flag is set, the boot error bit is set. (Refer to step S715). When the activation error bit is set, the payout control CPU 371 enters a stopped state in which the control is stopped (see steps S541 and S621 described later). However, the configuration for shifting to the stop state when the payout start command is not input is not limited to the above configuration. For example, the payout start is performed until the payout control CPU 371 inputs the payout start command. You may be comprised so that it may be in the stop state which stopped control by performing the loop process which repeatedly performs the process which confirms the input of a command.

  FIG. 40 is a flowchart showing an example of timer interrupt processing executed by the payout control means. The payout control CPU 371 first executes a power-off process for monitoring whether or not a power-off signal is output (step S750). Thereafter, a payout control process after step S751 is executed. In the payout control process, the payout control CPU 371 first performs an input determination process (step S751). In the input determination process, the states of bit 5 of input port 0 and bits 3 to 7 (see FIG. 37) of input port 1 are detected, and the detection result is reflected in a predetermined 1 byte of RAM (referred to as an input state flag). It is processing to do. In the payout control process, when control is performed based on the state of bit 5 of input port 0 and bits 3 to 7 of input port 1, the state of the input state flag is not checked instead of directly checking the state of the input port. Check status. Further, the input determination process includes a process of checking the state of bits 1 and 2 of the input port 1, that is, checking the state of the detection signal of the payout number count switch and the error release switch. Specifically, switch timers (payout number count switch timer, error release switch timer) corresponding to each of them are formed in the RAM, and when it is detected in the input determination process that they are in the ON state, the corresponding switch timer The value of the switch timer is incremented by one, and when it is detected that the switch is off, the corresponding switch timer value is cleared.

  Next, the payout control CPU 371 executes a payout motor control process (step S753). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Also, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S754). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S755). Further, a prize ball lending control process for performing a control for paying out a lending ball in response to a ball lending request from the card unit 50 and a control for paying out the number of award balls indicated by a prize ball control signal from the main board. Is executed (step S756).

  Then, the payout control CPU 371 executes error processing for detecting various errors (step S757). Further, an information output process for outputting prize ball information and ball lending information output to the outside of the gaming machine is executed (step S758). Further, a predetermined display is performed on the error display LED 374 according to the result of the error processing, and a display control process for turning on the ball break LED 52 is executed (step S759).

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer, output port 2 buffer) corresponding to the output state of the output port is provided. The contents of the port 0 buffer, output port 1 buffer, and output port 2 buffer are output to the output port (step S760: output processing). The output port 0 buffer, the output port 1 buffer, and the output port 2 buffer are a payout motor control process (step S753), a prepaid card control process (step S754), a main control communication process (step S755), and an information output process (step S758). And it is updated by the display control process (step S759).

  The power-off process is a process similar to the power-off process executed by the game control means (see FIGS. 19 and 20). That is, if the power-off signal from the power supply board 910 is in an on state continuously for a predetermined time counted by the backup monitoring timer (for example, when the value of the backup monitoring timer becomes 2 as the determination value (see step S453)). The power supply stop process is executed. In the process when power supply is stopped, the check code (specifically, checksum) is calculated for the RAM area that you want to save even when the power supply is stopped, the check code is stored in the backup RAM area, RAM access is prohibited, and the output port After clearing, loop processing starts. When it is detected that the power-off signal is turned off in the loop processing, the state of the payout control means is the same as when the game control means returns to the state of executing the game control processing (at least from the main board). This includes a process of driving the ball payout device 97 in response to a command signal related to award ball payout, and may include a process of driving the ball payout device 97 in response to a ball lending request. Specifically, for example, the process returns to step S701 of the main process shown in FIG.

  FIG. 41 is a flowchart showing the payout motor control process in step S753. In the payout motor control process, the payout control CPU 371 executes any one of steps S521 to S526 in accordance with the value of the payout motor control code.

  In the payout motor normal process (step S521) executed when the value of the payout motor control code is 0, the payout control CPU 371 sets the pointer at the head address of the table stored in the ROM. The payout motor normal process setting table stores a payout motor excitation pattern table in which data of excitation patterns (payout motors φ1 to φ4) of each step for rotating the payout motor 289 at the time of ball payout is sequentially set. Yes.

  In the payout motor activation preparation process (step S522) executed when the value of the payout motor control code is 1, the payout control CPU 371 sets bits 0 to 3 of the output port 0 buffer corresponding to the output state of the output port 0. Performs processing such as setting the initial value of the excitation pattern.

  In the payout motor slow-up process (step S523) executed when the value of the payout motor control code is 2, the payout control CPU 371 starts the rotation of the payout motor 289 more smoothly than in the case of the constant speed process. Bit 0 of the output port 0 buffer corresponding to the output state of the output port 0 by reading the contents of the payout motor excitation pattern table at a long interval and gradually approaching the time interval in the case of constant speed processing. Set to ~ 3. At the time of reading, the contents of the payout motor excitation pattern table at the address pointed to by the pointer are read and the pointer value is incremented by one.

  In the payout motor constant speed process (step S524) executed when the value of the payout motor control code is 3, the payout control CPU 371 periodically reads the content of the payout motor excitation pattern table and outputs the output state of the output port 0. Are set to bits 0 to 3 of the output port 0 buffer corresponding to.

  In the payout motor brake process (step S525) executed when the value of the payout motor control code is 4, the payout control CPU 371 has a longer interval than in the case of the constant speed process in order to stop the payout motor 289 smoothly. In addition, bits 0 to 3 of the output port 0 buffer corresponding to the output state of the output port 0 are read out at a time interval that gradually moves away from the time interval in the case of constant speed processing. Set to.

  In the payout motor brake process, the rotation of the payout motor 289 is finally stopped. At the time of stoppage, the payout motor normal process is repeated in the payout motor normal process to repeat the output state of the output port 0. Are set to bits 0 to 3 of the output port 0 buffer corresponding to. The stop-time payout motor excitation pattern is a pattern in which at least one phase of the payout motors φ1 to φ4 is excited. Since the excitation pattern given to the payout motor 289 is one type of the stop-time payout motor excitation pattern (it does not change), the payout motor 289 does not rotate. Moreover, since the dispensing motor 289 is excited, it does not rotate easily. Therefore, for example, even if an act that gives vibration to a gaming machine installed in a gaming store is performed, the gaming ball is not paid out. If the excitation is released when the rotation of the payout motor 289 is stopped, the payout motor 289 is not restrained, so that the payout motor 289 vibrates in the rotation direction in accordance with the vibration given from the outside, and the game ball is paid out. There is a possibility.

  In the ball biting payout motor brake process (step S526) executed when the value of the payout motor control code is 5, the payout control CPU 371 smoothes the payout motor 289 in the case of rotation for releasing the ball biting. The payout motor excitation pattern is longer than the rotation of the payout motor 289 for releasing the ball biting, and gradually away from the time interval in the case of constant speed processing. The contents of the table are read and set to bits 0 to 3 of the output port 0 buffer corresponding to the output state of output port 0.

  FIG. 42 is a flowchart showing the main control communication process in step S755. In the main control communication process, the payout control CPU 371 executes any one of steps S531 to S532 according to the value of the main control communication control code. If the value of the main control communication control code is 0 (waiting for reception of a prize ball control signal), the process ends without moving to step S531 or S532.

  FIG. 43 is a flowchart showing a prize ball REQ interrupt process activated in response to the prize ball REQ signal from the main board 31 introduced into the interrupt terminal being turned on (low level). In the prize ball REQ interrupt process, the payout control CPU 371 executes the subsequent processes when the error bit (main control unconnected error bit, prize ball REQ signal error bit or activation error bit) is on. The process is terminated (step S541). In step S541, if any one of the three bits in the error flag is set, it is determined that the error bit is set.

  If the error bit is not set in step S541 and the connection confirmation signal is on (step S543), the payout control CPU 371 inputs a prize ball control signal via the input port 0, and the prize ball The number of prize balls indicated by the control signal is added to the contents of the prize ball unpaid number counter (step S545). Then, the value of the main control communication control code is set to 1 (step S548), and the process ends. The prize ball unpaid-out counter is formed in a non-volatile (power-backed up in this example) RAM area.

  The prize ball control signal transmitted from the main board 31 is received by the interrupt process as described above.

  FIG. 44 is a flowchart showing main control communication processing (step S531) executed when the value of the main control communication control code is 1. In the main control communication process, the payout control CPU 371 checks the state of the prize ball REQ signal if the connection confirmation signal is in the on state (step S551) (step S552). If the winning ball REQ signal is off, the winning ball REQ signal error bit is set in the error flag (step S553). This is because it is strange that the prize ball REQ signal is immediately turned off at this stage.

  Next, the payout control CPU 371 sets the prize ball REQ signal off monitoring time in the main control communication control timer (step S557). Then, the value of the main control communication control code is set to 2 (step S558), and the process ends. The main control communication control timer is a timer used for monitoring time related to communication with the game control means of the main board 31.

  FIG. 40 is a flowchart showing main control communication end processing (step S532) executed when the value of the main control communication control code is 2. In the main control communication process, if the error bit (main control unconnected error bit, prize ball REQ signal error bit or activation error bit) is on, the payout control CPU 371 proceeds to step S567 (step S567). S561). Moreover, also when a connection confirmation signal is an OFF state, it transfers to step S567 (step S562). If both error bits are off and the connection confirmation signal is on, it is confirmed whether or not the prize ball REQ signal is off (step S563). When it is turned off, the process proceeds to step S567.

  If the prize ball REQ signal is not turned off, the value of the main control communication control timer is confirmed (step S564). If the value of the main control communication control timer is not 0, the value of the main control communication control timer is decremented by 1 (step S565). If the value of the main control communication control timer is 0, it is determined that the prize ball REQ signal has not been turned off within the monitoring time, and the prize ball REQ signal error bit is set in the error flag (step S566). Transition.

  In step S567, the value of the main control communication control code is set to 0, and the process ends.

  FIG. 46 is a flowchart showing the prize ball lending control processing in step S756. In the winning ball lending control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S601), and lends whether or not the paid gaming ball is a winning ball. It is confirmed whether it is a sphere (steps S602 and S603). In this example, whether or not the game ball is a prize ball is confirmed by whether or not the current payout control state is a prize ball. Whether or not a prize ball is in progress is confirmed, for example, by whether or not a prize ball operating flag in the payout control state flag formed in the RAM is set (step S602). Further, whether or not the game ball is a lending ball is confirmed by whether or not the current payout control state is lending the ball. Whether or not the ball is being lent is confirmed, for example, by whether or not the ball renting operation bit in the payout control state flag formed in the RAM is set (step S603).

  If it is during the winning ball, the value of the winning ball unpaid number counter is decremented by 1 (step S604). If it is not in the winning ball but in the ball lending, the value of the ball lending unpaid-out number counter is decreased by 1 (step S605). Further, if the winning ball is not being lent and not being lent, the value of the award ball unpaid-out counter is decremented by 1 assuming that the paid-out gaming ball is a winning ball (step S604).

  When the value of the winning ball unpaid-out counter is decremented by 1, the payout control CPU 371 turns on the winning ball count signal for a predetermined period (step S606). Next, the payout ball detection bit of the payout control state flag formed in the RAM is set (step S607). The payout ball detection bit is a game regardless of whether the payout motor 289 is driven during one award ball payout process (maximum 15 balls) or one ball lending process (25 payouts) in the payout passing waiting process. This is used to detect that no sphere has passed through the payout number counting switch 301. Thereafter, any one of steps S610 to S612 is executed according to the value of the payout control code.

  In the prize ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one prize ball payout or one ball lending) as shown in FIG. Only in the payout start waiting process. That is, the confirmation process of the payout number count switch 301, the subtraction process of the non-payout number counter, the output process of the prize ball count signal, etc. shown in FIG. 46 are executed without checking the error bit. Therefore, even if an error occurs, the ball lending unpaid-out counter or the winning ball unpaid-out counter is subtracted in accordance with the detection output from the paid-out count switch 301, and the value of the award ball unpaid-out counter When is subtracted, a prize ball count signal is output. Therefore, the number of unpaid game balls can be managed even in an error state. Even if an error state is detected, a prize ball count signal can be output in response to the detection of a payout of a prize ball. Therefore, even in an error state, it is detected on the payout control board 37 side. Information indicating that the winning ball has been paid out can be transmitted to the main board 31 side.

  In the prize ball lending control processing, if there is a detection output from the number-of-payout count switch 301 when neither a prize ball nor a ball is lent, it is determined that the game ball that has been paid out is a prize ball, The value of the payout number counter is subtracted, and a prize ball count signal is output to the main board 31. Therefore, even when an illegal game ball is paid out, a prize ball count signal is transmitted to the game control means (specifically, the game control microcomputer 560) mounted on the main board 31. . Since the game control means manages the number of prize balls to be paid out, if a prize ball count signal indicating the number of prize balls more than the number of prize balls to be originally paid out is received, illegal payout is performed. Can be determined. When it is determined that an illegal game ball has been paid out, the game control means performs the following appropriate processing.

  For example, the game control means performs a process for notifying a player, a game clerk, or the like of the occurrence of an error using the variable display device 9 or the like. Specifically, the game control means transmits an effect control command for notifying the occurrence of an error to the effect control means (specifically, the effect control microcomputer 100), thereby causing an error in the effect control means. Control to display the above on the variable display device 9 is executed. The game control means transmits a lamp control command and a sound control command for informing the error to the lamp control means and the sound control means via the effect control means, so that the error is notified to the lamp control means and the sound control means. You may make it perform lighting of the lamp and LED for alerting | reporting generation | occurrence | production, and audio | voice output. In addition, the game control means performs a process for stopping the progress of the game. Specifically, the game control means saves the current control state, for example, the output state of the output port, in the RAM 55 before stopping the progress of the game, and then clears the output state of the output port so that the abnormal state is Stop playing until it is resolved. Further, the game control means performs a process (step S32) of outputting information indicating that an illegal game ball has been paid out to a hall computer or the like outside the game machine. The game control means sends information indicating the number of prize balls to be paid out and a signal indicating the number of prize balls actually paid out based on the prize ball count signal to a hall computer or the like outside the gaming machine by information output processing. By outputting, it is possible to make the hall computer or the like determine whether or not an illegal game ball has been paid out. Incidentally, all of the above processes may be executed, but at least one or more of the above processes are executed.

  FIG. 47 is a flowchart showing the payout start waiting process (step S610) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 does not execute the subsequent processes if the error bit is set (step S621). The error bits in the error flag include a main board unconnected error, a payout case error, and a start error bit. The main board unconnected error is set when the connection confirmation signal from the main board 31 is in the OFF state (see step S816). The activation error bit is set when a payout activation command from the game control microcomputer 560 is not input within a predetermined period (see step S715). Accordingly, the payout control means starts substantial control on the condition that after the power supply to the gaming machine is started, the connection confirmation signal is turned on and a payout activation command is input.

  On the other hand, if the BRDY signal is not in the on state, processing for paying out a prize ball after step S631 is executed. If the BRDY signal is on and the BRQ signal, which is a ball lending request signal, is on, a ball lending operation flag is set (steps S623 and S624). Then, “25” is set in the unpaid ball lending number counter (step S625), and “25” is set in the payout motor rotation number buffer (step S626).

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S768). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  Thereafter, the payout control CPU 371 sets a value (specifically “1”) corresponding to the payout motor activation preparation process (step S522) to the payout motor control code for selecting the process executed in the payout motor control process. It is set (step S627), the value of the payout control code is set to 1 (step S628), and the process is terminated.

  In step S631, the payout control CPU 371 checks whether or not the value of the award ball non-payout counter is 0 (step S631). If 0, the process ends. The prize ball unpaid-out counter is a value other than 0 (the number indicated by the prize ball control signal) when the prize ball REQ signal is received from the game control means of the main board 31 in step S546 in the main control communication normal process. ) Is added. If the value of the award ball unpaid number counter is not 0, it is confirmed whether it is 15 or more (step S632). If it is less than 15, the value of the award ball unpaid number counter is set in the payout motor rotation count buffer (step S633), and if it is 15 or more, “15” is set in the payout motor rotation count buffer. Then, a winning ball operating flag is set (step S635), and the process proceeds to step S637.

  FIG. 48 is a flowchart showing a payout motor stop waiting process (step S611) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 checks whether or not the payout operation is completed (step S641). For example, the payout control CPU 371 sets a flag to that effect when the payout motor brake process (step S525) in the payout motor control process ends, and whether the payout operation is completed by checking the flag in step S641. You can check whether or not.

  When the payout operation is completed, the payout control CPU 371 sets the payout passing monitoring time in the payout control monitoring timer (step S642). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. Then, the value of the payout control code is set to 2 (step S643), and the process ends.

  FIG. 49 is a flowchart showing a payout passing waiting process (step S612) executed when the value of the payout control code is 2. In the payout passing waiting process, when a prize ball is being paid out, it is determined that the payout has been completed normally if the value of the prize ball unpaid number counter is zero. If the value of the award ball unpaid number counter is not 0 even after the predetermined period has elapsed, the state shifts to an error state.

  In this embodiment, the maximum number of game balls to be paid out in one prize ball payout operation is 15, and if a prize ball control signal is received during the prize ball payout, the value of the prize ball unpaid number counter Therefore, even when the payout is completed normally, the value of the award ball non-payout number counter may not be 0. Therefore, when the payout of the number of award balls set in step S633 or step S634 is confirmed (the value of the award ball unpaid number counter is the unpaid prize ball whose grasp control microcomputer 370 knows) It is determined that the payout is normally completed when the total number (the number including the number of prize balls to be paid out this time is a value obtained by subtracting the number set in step S633 or step S634). You may make it do.

  Further, when the ball lending is being paid out, it is determined that the payout has been completed normally if the value of the ball lending unpaid-out counter is 0. If the value of the unpaid ball lending counter is not 0, the state shifts to an error state. In this embodiment, the number of game balls to be paid out in one ball lending and payout operation is 25 (fixed value), and the payout motor 289 is rotated so that 25 game balls are paid out. Therefore, when the value of the unpaid ball lending counter is not 0, the payout has not been completed normally.

  In the payout passage waiting process, the payout control CPU 371 first decrements the value of the payout control timer by 1 (step S651). Then, the value of the payout control timer is confirmed. If the value is not 0 (step S652), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out (step S652), it is confirmed whether or not the ball lending payout process (ball lending operation) has been executed (step S653). Whether or not the ball lending operation has been executed is confirmed by whether or not the ball lending operation in progress flag in the payout control state flag formed in the RAM is set. When the ball lending operation is not executed, that is, when the prize ball payout process (prize ball operation) is executed, the payout control CPU 371 checks the value of the award ball unpaid number counter (step S654). ). If the value of the award ball unpaid number counter is 0, it is determined that the award ball payout process has been completed normally, and a payout ball detection bit, a prize ball operating flag, and a ball lending operation bit in the payout control status flag Is reset (step S655), the payout control code is set to 0 (step S656), and the process ends.

  If the value of the award ball unpaid number counter is not 0 and the payout ball detection bit is not set (step S658), the payout control CPU 371 will play the game ball even if the payout operation is performed. Is not paid out, a payout count switch non-passing error bit (payout case error bit) is set as a game ball payout failure (step S659).

  As described above, in this embodiment, even when the payout is normally completed, the value of the award ball non-payout number counter may not be 0. Therefore, if the payout ball detection bit is set, that is, if the payout number count switch 301 detects the payout of at least one game ball during the prize ball payout process, it is assumed that the prize ball payout process is normally completed. The process proceeds to step S655. For example, when 15 game balls should be paid out in one prize ball payout process, when only 14 game balls are actually paid out (the number of payout count switch 301 is 14 game balls). In this case, the payout ball detection bit is set, so it is considered that the award ball payout process has been completed normally. It should not have been done, and the shortage will be paid out in the next prize ball payout process, so there will be no disadvantage to the player.

  As described above, if no game ball is paid out even if a payout operation is performed in the payout process, a payout count switch non-passing error bit (payout case error bit) is set as a game ball payout operation failure. Set.

  In the winning ball lending control process, the error bit is checked to determine whether or not to perform a payout operation (one winning ball payout or one ball lending). The payout start shown in FIG. Only in the waiting process. In the payout motor stop waiting process shown in FIG. 48 and the payout passing wait process shown in FIG. 49, the error bit is not checked. Therefore, after the process of step S626, S633, or step S634 is performed and the game ball payout process is started, the payout process is not interrupted even if an error occurs. In other words, when an error occurs, the game ball payout process is continued until a point at which the game ball can be cut well (at the time when one prize ball payout or one ball lending ends). The error bit in the error flag checked in step S621 includes an error bit indicating that the connection confirmation signal from the main board 31 has been turned off. Therefore, even when the connection confirmation signal is turned off, the game ball payout process is stopped at a time when it is best to turn it off. When an error occurs after the game ball payout process is started, the payout process may be interrupted even during the process.

  Upon confirming that the ball lending / dispensing process (ball lending operation) has been executed in step S653, the payout control CPU 371 confirms whether or not the value of the unlapped ball lending number counter is 0 (step S657). . If it is 0, it is determined that the ball lending / dispensing process is normally completed, and the process proceeds to step S655.

  If the value of the ball lending unpaid number counter is not 0 and the payout ball detection bit is not set (step S658), the game ball is not paid out even if the payout process is executed (payout). As the number count switch 301 has not detected a game ball), the payout case error bit of the error flag is set (step S659), and the process is terminated.

  As described above, if no game balls are paid out even if a payout operation is performed in the payout process related to the ball lending process, the payout count switch non-passing error bit (payout) is assumed as a game ball payout operation failure. Case error bit) is set.

  FIG. 50 is a timing chart for explaining the ball biting detection process executed in the payout motor control process (step S753). In the payout motor constant speed process (step S524) in the payout motor control process, the payout control CPU 371 monitors the detection signal of the payout motor position sensor 295. The detection signal of the payout motor position sensor 295 is turned on twice, for example, every time the cam that rotates in conjunction with the payout motor 289 rotates once. In order for the detection signal to be output twice each time the cam rotates once, the cam has two locations in the portion that receives light from the light emitting portion in the payout motor position sensor 295 (positions symmetrical with respect to the axis). Is provided with a reflector. The output of the light receiving unit in the dispensing motor position sensor 295 is used as a detection signal.

  Therefore, even if the payout control CPU 371 gives an excitation pattern having a step number of 1/2 rotation or more to the payout motor 289, the detection signal of the payout motor position sensor 295 does not turn on. Actually, the payout motor 289 does not rotate due to foreign matter such as dust adhering to the cam portion and the like, and the game ball is clogged (ball biting has occurred). As a result, the cam rotates. It can be judged that it is not.

  In this embodiment, when the payout motor 289 receives an excitation pattern for 16 steps (2.087 ms per step), it makes one rotation and pays out one game ball. Then, the payout control CPU 371 checks the detection signal of the payout motor position sensor 295 every time the payout control CPU 371 gives an excitation pattern for 8 steps to the payout motor 289, and the payout motor 289 rotates. It is determined whether or not. Then, if the same state is detected five consecutive times (the detection signal of the dispensing motor position sensor 295 is OFF for five consecutive times or ON for five consecutive times), it is determined that ball engagement has occurred. A ball biting release process is executed.

  As shown in FIG. 51, the payout control CPU 371 repeats a process of rotating the payout motor 289 at a high speed and a process of rotating at a low speed a predetermined number of times (for example, 9 times). Each time an excitation pattern for 8 steps is given to the payout motor 289, the detection signal of the payout motor position sensor 295 is checked to determine whether the payout motor 289 is rotating. If it is determined by the detection signal that the rotation of the payout motor 289 has been restored, the ball biting release processing is terminated and the normal ball payout processing is returned to.

  If no change occurs in the detection signal of the payout motor position sensor 295 even if the process of rotating at a high speed and the process of rotating at a low speed are performed a predetermined number of times, a ball biting error bit (payout case error bit) in the error flag Set. When the payout case error bit is set, the payout control CPU 371 does not drive the payout motor 289. When the payout case error bit is reset (see step S807 in FIG. 53), the payout control CPU 371 returns to a state in which the payout motor 289 can be driven.

  Thus, the payout control means includes a drive state monitoring means for monitoring the operating state of the payout means, and a drive stop means for stopping the driving of the payout means when the drive state monitoring means detects a malfunction of the payout means. Including.

  Next, error processing will be described. FIG. 52 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 52, when the connection confirmation signal from the main board 31 is turned off, the payout control CPU 371 displays “1” on the error display LED 374 as a main board non-connection error. I do. When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above. When the prize ball REQ signal is turned on at an improper timing or when the prize ball REQ signal is turned off at an improper timing, “5” is displayed in the error display LED 374 as a prize ball REQ signal error. Control to display. A specific method for detecting that the prize ball REQ signal is turned on or off at an incorrect timing is as described above.

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit unconnected error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S754).

  In addition, when the start error bit set due to not receiving the payout start command from the main board 31 at the start of power supply is set, control for displaying “A” on the error display LED 374. I do.

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, a prize ball REQ signal error or a start-up error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (ON When the state is reached, the payout control means returns to the state before the error occurred.

  As for the startup error, even if an operation signal is output from the error release switch 375, it may be configured not to return to the state before the error occurred.

  53 and 54 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 checks the error flag, and the set bits are only payout switch abnormality detection error 2, payout case error and prize ball REQ signal error (any one of the three). It is confirmed whether it is only a bit, or only two bits out of three, or only these three bits (step S801). If only those bits are set, it is confirmed whether or not the operation signal is turned on from the error release switch 375 (step S802). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S803). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S804). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S808. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S805). If the pre-error recovery timer value becomes 0 (step S806), the payout switch of the error flag is set. The bits of the abnormality detection error 2, the payout case error and the prize ball REQ signal error are reset (step S807), and the process proceeds to step S808.

  When the processing of step S807 is executed, there may be an error bit that is not in the set state among the bits of the payout switch abnormality detection error 2, the payout case error, and the prize ball REQ signal error. There is no problem resetting error bits that are not in the state. As described above, in this embodiment, if an error (see FIG. 52) that causes the setting of the payout switch abnormality detection error 2, the payout case error, or the prize ball REQ signal error bit occurs, an error occurs. The error is released when the release switch 375 is pressed. However, in the example shown in FIG. 53, when an error (see FIG. 52) that causes the start error bit to be set occurs, the error is not released even if the error release switch 375 is pressed. ing.

  In this example, even in the error state, the processes in steps S601 to S605 shown in FIG. 46 are executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the award ball unpaid number counter or the ball lending unpaid number counter is subtracted. Therefore, the value of the award ball unpaid number counter or the ball lending unpaid number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Even when it is confirmed that the game ball has passed through the payout count switch 301 during the error state, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) (steps S802 and S807). That is, the state of the payout case error (payout shortage error) is not automatically canceled based on the fact that the game ball has passed the payout number count switch 301, etc. The error is not cleared. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred.

  When the error cancel switch 375 is operated so as to be reset in hardware (reset to the payout control CPU 371), the error cancel switch 375 is operated, for example, a prize ball has not been paid out. The value of the number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  Although not shown in FIG. 53, after a predetermined error bit is reset in step S807, processing for setting the value of the payout control code to 0 is executed. By such processing, the game ball payout process is executed again from the beginning, and the game ball is paid out reliably.

  In step S808, the payout control CPU 371 checks the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error bit in the error flag is set (step S809). If the detection signal of the full tank switch 48 is in the OFF state, the full tank error bit is reset (step S810).

  Also, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S811). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error bit in the error flag is set (step S812). If the detection signal of the ball break switch 187 is OFF, the ball break error bit is reset (step S813). When the ball break error bit is set, the bit corresponding to the ball break LED 52 in the output port 1 buffer is set to a value corresponding to the lighting state in the display control process of step S759.

  Further, as shown in FIG. 54, the payout control CPU 371 checks the state of the connection confirmation signal from the main board 31 (step S815). If the connection confirmation signal is not output (if it is in the off state), The main board unconnected error bit is set (step S816). If the connection confirmation signal is output (if it is on), the main board non-connection error bit is reset (step S817).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 240 ") (step S818), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S819). If the value of the switch timer corresponding to the payout number count switch 301 is less than the switch-on maximum time, the bit of the payout switch abnormality detection error 1 is reset (step S820). Note that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S751, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371, when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (eg, “2”) (step S821), the ball lending operation flag and the winning ball operation If both the middle flags are in the reset state, the game ball passes through the payout number count switch 301 even when the payout operation is not in progress, and the bit of the payout switch abnormality detection error 2 is set in the error flag (steps S822 and S823). . If the ball lending operation flag or the winning ball operation flag is set, the bit of the payout switch abnormality detection error 2 is reset (step S824).

  Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S825). If the VL signal is not input (if it is in the OFF state), the prepaid card unit not yet out of the error flags is displayed. A connection error bit is set (step S826). If the VL signal is input (if it is on), the prepaid card unit unconnected error bit is reset (step S827).

  Further, the payout control CPU 371 checks the state of predetermined error bits (in this example, full error bit, ball out error bit, main control unconnected error bit) in the error flag (step S828a), and the predetermined error If any of the error bits is set, the payout error signal is turned on (step S828b). If all the predetermined error bits are in the reset state, the payout error signal is turned off (step S828c). The payout control CPU 371 may turn on the payout error signal even when the activation error bit is set. Incidentally, when the payout error signal is turned on, the game control microcomputer 560 executes an error notification process (see step S24b).

  In the display control process of step S771, notification by display (numerical value display) corresponding to the error bit in the error flag is performed by the error display LED 374.

  In this embodiment, the main board unconnected error is automatically eliminated when the connection confirmation signal is turned on (see steps S815 and S817), but the condition that the error cancel switch 375 is further operated is added. Thus, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (prepaid card unit non-connection error and prepaid card unit communication error) and other errors (see FIG. 52). ). Therefore, a communication error between the game control unit and the payout control unit is easily identified.

  In this embodiment, the error display LED 374 mounted on the payout control board 37 installed on the back side of the gaming machine is informed that an error relating to the payout has occurred. You may mount an alerting | reporting means in other locations (For example, the payout unit in which the ball payout apparatus 97 etc. were concentratedly arranged). Furthermore, you may make it alert | report by the indicator installed in the front side of the gaming machine. If an error is notified by a display device installed on the front side of the gaming machine, the game shop clerk can more easily recognize the occurrence of the error. Moreover, you may use together the alerting | reporting by error display LED374, and the alerting | reporting by the indicator installed in the front side of the gaming machine.

  FIG. 55 is a flowchart showing the display control process (step S759). In the display control process, the payout control CPU 371 sets the ball break LED output bit in the output port 1 buffer (step S572) when the ball break error bit is set in the error flag (step S571). If the ball break error bit is not set, the ball break LED output bit in the output port 1 buffer is reset (step S573). Note that the contents of the output port 1 buffer are output to the output port 1 in the output process of step S760.

  The payout control CPU 371 loads an error flag (step S574), determines an error code (7SEG display code; see FIG. 52) corresponding to the error bit in the error flag (step S575), and determines the determined error code. The output port 2 is set in the output buffer (step S576).

  Next, the operation of the effect control means mounted on the effect control board 80 will be described. FIG. 56 is a flowchart showing main processing executed by the effect control CPU 101. In the main process, an initialization process is first performed for clearing the RAM area, setting various initial values, initializing a 4 ms timer for determining the display control activation interval, and the like (step S321). Thereafter, the effect control CPU 101 proceeds to a loop process for checking the timer interrupt flag (step S322). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the interrupt processing. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S323), and executes the following effect control process.

  In this embodiment, the timer interrupt takes every 4 ms. That is, the effect control process is started every 4 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific effect control process is executed in the main process, but the effect control process may be executed in the timer interrupt process.

  In the effect control process, the effect control CPU 101 first executes a command analysis process (step S324) for analyzing the received effect control command, and a counter update process for updating the count value of the counter for generating a random number (step S324). S325). Then, the effect control CPU 101 executes effect control process processing (step S326). In the effect control process, a process corresponding to the current control state is selected and executed from among the processes corresponding to the control state.

  Next, the production control CPU 101 checks whether or not a V blank interrupt has occurred (step S327). Whether or not a V blank interrupt has occurred is confirmed based on an interrupt signal output from the VDP 109 at the start of the V blank. The V blank is the display of the image developed in the display area (not shown) of the VRAM on the display screen of the variable display device 9, and then the image developed next in the display area of the VRAM is displayed on the variable display device 9. This is the period until display starts on the display screen. The VDP 109 outputs an interrupt signal to the effect control CPU 101 at the start of the V blank and issues a V blank interrupt. For example, when an image of 30 frames is displayed per second, a V blank interrupt is applied approximately every 33 ms.

  The effect control CPU 101 includes an interrupt terminal for receiving an interrupt signal from the VDP 109. When the input level of the interrupt terminal falls to a low level, the effect control CPU 101 detects the occurrence of a V blank interrupt as an external interrupt. For example, as shown in FIG. 57, when the CPU 101 for effect control detects the occurrence of the V blank interrupt, it sets a flag indicating the presence of the V blank interrupt in the register (step S331).

  When there is a V blank interrupt, the effect control CPU 101 executes an image development instruction control process as an interrupt process (step S328). In the image expansion instruction control process, the effect control CPU 101 executes control for instructing the VDP 109 to expand the image data displayed on the display screen of the variable display device 9 to the display area of the VRAM. Note that the VDP 109 develops image data in the display area of the VRAM in accordance with an instruction from the effect control CPU 101. The VDP 109 creates an image signal based on the image data in the display area, outputs the image signal to the variable display device 9, and displays an image frame on the display screen of the variable display device 9. As described above, since a V blank interrupt is generated every 33 ms, the image frame is updated once every 33 ms.

  If there is no V blank interrupt, the process returns to the process of checking the timer interrupt flag in step S702. Even after the image development instruction control process is executed, the process returns to the process of checking the timer interrupt flag in step S702.

  In this embodiment, in the V blank interrupt processing, only flag setting (setting with V blank interrupt) is performed, and specific image development instruction control processing and command transmission processing are executed in the main processing. The image development instruction control process and the command transmission process may be executed by an interrupt process.

  In this embodiment, in the command analysis process (step S324), whether or not the effect control CPU 101 stores the received command (the effect control command from the game control board 31) in the command reception buffer provided in the RAM. If the received command is stored in the command reception buffer, the received command is read from the command reception buffer. Then, the effect control CPU 101 determines the content of the read reception command. When it is determined that the received command is a prize ball payout confirmation designation command, the effect control microcomputer 101 executes a process for notifying the player that one prize ball has been paid out. In this embodiment, as described with reference to FIG. 26, the effect control CPU 101 controls the driving (lighting) of the prize ball lamp 51 in response to receiving the prize ball payout confirmation designation command. Is output to the frame-side lamp driver substrate 35 to execute control for turning on the prize ball lamp 51 for a predetermined period (for example, 0.5 seconds).

  Further, when it is determined that the received command is an error occurrence notification command, the effect control CPU 101 executes a process for notifying a player or the like that a predetermined error state has occurred. Specifically, the effect control CPU 101 sets an error notification in-execution flag indicating that an error occurrence notification process is being executed. When the error notification execution flag is set, the flag is first checked in the effect control process (step S326), the image development instruction control process (step S328), etc., and the execution of these processes is stopped. . Further, when the CPU 101 for effect control is currently controlling image display such as variable display for the VDP 109, the current control state is saved (backed up) in a predetermined area of the RAM. Then, the effect control CPU 101 uses the VDP 109 to display error data in the display area of the VRAM in order to display an error display on the display screen of the variable display device 9 based on the received error occurrence notification command. Executes the control for instructing the deployment of The production control CPU 101 executes such control when the lamp / LED is blinked or a sound effect is emitted from the speaker 27 in order to notify the player or the like of the occurrence of the error state. Control signal (command signal) is output to the frame side lamp driver board 35 and the voice control board 70.

  Further, when it is determined that the received command is an error release notification command, the effect control CPU 101 executes a process for notifying the player or the like that the error state has been released. Specifically, the CPU 101 for effect control erases the error display displayed on the display screen of the variable display device 9, and in the variable display device 9 based on the control state stored in a predetermined area of the RAM. In order to restart the image display from the display state before the error display, the control for instructing the VDP 109 to expand the image data in the display area of the VRAM is executed. The production control CPU 101 executes such control when the lamp / LED blinks or the sound effect is emitted from the speaker 27 in order to notify the player or the like that the error state has been released. A control signal (command signal) for causing the signal to be output is output to the frame side lamp driver board 35 and the voice control board 70. The effect control CPU 101 resets the error notification in-execution flag when executing a process for notifying the player or the like that the error state has been canceled using an effect device such as the variable display device 9. When the error notification execution flag is reset, the effect control process (step S326), the image development instruction control process (step S328), and the like are resumed.

  If the received command is not a prize ball payout confirmation designation command, an error occurrence notification command, or an error release notification command, the effect control CPU 101 performs an effect control process process (step S326) or an image expansion instruction according to the received reception command. This is executed in the control process (step S328).

  As described above, in the above embodiment, the game control means transmits a payout activation command to the payout control means when power supply to the gaming machine is started (step S5), and then clears. The check signal of the switch 921 is checked (step S7), and the payout control means checks the detection signal of the clear switch 921 when receiving a payout start command from the game control means (steps S726, S727, S708) Although the game control means executes the software delay processing, the game control means and the payout control means check the detection signal of the clear switch 921 almost simultaneously. Therefore, although one control means has performed the detection signal check processing of the clear switch 921, the other control means does not perform the detection signal check processing of the clear switch 921 and the backup storage contents in one control means. This prevents the situation in which the backup storage contents in the other control means are not cleared even though they are cleared.

  Further, the payout control means introduces a take-in signal (in the above embodiment, a prize ball REQ signal) for instructing taking-in of the payout activation command into the maskable interrupt terminal of the payout control microcomputer 370, thereby playing the game control means. When it is confirmed that the payout start command has been sent from (the initial setting process is in progress), the interrupt is disabled and the external interrupt request register bit is checked to input the capture signal. Confirmation (steps S701 and S721). Therefore, even if it is configured to introduce the capture signal to the interrupt terminal, there is no possibility that the initial setting process is not correctly performed due to the occurrence of the interrupt. If an interrupt is allowed during the initial setting process, the internal state of the payout control microcomputer 370 may change during the interrupt process, and the initial setting process may not be performed correctly.

  The payout control means, in the payout control process executed after executing the initial setting process and the initialization process, shows a prize indicating the number of prize balls paid out in the interrupt process based on the input of the capture signal to the maskable interrupt terminal. Since the ball control signal is received (see FIG. 43), the number of prize balls paid out based on the prize ball control signal can be received quickly and accurately.

  In the above embodiment, the payout start command (payout start command) and the prize ball control signal are transmitted through the same signal line, but the signal lines for transmitting them may be separated. The form of the payout activation command and the prize ball control signal used in the above embodiment may be changed to another form. For example, a 1-byte or 2-byte command may be transmitted via an 8-bit signal line. When a 2-byte command is used, a capture signal is transmitted for each byte.

  Further, in the above embodiment, the game control microcomputer creates a delay time by software when power supply is started, but also creates a delay time by hardware as shown in FIG. You may do it. In the configuration shown in FIG. 58, the reset signal from the power supply board 910 input to the reset terminal of the CPU 56 is delayed by the delay circuit 69 in the main board 31. According to such a configuration, since the start of the game control process is also delayed by hardware, the data capacity of software for the delay process can be reduced.

  In the above embodiment, the payout number count switch 301 for detecting the payout of the game ball without distinguishing the winning ball and the lending ball is provided, and the detection output of the payout number count switch 301 is input only to the payout control means, When the payout control means inputs a detection signal from the payout number count switch 301, it determines whether the payout of the prize ball or the payout of the lending ball is detected, and determines that the payout of the prize ball is detected. Sometimes the prize ball count signal is transmitted to the game control means, so that the game control means can more reliably manage the number of prize balls that have not been paid out and one payout number count switch. Since the winning ball payout and the lending ball payout are detected at 301, there is an effect that the number of parts is reduced and the cost of the gaming machine can be reduced.

  Further, in the above-described embodiment, the payout control means detects the winning ball payout when the detection signal from the payout number count switch 301 is input even in an error state where the payout of the game ball is stopped. When it is determined that there is a prize ball, a prize ball count signal is transmitted to the game control means, so that a prize ball count signal indicating that a payout of the prize ball has been detected can be reliably transmitted to the game control means. .

  Further, in the above-described embodiment, the payout control means receives the detection signal from the payout number count switch 301 when the award ball is not paid out or the lending ball is not paid out. Since the award ball count signal is transmitted to the game control means as being a prize ball, the award ball count signal can be transmitted to the game control means even when an invalid gaming ball is paid out. Can be processed appropriately.

  In the above-described embodiment, when the game control means transmits a payout command signal, a subtraction process is performed to subtract the payout number specified by the payout command signal from the number of prize balls stored in the total prize ball number storage buffer. Since it is configured to perform, it is possible to prevent the designation of payout from being executed again for a prize ball for which payout has already been designated. Further, since the number of payouts specified by the payout command signal is subtracted regardless of whether or not a prize ball count signal is received, the prize ball number subtraction process stored in the total prize ball number storage buffer is executed. Therefore, it is possible to reduce the control burden of the game control means.

  In the above-described embodiment, after the payout command signal is transmitted as described above, the signal indicating the completion of the payout process from the payout control board 37 side is received in the total winning ball number storage buffer regardless of whether or not the signal is received. The subtraction process for the number of prize balls stored is executed, and the game control means does not accurately manage the number of unpaid prize balls, but the game control means transmits a payout command signal. After that, in response to receiving the prize ball count signal, the subtraction process for subtracting the number of payouts confirmed to be actually paid out from the number of prize balls stored in the total prize ball number storage buffer is performed. Also good. In this case, each time the game control means receives the prize ball count signal, the game control means may subtract one from the prize ball number stored in the total prize ball number storage buffer. If the configuration is such that the number of unpaid prize balls is managed by bidirectional communication between the game control means and the payout control means as described above, in the game control means based on the prize ball count signal from the payout control means. The number of unpaid prize balls can be managed accurately. In other words, if the management of the number of unpaid balls is not performed using the prize ball count signal, the management of the number of unpaid balls is performed by one-way communication. There is a problem that the number of unpaid prize balls ascertained in the means is not always accurate. As described above, if the configuration is such that the game control means manages the number of unpaid balls in the game control means as described above, the number of unpaid balls can be subtracted when the game is actually paid out. The number of unpaid prize balls can be managed accurately.

  Further, when the configuration is such that the management of the number of unpaid balls has been accurately performed as described above, the number of times corresponding to the number of payouts specified by the payout command signal after the game control means has transmitted the payout command signal. The payout command signal for instructing the next prize ball payout may not be transmitted until the prize ball count signal is received. Specifically, when the game control means transmits a payout command signal instructing the payout of seven prize balls, the game control means receives the prize ball count signal seven times, and then instructs the next prize ball payout. The payout command signal may be transmitted. According to the above configuration, it is possible to prevent the payout command signal transmitted from the game control means to the payout control means and the prize ball count signal transmitted from the payout control means to the game control means from competing. Can do. Therefore, in the payout control means and the game control means, it is possible to prevent the control signal (payout command signal, prize ball count signal) from being lost.

  Further, the payout control means transmits a command acceptance signal indicating that the payout command signal transmitted from the game control means has been received to the game control means, and the game control means accepts the command acceptance transmitted from the payout control means. When the signal is received, the winning ball number stored in the total winning ball number storage buffer may be subtracted. Here, the command acceptance signal corresponds to an acceptance confirmation signal for the payout command signal, and is also referred to as a prize ball BUSY signal. Even in such a configuration, the number of unpaid prize balls can be centrally managed by the game control means.

  In the embodiment described above, the game control means is configured to execute processing for turning on the prize ball lamp 51 in response to reception of the prize ball count signal. Even if it is not controlled by this, it is possible to notify the player or game store clerk that the prize ball has been paid out or that the game ball that has been paid out is a prize ball. In the above example, as a process for turning on the prize ball lamp 51, a process for transmitting a prize ball payout confirmation designation command to the effect control board 80 is executed. When receiving the prize ball payout confirmation designation command, the effect control CPU 101 of the effect control board 80 executes control for lighting the prize ball lamp 51 for a predetermined period. However, the game control means may control the prize ball lamp 51, and the game control means may execute a driving process for turning on the prize ball lamp 51 in response to reception of the prize ball count signal. . Further, it may be notified that a prize ball has been paid out by a light emitter other than the prize ball lamp 51 or a display device.

  In the above-described embodiment, the payout control means transmits a payout error signal to the game control means when the bottom pan full or an out of ball error occurs (turns on). It is possible to make the game control means recognize that an error relating to the payout of the ball has occurred.

  In the embodiment described above, the game control means transmits an error occurrence notification command for notifying the occurrence of an error to the effect control means in response to receiving the payout error signal from the payout control means. Thus, it is possible to cause the effect control means to perform a process of notifying the occurrence of an error, and to make the player easily recognize the occurrence of the error.

  In the above-described embodiment, the game control means transmits the payout command signal to the payout control means even when the game control means receives the payout error signal from the payout control means. When a payout error signal is received, a payout command signal may not be transmitted to the payout control means. Specifically, before executing the process of step S251 in the prize ball transmission process shown in FIG. 33, it is confirmed whether or not the game control means has received a payout error signal from the payout control means. If a signal is received, the processing after step S251 is not executed. According to such a configuration, it is possible to reduce the possibility that a payout command signal is missed in the payout control means.

  In the above-described embodiment, the production control microcomputer 100 of the production control board 80 not only controls the display state of the variable display device 9, but also sends control signals to the frame side lamp driver board 35 and the audio control board 70. To control the lighting / extinguishing of the lamp / LED and the sound output of the speaker 27. However, the present invention is not limited to this configuration, and the frame side lamp driver board 35 and the voice control board 70 are each provided with a lamp control microcomputer and a voice control microcomputer, and the stage control microcomputer responds to the stage control command. The control command and the voice control command are transmitted to the lamp control microcomputer and the voice control microcomputer, respectively, and the lamp / LED is turned on / off and the voice output of the speaker 27 is sent to the lamp control microcomputer and the voice control microcomputer. You may make it perform.

  Further, in the above-described embodiment, when the error bit is set due to occurrence of a ball-out condition or a full-bottom-plate condition (step S621), the process after step S622 of the payout start waiting process (see FIG. 47) is performed. Is not executed and the game ball payout process is not executed, so that it is possible to prevent the game ball payout process from being executed in an abnormal state. . Therefore, it is possible to prevent a situation in which the game balls are not paid out effectively, for example, a situation in which the ball payout device 97 is unable to pay out the game balls even if the ball payout device 97 tries to pay out the game balls due to a shortage of the ball or a full lower tray.

  In the above embodiment, the payout control means confirms that the game ball has been paid out based on the detection signal of the payout count switch 301, but the game ball is based on the output signal of the payout motor position sensor. You may make it confirm that was paid out.

  Also, the payout control means detects the operation amount of the drive means (for example, payout motor 289, cam, etc.) of the payout means, and determines whether or not an abnormality related to payout (payout unit error) has occurred based on the detected amount. It may be configured to. With such a configuration, it is possible to reliably detect an abnormality relating to payout.

  In the above embodiment, the ball payout device 97 has a configuration capable of executing both ball lending and prize ball payout. However, even if the mechanism that lends the ball and the mechanism that pays out the prize ball are independent, The invention can be applied.

  In the above embodiment, a signal from the main board 31 to the peripheral board is output to each peripheral board via the central relay board 77. The main board 31 is provided with signal direction restricting means for preventing signal input from the centralized relay board 77 (see FIG. 8). Further, the central relay board 77 is provided with signal direction regulating means for preventing signal input from the peripheral board (see FIG. 8). Furthermore, in an electrical component control board equipped with a microcomputer that inputs a signal from the main board 31 and does not send a signal to the main board 31, the signal is input from the central relay board 77 to the central relay board 77. Signal direction restricting means for preventing signal output is provided (for example, the input buffer circuit 102 shown in FIG. 9).

  Since the signal from the main board 31 to each peripheral board is concentrated on the central relay board 77 and the signal output from the main board 31 to the central relay board 77 is provided with signal direction regulating means, the main board It is possible to effectively prevent the input of an illegal signal that illegally generates a big hit with respect to 31.

  In the above embodiment, the presentation control board 80 is exemplified as an electric component control board on which a microcomputer that inputs signals from the main board 31 and does not send signals to the main board 31 is used. If there is another electrical component control board on which a microcomputer that does not send signals to the main board 31 is input, the signal from the main board 31 also passes through the centralized relay board 77 for that board. In addition, a signal direction regulating means for preventing signal output to the central relay board 77 is provided at a portion where a signal is input from the central relay board 77.

  By adopting the configuration as described above, there is a suspicious point in the operation of the gaming machine and an illegal act (an act of inputting a signal causing an illegal big hit to the main board 31, for example, a peripheral board or a board) In the case where it is suspected that an illegal board is connected to the cable between them, it is only necessary to examine the central relay board 77 other than the main board 31. Even if an illegal signal is sent to the central relay board 77 in order to send an illegal signal to the main board 31, the signal is sent to the main board 31 side by the signal direction regulating means mounted on the central relay board 77. This is because the signal transmission is blocked.

  In addition, since only one centralized relay board 77 needs to be investigated, the number of targets that can be fraudulent can be reduced particularly compared to the case where a large number of relay boards are provided. The investigation time can be shortened compared with the case where the relay boards are arranged in cascade. Further, when the central relay board 77 is inspected, it is easy to investigate that the front and back surfaces of the central relay board 77 can be easily seen from the outside of the board box. Further, the substrate box for storing the central relay substrate 77 has a structure that cannot be easily opened, and when it is opened, it is easily grasped. Therefore, it is easy to find fraudulent acts performed on the central relay board 77.

  In the above embodiment, one central relay board 77 is provided for all peripheral boards, but a plurality of relay boards may be provided in parallel. For example, one relay board may be provided for each peripheral board or for several peripheral boards (not all peripheral boards). In such a case, there is a possibility that the investigation time for fraud may be longer, but there is a merit that it is easy to route the wiring inside the gaming machine.

  In the above embodiment, the central relay board 77 is firmly stored in the board box and cannot be easily detached from the gaming machine. However, instead of using a one-way screw, a general screw is used. A simple fixing method such as fixing with, for example, may be used. In that case, the central relay board 77 is removed from the gaming machine using a screwdriver (driver) as a jig or a coin. Even when a simple fixing method is used, since the front and back surfaces of the central relay board 77 can be easily visually recognized from the outside of the board box, the central relay board 77 can be easily investigated.

  Thus, it is preferable that the central relay board 77 is detachably mounted from the gaming machine by using a predetermined jig (such as a screwdriver or a cutting tool). This is because the central relay board 77 cannot be easily removed, and illegal acts against the central relay board 77 can be prevented.

  Further, as described above, when the central relay board 77 is removed from the gaming machine, it is more preferable that the central relay board 77 is mounted on the gaming machine so that it cannot be mounted (for example, with a one-way screw) in the same manner as the mounting mode before removal. This is because it can be easily recognized that the central relay board 77 has been illegally removed.

  In the above embodiment, the game control means on the main board 31 controls the light emitters provided on the game board 6, but the light emitters provided on the game board 6 are controlled by the game. Even if it is configured to be controlled by a control means other than the means (for example, a production control means or a microcomputer other than the production control microcomputer that controls the light emitter in the game machine), The invention can be applied.

  In the above embodiment, the signal from the main board 31 is routed through the centralized relay board 77, but the peripheral board for the payout control board 37 (the signal is input from the payout control board 37) from the payout control board 37. Each signal output to the circuit board) may be routed through a single relay board on which a unidirectional circuit that passes only in the direction from the payout control main board 37 to the peripheral board is mounted. For example, when a ball-out lamp indicating that the supply ball is out of control is controlled by a dispensing control microcomputer mounted on the dispensing control board 37, those lamps or those lamps are mounted. Each signal including a signal to the board may be routed through one relay board. In such a configuration, as in the prevention and investigation of fraud on the main board 31, it is ensured that the fraud signal is input to the payout control board 37 so that the game ball is illegally paid out. It can be prevented and it becomes easy to investigate whether or not fraudulent activity has been made. Further, as in the case of the main board 31, a plurality of relay boards may be installed in parallel as the relay boards with respect to each peripheral board or a plurality of peripheral boards.

  In each of the above embodiments, different expressions such as transmission / reception and output / input are used for the exchange of various signals, but transmission and output or reception and input are used in substantially the same meaning. Needless to say, these expressions are interchangeable. In addition, the transmission / reception of signals having many meanings such as control commands is made transmission / reception, and the transmission / reception and output / input are made of transmission / reception of signals for transmitting information by switching on / off. There are also cases where they are used properly. Even in this case, these expressions are interchangeable.

  In each of the above embodiments, the on / off state of the signal may be a high level state / low level state, and conversely may be a low level state / high level state.

  Note that the pachinko gaming machine of each of the above embodiments mainly has a predetermined game value when the stop symbol of the special symbol variably displayed on the variable display portion 9 based on the start winning is a combination of the predetermined symbols. It is a first type pachinko gaming machine that can be granted to the player, but if there is a winning in a predetermined area of the electric game that is released based on the start winning, the second type that can be given a predetermined gaming value to the player A third type in which a predetermined right is generated or continued if there is a prize for a predetermined electric combination that is released when a stop symbol of a symbol that is variably displayed based on a start winning prize is a combination of a predetermined pattern The present invention can be applied even to a pachinko gaming machine. Furthermore, the present invention can be applied to a slot machine as long as it has a configuration including a main board and a payout control board.

  The present invention can be applied to games such as pachinko gaming machines, and in particular, can be applied to gaming machines in which game control means and payout control means are provided separately.

It is the front view which looked at the pachinko machine from the front. It is the rear view which looked at the gaming machine from the back. It is the front view and sectional drawing which show a ball dispensing apparatus. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the example of a circuit structure for transmitting the signal transmitted / received between a card unit and a payout control board. It is a block diagram which shows the connection state of the main board | substrates provided in the game machine. It is explanatory drawing which shows the components mounted in the signal output part in a main board | substrate, and the concentrated relay board | substrate. FIG. 12 is a block diagram illustrating circuit configuration examples of an effect control board, a frame side lamp driver board, and a sound control board. It is a block diagram which shows the structural example of a power supply board. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which the microcomputer for game control in a main board | substrate performs. It is a flowchart which shows the main process which the microcomputer for game control in a main board | substrate performs. It is a flowchart which shows payout starting command transmission processing. FIG. 11 is a timing chart showing how the microcomputer operates when power supply to a gaming machine is started and when power supply is stopped. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a power-off process. It is a flowchart which shows a power-off process. It is explanatory drawing which shows the buffer used by switch processing. It is a flowchart which shows an example of a switch process. It is explanatory drawing which shows an example of the content of a control signal. It is a block diagram which shows the signal wire | line etc. which are used for transmission / reception of a control signal. It is a timing diagram which shows an example of the method of outputting a prize ball control signal. It is a timing chart showing an example of how to output a prize ball count signal. It is a timing chart showing an example of how to output a payout error signal. It is a flowchart which shows a prize ball process. It is explanatory drawing which shows the structural example of a prize ball number table. It is a flowchart which shows a prize ball number addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball waiting processing 1. It is a flowchart which shows a prize ball transmission process. It is a flowchart which shows the winning ball waiting process 2. FIG. It is a flowchart which shows prize ball waiting processing 3. It is explanatory drawing which shows the example of bit allocation of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a timing diagram for demonstrating communication between a prepaid card unit and a game machine. It is a flowchart which shows the main process which the microcomputer for payout control performs. It is a flowchart which shows the timer interruption process which the microcomputer for payout control performs. It is a flowchart which shows a payout motor control process. It is a flowchart which shows a main control communication process. It is a flowchart which shows a prize ball REQ interruption process. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a prize ball lending control process. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a timing diagram for explaining a ball biting detection process. It is a timing diagram for demonstrating a ball biting cancellation | release process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows a display control process. It is a flowchart which shows the main process which the microcomputer for production control performs. It is a flowchart which shows the V blank interruption process which the microcomputer for production control performs. It is a block diagram which shows the other circuit structural example of a game control board (main board | substrate).

Explanation of symbols

1 Pachinko machine 31 Game control board (main board)
37 Dispensing control board 56 CPU
69 Delay Circuit 80 Production Control Board 97 Ball Dispensing Device 101 Production Control CPU
301 payout count switch 371 payout control CPU
374 LED for error display
375 Error release switch 917 Capacitor (backup power supply)
920 Power supply monitoring circuit

Claims (9)

A gaming machine in which a player can play a predetermined game using a game medium and pays out the game medium to the player based on the fact that a payout condition is satisfied,
A game control board equipped with a game control microcomputer for executing a game control process for controlling the progress of the game;
A payout means for paying out the game medium;
A payout control board equipped with a payout control microcomputer for executing payout control processing for controlling the payout means;
A payout that detects a payout of a prize game medium as a free gift based on establishment of a payout condition by a game and a payout of a rental game medium based on fulfillment of a payout condition by a loan request, and outputs a detection signal to the microcomputer for payout control Detection means;
An operation means for outputting an operation signal in response to an operation;
An effect control board equipped with an effect control microcomputer for controlling an effect device for performing a game effect according to a control signal from the game control microcomputer;
A relay board for relaying the control signal output from the game control microcomputer to the effect control microcomputer;
The game control board is provided with a signal direction regulating means for blocking input of a signal from the relay board,
The game control microcomputer is:
A game control variation data storage unit that stores an execution state of the game control process and retains the stored content for a predetermined period even when power supply to the gaming machine is stopped.
A payout command signal that outputs a payout command signal capable of specifying the number of premium game media to be paid out to the payout control microcomputer together with a take-in signal instructing the take-in of the command signal based on the establishment of the payout condition by the game Output means;
A payout control start signal output means for outputting a payout control start signal to the payout control microcomputer together with the take-in signal when power supply to the gaming machine is started and the execution of the game control process becomes possible;
After the payout control start signal output means outputs the payout control start signal, a game control operation signal check means for checking whether or not the operation signal is output from the operation means,
When the game control operation signal confirmation means confirms that the operation signal is not output, the game control process execution state is determined based on the stored contents held in the game control variation data storage means. An execution state return means for game control to be returned;
When the game control operation signal confirmation means confirms that the operation signal has been output, the game control process is initialized by initializing the stored contents held in the game control variation data storage means. Execution state initialization means for game control to start from the state,
The dispensing control microcomputer is:
A payout control variation data storage means for storing the execution state of the payout control process and retaining the stored content for a predetermined period even when the power supply to the gaming machine is stopped;
Interrupt processing execution means for updating the value of the specific register to a predetermined value in response to the input of the capture signal from the game control microcomputer and interrupting the payout control processing to execute the interrupt processing When,
Interrupt prohibiting means for controlling an interrupt disabled state for prohibiting execution of interrupt processing by the interrupt processing executing means;
A payout command signal input means for inputting the payout command signal from the payout command signal output means in the interrupt processing;
The number of prize game media payouts specified by the payout command signal input by the payout command signal input means is stored in the payout control variable data storage means, and the payout stored in the payout control variable data storage means A prize game medium payout control means for executing a payout process for controlling the payout means to pay out a plurality of prize game media;
A payout determining means for determining whether the detection signal input from the payout detecting means is a payout of the premium game medium or the rented game medium;
When it is determined by the payout determination means that the detection signal is due to payout of the prize game medium by the prize game medium payout control means, the prize control medium of the prize game medium payout control means is sent to the game control microcomputer. Count signal output means for outputting a prize game medium count signal indicating detection of payout;
Initial setting means for executing an initial setting process for initial setting of an internal state of the payout control microcomputer after the interruption prohibiting means controls the interruption prohibiting state when power supply to the gaming machine is started When,
Register checking means for checking whether or not the value of the specific register is the predetermined value after the initial setting processing is executed by the initial setting means;
A payout control activation signal input means for inputting the payout control activation signal from the payout control activation signal output means when the register confirmation means confirms that the value of the specific register is the predetermined value;
An operation signal confirmation means for payout control for confirming whether or not the operation signal is output from the operation means, on condition that the payout control activation signal input means inputs the payout control activation signal;
When the payout control operation signal confirming means confirms that the operation signal is not output, the payout control process execution status is determined based on the stored contents held in the payout control variation data storage means. An execution state return means for payout control to be returned;
When the operation signal confirmation means for payout control confirms that the operation signal is output, the storage content held in the change data storage means for payout control is initialized and the payout control process is initialized. Execution state initialization means for payout control to start from the state;
An error state setting means for shifting a control state related to payout to an error state when a predetermined condition is satisfied;
An abnormality notification means for outputting an abnormality detection signal indicating the fact to the microcomputer for game control when the error state setting means shifts to an error state;
The production control microcomputer includes error notification means for notifying that the control state related to payout has shifted to an error state,
The game control microcomputer has an abnormality notification signal output means for outputting an abnormality notification signal for notifying the production control microcomputer of an abnormality in response to an input of an abnormality detection signal from the abnormality notification means. Including
The counting signal output means outputs the prize game medium counting signal even when the error state setting means has shifted to the error state.
The game control microcomputer notifies the fact that the error notification means has shifted to the error state based on the abnormality notification signal from the abnormality notification signal output means. It is possible for a player to play a predetermined game by launching the game medium into the game area. Based on the fact that the game medium has won the predetermined prize area, the prize game medium is paid out as a prize. A gaming machine that pays out a rental game medium to be lent to a player based on a loan request signal from a loan request reception device that has received a loan request,
Launching means for launching the game medium toward the game area;
A game control board equipped with a game control microcomputer for executing a game control process for controlling the progress of the game;
A payout means for paying out the game medium;
An input unit to which a lending request accepting apparatus connection signal indicating that the lending request accepting apparatus is connected to a gaming machine is input, a payout control microcomputer that executes a payout control process for controlling the payout means, and A photocoupler that transmits a connection signal to the payout control microcomputer based on the input of the lending request receiving device connection signal from the lending request receiving device, and is connected between the input unit and the photocoupler. A payout control board with a capacitor mounted thereon;
A lending request accepting device relay board that relays the lending request signal from the lending request accepting apparatus and outputs it to the payout control board;
Firing stop means for stopping the operation of the launching means when a connection signal transmitted from the photocoupler is not input;
A payout that detects a payout of a prize game medium as a free gift based on establishment of a payout condition by a game and a payout of a rental game medium based on fulfillment of a payout condition by a loan request, and outputs a detection signal to the microcomputer for payout control Detection means;
An operation means for outputting an operation signal according to the operation,
The game control microcomputer is:
A game control variation data storage unit that stores an execution state of the game control process and retains the stored content for a predetermined period even when power supply to the gaming machine is stopped.
A payout command signal that outputs a payout command signal capable of specifying the number of premium game media to be paid out to the payout control microcomputer together with a take-in signal instructing the take-in of the command signal based on the establishment of the payout condition by the game Output means;
A payout control start signal output means for outputting a payout control start signal to the payout control microcomputer together with the take-in signal when power supply to the gaming machine is started and the execution of the game control process becomes possible;
After the payout control start signal output means outputs the payout control start signal, a game control operation signal check means for checking whether or not the operation signal is output from the operation means,
When the game control operation signal confirmation means confirms that the operation signal is not output, the game control process execution state is determined based on the stored contents held in the game control variation data storage means. An execution state return means for game control to be returned;
When the game control operation signal confirmation means confirms that the operation signal has been output, the game control process is initialized by initializing the stored contents held in the game control variation data storage means. Execution state initialization means for game control to start from the state,
The dispensing control microcomputer is:
A payout control variation data storage means for storing the execution state of the payout control process and retaining the stored content for a predetermined period even when the power supply to the gaming machine is stopped;
Interrupt processing execution means for updating the value of the specific register to a predetermined value in response to the input of the capture signal from the game control microcomputer and interrupting the payout control processing to execute the interrupt processing When,
Interrupt prohibiting means for controlling an interrupt disabled state for prohibiting execution of interrupt processing by the interrupt processing executing means;
A payout command signal input means for inputting the payout command signal from the payout command signal output means in the interrupt processing;
The number of prize game media payouts specified by the payout command signal input by the payout command signal input means is stored in the payout control variable data storage means, and the payout stored in the payout control variable data storage means A prize game medium payout control means for executing a payout process for controlling the payout means to pay out a plurality of prize game media;
A payout determining means for determining whether the detection signal input from the payout detecting means is a payout of the premium game medium or the rented game medium;
When it is determined by the payout determination means that the detection signal is due to payout of the prize game medium by the prize game medium payout control means, the prize control medium of the prize game medium payout control means is sent to the game control microcomputer. Count signal output means for outputting a prize game medium count signal indicating detection of payout;
Initial setting means for executing an initial setting process for initial setting of an internal state of the payout control microcomputer after the interruption prohibiting means controls the interruption prohibiting state when power supply to the gaming machine is started When,
Register checking means for checking whether or not the value of the specific register is the predetermined value after the initial setting processing is executed by the initial setting means;
A payout control activation signal input means for inputting the payout control activation signal from the payout control activation signal output means when the register confirmation means confirms that the value of the specific register is the predetermined value;
An operation signal confirmation means for payout control for confirming whether or not the operation signal is output from the operation means, on condition that the payout control activation signal input means inputs the payout control activation signal;
When the payout control operation signal confirming means confirms that the operation signal is not output, the payout control process execution status is determined based on the stored contents held in the payout control variation data storage means. An execution state return means for payout control to be returned;
When the operation signal confirmation means for payout control confirms that the operation signal is output, the storage content held in the change data storage means for payout control is initialized and the payout control process is initialized. Execution state initialization means for payout control to start from the state;
An error state setting means for shifting a control state related to payout to an error state when a predetermined condition is satisfied;
Input state determining means for determining an input state of the connection signal according to an input state of the connection signal transmitted from the photocoupler;
Connection error notification for executing connection error notification processing for notifying that the lending request acceptance device is not connected to a gaming machine when the input state determination means determines that the connection signal is not transmitted Processing means,
The gaming machine characterized in that the counting signal output means outputs the premium game medium counting signal even when the error state setting means has shifted to the error state. The gaming machine according to claim 2, wherein the connection signal transmitted from the photocoupler is branched and input to a payout control microcomputer and a launch board for transmitting a launch control signal for driving the launching means. The payout control microcomputer shifts to a stopped state in which the control is stopped when a predetermined waiting period has elapsed without inputting a payout control start signal from the payout control start signal output means. Item 4. A gaming machine according to any one of Items 3 to 3. The dispensing control microcomputer
A communication abnormality detecting means for detecting that an abnormality relating to communication has occurred when a predetermined standby period has elapsed without inputting a dispensing control activation signal from the dispensing control activation signal output means;
The gaming machine according to any one of claims 1 to 4, further comprising: a communication abnormality notifying unit that notifies that when the communication abnormality detecting unit detects that an abnormality has occurred. An allowance signal output means for outputting an allowance signal for enabling the game control microcomputer and the payout control microcomputer to be operable when power supply to the gaming machine is started;
When the payout control microcomputer and the game control microcomputer become operable based on the allowance signal from the allowance signal output means, the time is specified more than when the payout control microcomputer becomes operable. The gaming machine according to any one of claims 1 to 5, further comprising delay means for delaying a period to make the game control microcomputer operable. A prize game medium payout notification means for notifying that a prize game medium has been paid out by the prize game medium payout control means;
The game control microcomputer, in response to the input of the prize game medium count signal, causes the prize game medium payout notifying means to notify that the prize game medium has been paid out by the prize game medium payout control means. The gaming machine according to any one of claims 1 to 6. The payout control microcomputer includes a lending game medium payout control means for executing a lending process for controlling a payout means to pay out a predetermined number of lending game media based on establishment of a payout condition based on a lending request,
The payout determination means receives the detection signal from the payout detection means when neither the payout process by the prize game medium payout control means nor the lending process by the rental game medium payout control means is executed. The gaming machine according to any one of claims 1 to 7, wherein the game machine is determined to be a payout of a prize game medium by the prize game medium payout control means. The dispensing control microcomputer
Lending game medium number data storage means for storing lending game medium number data indicating the number of lending game media to be paid out by lending processing by the lending game medium payout control means;
The number of rented game media even when the error state setting means shifts to an error state in response to the determination by the payout determination means that the detection signal input from the payout detection means is due to payout of the rented game media The gaming machine according to claim 8, further comprising: lending game medium number data subtracting means for subtracting lending game medium number data stored in the data storage means.

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