JP2003115875A - Method and device for controlling transmission of atm cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of cell transmission delay while performing address polling operation according to UTOPIA level 2. SOLUTION: Concerning each FIFO 22, the 'stored cell absence' state of storing no ATM cell in any FIFO 22 is managed and when a new ATM cell is written into any FIFO 22 in the 'stored cell absence' state, the PHY number of a PHY layer function part 1 which is a destination to transmit the new ATM cell is outputted as a transmitting address. Then, the ATM cell is transmitted after confirming whether each PHY layer function part 1 can receive the cell. By starting such address polling operation from the relevant PHY layer function part, the preferential transmission of that new ATM cell is performed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ATM (Asynchor)
onous transfer mode (cell) transmission control method and apparatus, and particularly to an ATM layer function unit and a plurality of PHYs (Physic
al Layer Protocol) An ATM that controls the transmission of ATM cells based on the UTOPIA level 2 system defined by the ATM Forum as an interface with the layer function unit.
The present invention relates to a cell transmission control method and device.

[0002]

2. Description of the Related Art In the ATM forum, UNI (User-N
etwork Interface) and NNI (Network-Network Interf)
ACE) protocol configuration, ALL (ATM Aplicati) is used as the data link layer (second layer) of the OSI reference model.
on layer) and ATM layer, and defines the physical layer (first layer)
As the PHY layer. The ATM functional unit that realizes the ATM layer assembles / disassembles ATM cells, and the PHY functional unit that realizes the PHY layer
ATM cells are encoded / decoded.

These ATM layer functional units and a plurality of PHYs
The ATM forum defines the UTOPIA level 2 system as an interface with the layer function unit. According to this regulation, PHYs are assigned to multiple PHY layer functional units.
By assigning a number and polling the PHY number from the ATM layer function unit using the transmission address, it is possible to recognize whether the PHY layer function unit of the ATM cell destination can receive and handshake with the receivable PHY layer function unit. After that, the ATM cell is to be delivered.

The PHY number polling order for the PHY layer functional unit is not specified in detail, and the currently implemented ATM layer functional unit considers the simplification of the circuit configuration and the like, and the order of notifying the PHY number is ascending order. Allocations are being made. In addition, a method of unconditionally notifying the PHY number regardless of whether it is used or not is used for the maximum number of PHYs that can be handled by the ATM layer function unit.

FIG. 4 shows a transmission connection configuration of the ATM layer function section and the PHY layer function section. The ATM layer function unit 2 and each PHY layer function unit 1 are connected in a bus format based on the UTOPIA level 2. ATM layer function unit 2
Sends an ATM cell to each PHY layer function unit 1 as a UTOPIA level 2 master. A maximum of 31 PHY layer functional units can be connected.

Signals used in this interface include transmission data for transferring an ATM cell from the ATM layer function unit 2 to the PHY layer function unit 1, a transmission address for polling the PHY layer function unit 1, and a PHY layer function unit 1. Is a transmission CLAV that reports whether or not the ATM cell can be transmitted to the ATM layer function unit 2, and the ATM layer function unit 2
Is a transmission enable that notifies the PHY layer function unit 1 that the data is valid at the time of ATM cell transmission, and a transmission SO that notifies the PHY layer function unit 1 of the start position of the transmission ATM cell.
There is C. Further, all control signals of UTOPIA level 2 are synchronized with the transmission clock. The transmission address is composed of 5 bits and indicates the PHY number (00hh) of the PHY layer function unit 1. The transmission data is 8 bits (or 1
6 bits).

FIG. 5 shows the configuration of the conventional ATM layer function unit 2. The ATM layer function unit 2 includes an ATM cell switching control unit 21, a FIFO (# 00 to # 1E) 22,
A FIFO management unit 23, an ATM cell transmission unit 24, a transmission clock generation unit 25, a transmission address generation unit 26, and a transmission CLAV monitoring unit 27 are provided. FIFO (Firs
The t-In First-Out buffer) 22 is provided for each PHY layer function unit 1, and A for the PHY layer function unit 1 is provided.
Stores TM cells. ATM cell switching control unit 2
1 stores an ATM cell generated in response to a notification from a higher-layer protocol or the like in the FIFO 22 corresponding to the destination PHY layer function unit 1.

[0008] The ATM cell transmission unit 24 is a FIFO designated after the handshake process with the PHY layer function unit 1.
The ATM cell is read out from 22 and is output as transmission data, and at the same time, transmission SOC and transmission enable are controlled. The FIFO management unit 23 manages the FIFO write address of the ATM cell switching control unit 21 and the FIFO read address of the ATM cell transmission unit 24. The transmission CLAV monitoring unit 27 monitors the transmission CLVA from each PHY layer function unit 1 and notifies the ATM cell transmission unit 24 of cell reception availability. The transmission clock generator 25 is an ATM
Cell transmission unit 24, transmission address generation unit 26 and each PH
The transmission clock is supplied to the Y layer functional unit 1.

FIG. 6 shows a conventional timing chart.
Here, the ATM cell switching control unit 21
AT to PHY layer functional unit 1 with PHY number "1Ch"
The case where M cells are stored in the FIFO 22 is shown.
Since the FIFO storage processing is performed asynchronously with the UTOPIA level 2, the FIFO storage completion is at the position of the transmission clock phase “5”. The transmission address at this time indicates "02h".

When the FIFO storage in FIG. 6 is completed, the FI
The FO management unit manages the ATM cell storage state in each FIFO, and the ATM cell transmission unit confirms the FIFO according to the transmission address from the transmission address generation unit. Therefore,
P stored in the FIFO in the transmission clock phase “5”
The ATM cell addressed to the HY number "1Ch" is in a transmission waiting state in which it is unconditionally stored in the FIFO until the clock phase "56" after which the transmission address becomes "1Ch". After "1Ch" is generated in the transmission address, a handshake process is performed between the ATM layer function unit 2 and the PHY layer function unit 1, and the handshake process is performed depending on whether the PHY layer function unit 1 can receive cells. ATM cells are read out from the FIFO 22 and transmitted.

[0011]

However, in such a conventional ATM cell transmission control method, a new ATM cell is generated because the ATM cell generated in the ATM layer functional unit and the polling of the transmission address are asynchronous. In that case, even if there is no other ATM cell to be transmitted to the ATM layer function unit, it is necessary to wait for the address of the destination PHY layer function unit to be polled, and the ATM cell stays in the ATM layer function unit. The maximum transmission clock is 61 clocks, which causes a problem of cell transmission delay.

In order to solve such a problem, it has been proposed to use a software algorithm to select a PHY layer functional unit satisfying a predetermined condition for each clock phase to transmit an ATM cell. However, for example, see Japanese Patent Laid-Open No. 11-177566 and the like, a configuration for realizing high-speed processing is required in order to process a software algorithm within one transmission clock, which is a factor of increasing the complexity and cost of the device. Becomes The present invention is intended to solve such problems, and the UTO
It is an object of the present invention to provide an ATM cell transmission control method and device capable of suppressing the occurrence of cell transmission delay with a relatively simple configuration while performing an address polling operation according to PIA level 2.

[0013]

In order to achieve such an object, an ATM cell transmission control method according to the present invention comprises:
The UT defined by the ATM Forum as an interface between the ATM layer function part and a plurality of PHY layer function parts.
Based on OPIA level 2, the PHY number pre-assigned to each PHY layer functional unit is sequentially output as a transmission address to perform an address polling operation, thereby confirming whether each PHY layer functional unit can receive an ATM cell. If the PHY layer functional unit is receivable, the P
By sending an ATM cell to the HY layer functional unit,
An ATM cell transmission control method for controlling transmission of ATM cells as an ATM layer function part, wherein each ATM is controlled by using a plurality of FIFOs provided for each PHY layer function part.
The FI corresponding to the PHY layer function part of the transmission destination of the cell
Each of them is stored in the FO, and when it is confirmed by the address polling operation that the PHY layer functional unit is receivable, the ATM cell is read from the FIFO corresponding to the PHY layer functional unit and transmitted.
When the "no storage cell" state in which no ATM cell is stored in any FIFO is managed and a new ATM cell is written to the FIFO in the "no storage cell" state,
By outputting the PHY number of the PHY layer function unit which is the destination of the new ATM cell as a transmission address and starting the address polling operation from the PHY layer function unit, priority transmission of the new ATM cell is performed. It was done.

Regarding the management of the "no storage cell" state,
It is also possible to count the number of times of writing and reading of the ATM cell for each FIFO, and to manage the "no storage cell" state based on these numbers.

Each FIFO has a P corresponding to the FIFO.
A write address equal to the PHY number of the HY layer function unit is given to each of the new ATs at the time of priority transmission.
The address polling operation may be started from the PHY layer functional unit by outputting the write address of the FIFO in which M is written as the transmission address.

Further, the ATM cell transmission control device according to the present invention preliminarily assigns to each PHY layer functional unit based on UTOPIA level 2 defined by the ATM Forum as an interface between the ATM layer functional unit and a plurality of PHY layer functional units. The assigned PHY number is sequentially output as a transmission address and an address polling operation is performed to confirm whether ATM cells can be received by each PHY layer function unit. If the PHY layer function unit can receive the PHY number, the PHY number is received. An ATM cell transmission control device for controlling transmission of ATM cells as an ATM layer function section by transmitting ATM cells to the layer function section, which is provided for each PHY layer function section and addressed to the PHY layer function section. The ATM cell is stored, and the PH A plurality of FIFOs from which the stored ATM cells are read when it is confirmed that the layer function unit is receivable, a transmission address generation unit that sequentially generates a transmission address for the address polling operation, and an ATM is used for each FIFO. A FIFO management unit that manages the "no storage cell" state in which no cell is stored, and gives a priority transmission instruction for a new ATM cell when a new ATM cell is written to the FIFO in the "no storage cell" state A transmission address setting unit is provided, and in the transmission address generation unit, a PHY that is a transmission destination of a new ATM cell according to a priority transmission instruction.
By outputting the PHY number of the layer function unit as the transmission address, the address polling operation is started from the PHY layer function unit, thereby performing preferential transmission of a new ATM cell.

Regarding the management of the "no storage cell" state,
The FIFO management unit may count the number of times of writing and reading of the ATM cell for each FIFO, and manage the "no storage cell" state based on these numbers.

For each FIFO, the P corresponding to that FIFO
A write address equal to the PHY number of the HY layer function unit is given, and the transmission address setting unit notifies the write address of the FIFO in which the new ATM is written as the change address when the priority transmission instruction is given, and the transmission address is generated. The address polling operation may be started from the PHY layer functional unit by outputting the changed address notified as the priority transmission instruction as the transmission address.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an ATM layer function according to an embodiment of the present invention. At ATM Forum UTOPIA Level 2,
The control when the ATM layer function unit 2 transmits and receives ATM cells to and from the plurality of PHY layer function units 1 is defined. The present invention is based on UTOPIA level 2
The present invention relates to ATM cell transmission control when the ATM layer function unit 2 serves as a UTOPIA level 2 master and transmits ATM cells from the ATM layer function unit 2 to the PHY layer function unit 1.

As shown in FIG. 4, the ATM layer function unit (ATM cell transmission control device) 2 is a UTOPIA.
Multiple PH based on level 2 interface
It is connected to the Y layer function unit 1 in a bus format. in this case,
To enable connection with each PHY layer function unit 10,
PHY unique to each PHY layer function unit 1
A number (00h to 1Eh: h is a hexadecimal number) is set in advance and a maximum of 31 PHY layer functional units 1 can be connected.

According to the regulation of UTOPIA level 2, the PHY number is assigned to each PHY layer function unit 1 in this way, and the ATM layer function unit 2 polls the PHY number by using the transmission address to transmit the ATM cell. The cell reception availability of the PHY layer function unit 1 to be recognized is recognized, and the ATM cell is to be transmitted only when reception is possible. Hereinafter, a series of these operations will be referred to as an address polling operation.

As shown in FIG. 4, the ATM layer function unit 2 and each PHY layer function unit 1 include transmission data for transferring an ATM cell from the ATM layer function unit 2 to the PHY layer function unit 1 and PHY layer function. A transmission address for polling the unit 1, a transmission CL for the PHY layer function unit 1 to report to the ATM layer function unit 2 whether or not an ATM cell can be transmitted.
The AV / ATM layer function unit 2 performs PH when ATM cells are transmitted.
These signals are connected by signals of transmission enable for notifying the Y layer functional unit 1 of the validity of data and transmission SOC for notifying the PHY layer functional unit 1 of the start position of the transmission ATM cell. Further, all control signals of UTOPIA level 2 are synchronized with the transmission clock. The transmission address consists of 5 bits, and the PHY number of the PHY layer function unit 1 (00h to 1E)
h) is shown. The transmission data is composed of 8 bits (or 16 bits).

Next, the ATM layer function unit (ATM cell transmission control device) 2 will be described in detail with reference to FIG. The ATM layer function unit 2 includes an ATM cell switching control unit 21, a FIFO (# 00 to # 1E) 22, and a FI.
FO management unit 23, ATM cell transmission unit 24, transmission clock generation unit 25, transmission address generation unit 26, and transmission CLA
A V monitoring unit 27 is provided. In addition to this,
A transmission address setting unit 28 is provided in the ATM layer function unit 2.

The FIFO 22 is provided for each PHY layer functional unit 1
It is a buffer provided for each and stores ATM cells addressed to each PHY layer function unit 1. The ATM cell switching control unit 21 stores the generated ATM cell in the FIFO 22 corresponding to the PHY layer function unit 1. The ATM cell transmission unit 24 performs a handshake process with the PHY layer function unit 1, and when the transmission CLVA monitoring unit 27 reports the transmission CLVA indicating that the cell can be received, the ATM cell transmission unit 24 outputs the ATM cells from the designated FIFO 22. Is output as the transmission data, and at the same time, the transmission SOC and the transmission enable are controlled.

The transmission CLAV monitoring unit 27 monitors the transmission CLVA from each PHY layer function unit 1 and notifies the ATM cell transmission unit 24 of whether or not cells can be received. The transmission clock generation unit 25 supplies the transmission clock to the ATM cell transmission unit 24, the transmission address generation unit 26 and each PHY layer function unit 1.

The FIFO management unit 23 receives the FIFO write address of the ATM cell switching control unit 21 and the AT
The FIFO read address of the M cell transmission unit 24 is managed, and it is monitored whether or not there is no storage cell in which no ATM cell is stored in any FIFO 22. Further, the transmission address setting unit 28 uses the FIF
When the storage cell presence signal from the O management unit 23 determines that there is no storage cell, the write address of the new ATM cell written in the FIFO 22, here the destination PHY number, is fetched and the PHY number is changed. By notifying the transmission address generation unit 26 as the address, the priority transmission instruction of the new ATM cell is performed.

Next, the operation of the ATM layer function unit 2 according to this embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing an ATM cell transmission operation (normal operation) of UTOPIA level 2. The ATM layer function unit 2 executes the address polling operation by sequentially changing the transmission address in the transmission address generation unit 26 based on the transmission clock generated in the transmission clock generation unit 25, thereby performing the address polling operation of each PHY layer function unit 1. Whether or not cells can be received is detected. In UTOPIA level 2,
Since a transmission clock capable of high-speed transfer of several tens of MHz is defined, the transmission address generation unit 26 transmits the PHY number “1Fh” as an unused number between valid PHY numbers to provide a wait time. A handshake with the PHY layer function unit 1 is realized.

For example, in the clock phase "9" of FIG. 2, the transmission address "04h" is output, and the PHY layer functional unit 1 having the PHY number "04h" corresponding thereto is selected. When the PHY layer function unit 1 recognizes the transmission address that matches the PHY number assigned to itself, and if the transmission data (cell) can be received from the ATM layer function unit 2, the next transmission is performed. Send CLAV is notified at clock timing. Transmission address generation unit 26
From the transmission address "04h" to the transmission address "1F" at the next clock (clock phase "10").
h ”is output. At this time, the transmission CLAV from the PHY layer functional unit 1 is monitored by the transmission CLAV monitoring unit 27, so that the AT for the specified PHY layer functional unit 1 is detected.
Recognize that M cells can be transmitted.

When an ATM cell can be transmitted, if there is an ATM cell waiting to be transmitted in the FIFO 22 corresponding to the transmission address, the transmission address generation unit 26 sends the transmission address in the next clock phase "11". Then, "04h" is transmitted again, and the ATM cell transmitter 24 transmits the ATM cell at the timing of the next clock phase "12" in which the PHY layer function unit 1 recognizes the address. At the same time, a transmission enable indicating that the transmission data is valid is output, and the beginning (H1) of the ATM cell is output.
The transmission SOC indicating the position is output. PHY number "0
The PHY layer functional unit 1 of “4h” is based on the transmission address, the transmission enable, and the transmission SOC, and sends the ATM addressed to itself.
Receive cells.

Next, the operation of the ATM layer function unit 2 according to this embodiment will be described with reference to FIG. FIG. 3 is a timing chart showing a transmission operation (priority transmission operation) of UTOPIA level 2. The ATM cell switching control unit 21 recognizes the destination PHY layer function unit 1 of the ATM cell from the ATM header of the ATM cell and stores it in the FIFO (# 00 to # 1E) 22 corresponding to each. The storage process of this FIFO 22 is performed by UTOPI.
It is performed asynchronously with the A level 2 ATM cell transmission process.

The FIFO management section 23 increments the write pointer provided for the FIFO 22 based on the storage address of the ATM cell stored by the ATM cell switching control section 21 to increase the AT.
Count the number of times M cells are written. When an ATM cell is read from each FIFO by the ATM cell transmission unit 24 and transmitted, the read pointer provided for the FIFO 22 is incremented to count the number of ATM cell readings. And FIF
The O management unit 23 detects the difference between the write pointer and the read pointer, and thereby the AT in each FIFO 22 is detected.
Determine if there are M cells left. Therefore, by referring to the pointer values of all the FIFOs 22, it is possible to confirm the presence or absence of a cell waiting to be transmitted in the ATM layer function unit 2.

In this way, the FIFO management unit 23 constantly monitors whether or not the ATM cells are not stored in any of the FIFOs 22 and is in a "no storage cell" state. When the cell is not stored, the FIFO management unit 23 determines that it is in the “no storage cell” state. Then, the ATM cell switching control unit 21 causes the new ATM cell to become a FIFO.
When it is written in 22, if it is in the “no storage cell” state, priority transmission processing is performed for the new ATM cell.

For example, as shown in FIG. 3, P is set based on the transmission address "02h" at the position of the clock phase "5".
When it is confirmed whether or not the ATM cell of the HY layer function unit 1 can be received, the new ATM cell is changed to “# 1” of the FIFO 22.
Consider the case where the data is stored in "C" and the FIFO storage is completed. In the transmission address setting unit 28, the FIFO management unit 23
When the "no storage cell" status is confirmed by
When a new ATM cell is written to the IFO 22, the write address is acquired. And
The write address is notified to the transmission address generation unit 26 as a changed address to give a priority transmission instruction to a new ATM cell.

As a result, the priority transmission process is started, and the transmission address generation unit 26 sends the changed address from the transmission address setting unit 28 at the fall of the transmission clock at the invalid address "1Fh" in the subsequent clock phase "6". Latch, and as the effective address value of the next clock phase “7”, the transmission address of the new ATM cell is “1C”.
h "is transmitted. After the address "1Ch" is changed, a handshake process is performed between the ATM layer function unit 2 and the PHY layer function unit 1 in the same manner as described above, and the ATM cell transmission unit 24 adds a new one from the "# 1C" of the FIFO 22. ATM cell is read and the PHY layer function unit 1 concerned
Sent to.

As described above, since the FIFO management unit 23 manages that all the FIFOs are empty, it is determined whether or not the generated ATM cells may be preferentially transmitted. Therefore, the UTOPIA level 2 is set. While performing the address polling operation according to the following, it is possible to change the address of the ATM cell generated in the state where the transmission cell does not exist in the ATM layer function unit 2 with a relatively simple structure and transmit the ATM cell in the shortest time. It is possible to optimize the staying time of each ATM cell in.

Further, since the "no storage cell" state is managed based on the number of times of writing / reading the ATM cell to / from the FIFO 22, the "no storage cell" state can always be managed with an extremely simple configuration. In addition, since the write address of the FIFO 22 and the transmission address of the PHY layer function unit 1 are matched and the addresses are given, it is not necessary to perform address conversion when giving a priority transmission instruction.
Priority transmission can be executed with a quick and simple configuration. After the priority transmission process is completed, the next transmission address "1D" of the PHY layer function unit 1 which has transmitted the new ATM cell is transmitted.
Since the address polling operation is restarted from "h", it is not necessary to restore the sending address after the priority transmission processing, and the address polling operation can be restarted after the priority transmission processing without requiring a special configuration.

Further, the ATM cell switching control unit 21
Since the ATM cells are transferred between the ATM cell transmitting section 24 and the ATM cell transmitting section 24 using the FIFO 22, if the number of the PHY layer function sections 1 is 31 or less, the unused FIFO is "FIFO in which cells are not always written. ", But the FIFO
The management unit 23 does not need to recognize it and can handle it. Therefore, irrespective of the number of PHY layer function units 1 (up to 31), A is set for all PHY layer function units 1.
The residence time of TM cells can be made equal.

The ATM cell transmitter 24 and other UTOP
When the FIFO is empty without changing the IA interface unit, the transmission address can be changed by the transmission address setting unit 28, so that even if this processing is performed, the UTO
PIA level 2 handshake processing is possible.

In the above description, the optimization of the retention time for the ATM cell that occurs when the maximum number (31) of PHY layer function units 1 is used and there is no transmission ATM cell in the ATM layer function unit 2 has been described. FIFO to connect
By reducing the number, it is possible to reduce the residence time even in the normal polling process. Further, when it is not necessary to average the transmission establishment of ATM cells when there is a lot of traffic, the ATM cells may be transmitted in the order stored in the FIFO.

[0040]

As described above, according to the present invention, each PH
Using a plurality of FIFOs provided for each Y layer functional unit, each ATM cell is stored in the FIFO corresponding to the PHY layer functional unit of the transmission destination, and
When the HY layer functional unit is receivable, the ATM cell is read from the FIFO corresponding to the PHY layer functional unit and transmitted, and for each FIFO, A
It manages the "no storage cell" state in which no TM cell is stored, and the new ATM cell is FI in the "no storage cell" state.
When written to the FO, the PHY number of the PHY layer functional unit that is the destination of the new ATM cell is output as the transmission address, and the address polling operation is performed for the PHY.
By starting from the layer function unit, new ATM cells are preferentially transmitted.
Even if there is no other ATM cell to be transmitted to the TM layer function unit, it is not necessary to wait for the address of the destination PHY layer function unit to be polled, and while performing the address polling operation according to UTOPIA level 2, It is possible to suppress the occurrence of cell transmission delay with a simple structure,
It is possible to optimize the staying time of each ATM cell in the layer function unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an ATM cell transmission control device (ATM layer functional unit) according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation (normal operation) of the ATM cell transmitter.

FIG. 3 Operation of ATM cell transmitter (priority transmission operation)
2 is a timing chart showing

FIG. 4 is a block diagram showing a connection configuration of an ATM layer functional unit and a PHY layer functional unit.

FIG. 5 is a block diagram showing a conventional ATM cell transmission control device (ATM layer functional unit).

FIG. 6 is a timing chart showing the operation of a conventional ATM cell transmitter.

[Explanation of symbols]

1 ... PHY layer function part, 2 ... ATM layer function part (A
TM cell transmission control device), 21 ... ATM cell switching control unit, 22 ... FIFO, 23 ... FIFO management unit, 2
4 ... ATM cell transmitter, 25 ... Transmit clock generator, 2
6 ... Transmission address generation unit, 27 ... Transmission CLAV monitoring unit,
28 ... Transmission address setting section.

Claims (6)

[Claims] 1. Each PH based on UTOPIA level 2 defined by the ATM Forum as an interface between an ATM layer function part and a plurality of PHY layer function parts.
The PHY number pre-assigned to the Y layer functional unit is sequentially output as a transmission address and the address polling operation is performed to confirm whether or not the ATM cell can be received by each PHY layer functional unit. When possible, an ATM cell is transmitted to the PHY layer functional unit to enable the AT to function as the ATM layer functional unit.
An ATM cell transmission control method for controlling transmission of M cells, comprising a plurality of FIs provided for each of the PHY layer functional units.
The FO is used to store each ATM cell in the FIFO corresponding to the destination PHY layer function unit, and when the address polling operation confirms that the PHY layer function unit is receivable, the PHY layer function is received. The ATM cell is read from the FIFO corresponding to the part and transmitted, and the ATM cell is transmitted to each of the FIFOs.
It manages the "no storage cell" state in which no cell is stored, and in the "no storage cell" state, a new ATM cell is
When written to the IFO, the PHY number of the PHY layer functional unit that is the destination of the new ATM cell is output as a transmission address, and the address polling operation is started from the PHY layer functional unit. A characterized in that the new ATM cell is preferentially transmitted.
TM cell transmission control method. 2. The ATM cell transmission control method according to claim 1, wherein the number of times of writing and reading of an ATM cell for each FIFO is counted, and the "no storage cell" state is managed based on these numbers. A characteristic ATM cell transmission control method. 3. The ATM cell transmission control method according to claim 1, wherein each of the FIFOs has a write address equal to a PHY number of a PHY layer function unit corresponding to the FIFO, and when the priority transmission is performed, F where new ATM was written
By outputting the write address of the IFO as the transmission address, the address polling operation is performed for the PH.
An ATM cell transmission control method starting from a Y layer functional unit. 4. Each PH based on UTOPIA level 2 defined by the ATM Forum as an interface between an ATM layer function part and a plurality of PHY layer function parts.
The PHY number pre-assigned to the Y layer functional unit is sequentially output as a transmission address and the address polling operation is performed to confirm whether or not the ATM cell can be received by each PHY layer functional unit. If possible, the ATM cell is sent to the PHY layer function unit to send the ATM cell as the ATM layer function unit.
An ATM cell transmission control device for controlling transmission of M cells, wherein the PHY layer functional unit is provided for each of the PHY layer functional units.
A plurality of FIFOs for storing the ATM cells addressed to the layer functional unit and reading the stored ATM cells when the address polling operation confirms that the PHY layer functional unit is receivable, and the address polling operation. And a FIFO management unit that manages a “no storage cell” state in which no ATM cells are stored in any of the FIFOs, and a “storage cell no” state. The new ATM cell is the F
A transmission address setting unit that gives a priority transmission instruction of the new ATM cell when written to the IFO, and the transmission address generation unit is a destination of the new ATM cell according to the priority transmission instruction. By outputting the PHY number of the PHY layer function unit as a transmission address to start the address polling operation from the PHY layer function unit, thereby performing priority transmission of the new ATM cell. Cell transmission controller. 5. The ATM cell transmission control device according to claim 4, wherein the FIFO management unit is an ATM for each FIFO.
An ATM cell transmission control device, characterized in that the number of times of cell writing and the number of times of reading are respectively counted and the "no storage cell" state is managed based on these numbers. 6. The ATM cell transmission control device according to claim 4, wherein each FIFO has a write address equal to a PHY number of a PHY layer function unit corresponding to the FIFO, and the transmission address setting unit is At the time of the priority transmission instruction, the write address of the FIFO in which the new ATM is written is notified as a change address, and the transmission address generation unit outputs the change address notified as the priority transmission instruction as a transmission address. An ATM cell transmission control device, wherein the address polling operation is started from the PHY layer functional unit.