JP4031002B2 - ATM cell transfer system and address polling control method - Google Patents

Description

  The present invention relates to an ATM cell transfer system in which an ATM layer function unit and a plurality of PHY layer function units are connected by a UTOPIA level 2 bus interface (hereinafter referred to as UTOPIA L2 bus), and in particular, an ATM layer function in this ATM cell transfer system. The present invention relates to an address polling control method for determining an address when polling a plurality of PHY layer function units from a unit.

  As an ATM cell transfer method when an ATM layer function unit and a plurality of PHY layer function units are multi-connected, a UTOPIA level 2 bus interface (hereinafter, UTOPIA L2 bus) is defined in the ATM Forum.

  FIG. 6 shows a configuration of a conventional ATM cell transfer system in which an ATM layer function unit and a PHY layer function unit are connected by a UTOPIA L2 bus. In this conventional ATM cell transfer system, as shown in FIG. 6, the ATM layer function unit 71 and the PHY layer function unit 2 are connected in a bus format based on UTOPIA L2. The ATM layer function unit 71 operates as a master of the UTOPIA L2 bus 3 and transmits an ATM cell to each PHY layer function unit 2. A maximum of 31 PHY layer function units 2 can be connected to the ATM layer function unit 71.

  The UTOPIA L2 bus 3 includes transmission data (TxDATA) for transferring ATM cells from the ATM layer function unit 71 to the PHY layer function unit 2, a transmission address (TxADDR) for polling the PHY layer function unit 2, and a PHY layer function unit 2. Is a transmission club (TxClav) for reporting whether or not a cell can be received to the ATM layer function unit 71, a transmission enable (TxEnb) indicating that transmission data is valid to the PHY layer function unit 2 when the ATM layer function unit 71 transmits a cell, and a PHY layer This is made up of a control signal composed of a transmission SOC (TxSOC) for notifying the function unit 2 of the start position of data. All control signals are driven in synchronization with the transmission clock (TxCLK). The transmission address TxADDR is composed of 5 bits and indicates the PHY number (00h to 1Eh) of the PHY layer function unit 2.

  In the UTOPIA L2 bus 3, for cell transfer processing from the ATM layer function unit 71 to the PHY layer function unit 2, a PHY number is assigned in advance to each of the plurality of PHY layer function units 2, and a transmission address (TxADDR) is sent from the ATM layer function unit 71. Is defined as a method of recognizing whether or not the PHY layer function unit 2 that is a cell transmission destination can receive and polling the PHY number.

  The operation of ATM cell transfer in the conventional address polling control method in such an ATM cell transfer system will be described with reference to FIGS.

  A basic configuration example of the conventional ATM layer function unit 71 is shown in FIG. 7, and a timing chart thereof is shown in FIG.

  The ATM layer function unit 71 includes an ATM switching function unit, a cell buffer memory 12, an ATM cell transmission unit 13, and a transmission clock generation unit 17.

  The ATM switching function unit 11 stores the cell in the cell buffer memory 12 divided for each PHY layer function unit 2 based on the information of the header of the ATM cell. The storing operation from the ATM switching function unit 11 to the cell buffer memory 12 is performed independently and asynchronously with the cell transmission operation of the ATM cell transmission unit 13.

  The ATM cell transmission unit 13 performs address polling by sequentially changing TxADDR (assuming ascending order in FIG. 8) based on TxCLK generated by the clock generation unit 17, and confirms whether each PHY layer function unit 2 can receive signals. is doing. In the address polling, the ATM cell transmission unit 13 waits for a response from the PHY layer function unit 2 by inserting the PHY number “1Fh” as an unused number and inserting a wait time between effective addresses.

  In FIG. 8, TxADDR “01h” is transmitted at the timing of clock “4”, and the PHY layer function unit (01h) corresponding to this is selected. When the PHY layer function unit (01h) recognizes the same TxADDR as the PHY number assigned to the PHY layer function unit (01h), if the cell can be received, the PHY layer function unit (01h) notifies the TxClav at the next clock “5” timing. The ATM cell transmission unit 13 inserts “1F” into address polling at the timing of the clock “5” and puts a wait time. When TxClav is input at this time, the selected PHY layer function unit (01h) can receive data. Recognize that.

  When it is recognized that the selected PHY layer function unit (01h) is receivable, the ATM cell transmission unit 13 determines that the clock “6” if the cell buffer memory has a transmission standby cell corresponding to the PHY layer function unit (01h). TxADDR “01h” is transmitted again at the timing of “”. Then, the PHY layer function unit (01h) starts data transfer at the timing of the clock “7” for recognizing TxADDR. Simultaneously with the start of data transfer, TxEnb indicating the validity of transmission data and TxSOC indicating the head of data transfer are notified. The PHY layer function unit (01h) receives a cell addressed to itself based on TxADDR, TxEnb, and TxSOC.

  During cell transfer to the PHY layer function unit (01h), address polling is continuously performed from the next PHY number “02h” (timing of clock “8”). When the PHY layer function unit (04h) capable of receiving the next cell is recognized as shown in the timing of the clock “13”, the ATM cell is recognized in the same manner as the address polling to the PHY layer function unit (01h). The transmission unit 13 reserves the PHY layer function unit (04h) for the next cell transfer. When the cell transfer to the PHY layer function unit (01h) is completed at the timing of the clock “59”, the cell transfer to the reserved PHY layer function unit (04h) is started from the timing of the clock “61” with one clock. To start.

  In the conventional transfer method described above, polling to each PHY layer function unit 2 is performed at a fixed number of times by all PHY layer function units 2 regardless of the transmission frequency.

  Assume that 10 transmission standby cells are stored in the cell buffer memory (01h), and the transmission standby cells destined for the other PHY layer function unit 2 are 0 cells. Even in this case, since the polling operation is performed for all the PHY layer function units 2 at a fixed number of times, the transmission cell to the PHY layer function unit (01h) has no other transmission cell. It stays in the cell buffer memory 12 for a polling period × N (N is the order stored in the cell buffer memory).

  As described above, the conventional polling method for cell transfer processing employs an order confirmation method such as ascending order or descending order in order to simplify the circuit scale. In addition, this is a method of notifying the PHY layer function unit 2 whether the PHY layer function unit 2 is used or not, by notifying the PHY number of the maximum number of PHY layer function units that the ATM layer function unit 71 can handle.

  In the above polling, the cell transmission frequency to each PHY layer function unit 2 is transmitted uniformly (cell transmission to each PHY layer function unit is the same band) regardless of whether each PHY layer function unit 2 is used or not used. Has been done. For this reason, the residence time of the cell of the PHY function part with a high transmission frequency increases, and there is a problem that the cell buffer memory overflows and causes the cell to be discarded.

For example, Patent Literature 1 introduces a polling control method for solving such a problem. This polling control method has a PHY number conversion register write function and a PHY number conversion register function, and can change the address polling order arbitrarily. However, it does not have a function of determining whether the PHY layer function unit is used / not used and the transmission frequency. For this reason, it is necessary for the user to directly write to the register, and the apparatus cannot autonomously change the polling order. This has the disadvantage that it is not possible to flexibly adapt to various traffic conditions.
JP-A-11-27276

  In the conventional polling described above, the cell transmission frequency to each PHY layer function unit, or whether the PHY layer function unit is used or not used is uniform (cell transmission to each PHY layer function unit is the same band). Sending is taking place. For this reason, the residence time of the cell of the PHY layer function part with a high transmission frequency increases, and there is a problem that the cell buffer memory overflows and causes the cell to be discarded.

  An object of the present invention is to provide a system that enables efficient ATM cell transfer by performing polling according to the frequency of cell transmission to each PHY layer function unit.

  The present invention is applied to an ATM cell transfer system in which an ATM layer function unit and a plurality of PHY layer function units are multi-connected by a UTOPIA level 2 bus interface.

In order to achieve the above object, an ATM cell transfer system according to the present invention is an ATM cell transfer system in which an ATM layer function unit and a plurality of PHY layer function units are connected by a UTOPIA level 2 bus interface,
The ATM layer function unit is
An ATM switching function unit that switches an ATM cell to be transmitted to the PHY layer function unit for each PHY layer function unit as a destination based on information of the header;
A cell buffer memory for storing each ATM cell switched by the ATM switching function unit for each PHY layer function unit;
A cell counter that counts the ATM cells for each of the PHY layer function units stored in the cell buffer memory as the number of standby cells;
An ATM cell transmitter for performing ATM cell transmission processing in conformity with UTOPIA level 2;
A threshold setting register in which the number of transmissions corresponding to the threshold of the number of standby cells and the range of the number of standby cells set by the threshold is stored;
Comparing the number of standby cells for each of the PHY layer function units counted by the cell counter with a threshold set in the threshold setting register, and controlling the ATM cell transmission unit based on the comparison result And a transmission address control unit for controlling address polling.

  In addition, the transmission address control unit, based on a comparison result between the number of standby cells for each PHY layer function unit counted by the cell counter and a threshold set in the threshold setting register, each PHY layer The number of transmissions in one polling cycle for each functional unit may be determined, and the ATM cell transmission unit may be controlled so that the determined number of transmissions is realized.

Further, the transmission address control unit,
Polling that monitors the address signal output from the ATM cell transmission unit to each PHY layer function unit, outputs a signal that triggers the determination of the number of polls for each polling period, and transfers the address signal for polling control An address monitoring unit;
In response to a signal from the polling address monitoring unit, the number of cells waiting in the cell counter is compared with a threshold value set in the threshold value setting register to determine the number of transmissions in one polling period for each PHY layer function unit. A polling frequency determination unit to perform,
The number of transmissions for each PHY layer function unit determined by the polling number determination unit is determined based on an address signal transferred from the polling address monitoring unit in the next polling address period, You may make it comprise from the polling control part reflected in the polling address production | generation of an ATM cell transmission part.

  According to the present invention, the cell counter counts the number of standby cells for each PHY layer function unit stored in the cell buffer memory, and compares it with the threshold value set in the threshold setting register in the transmission address control unit. Control is performed to change the number of address polling times according to the number of standby cells to the PHY layer function unit. As a result, retention and discard of cells destined for a specific PHY layer function unit are suppressed, and efficient ATM cell transfer with a uniform cell residence time for each PHY layer function unit is enabled.

  As described above, according to the present invention, the cell counter determines the frequency of cell transmission, and the transmission address control unit controls the number of polls to the PHY layer function unit 2 according to this transmission frequency. Therefore, polling of cells with high transmission frequency is prioritized, and the retention and discard of cells destined for a specific PHY layer function unit is suppressed, and the cell residence time for each PHY layer function unit is made uniform. It is possible to obtain an effect that good ATM cell transfer is possible.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the ATM layer function unit 1 in the ATM cell transfer system according to the first embodiment of the present invention. In FIG. 1, the same components as those in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted.

  The ATM cell transfer system of this embodiment has a configuration in which the ATM layer function unit 71 is replaced with the ATM layer function unit 1 shown in FIG. 1 in contrast to the conventional ATM cell transfer system shown in FIG.

  As shown in FIG. 1, the ATM layer function unit 1 in the ATM cell transfer system of the present embodiment includes an ATM switching function unit 11, a cell buffer memory 12, an ATM cell transmission unit 13, a cell counter 14, and a transmission. An address control unit 15, a threshold setting register 16, and a transmission clock generation unit 17 are provided.

  The ATM layer function unit 1 in this embodiment is different from the ATM layer function unit 71 in the conventional ATM cell transfer system shown in FIG. 7 in that a cell counter 14, a transmission address control unit 15, and a threshold setting register 16 are provided. It is a newly added configuration.

  The ATM switching function unit 11 switches an ATM cell (hereinafter abbreviated as a cell) to be transmitted to the PHY layer function unit 2 for each PHY layer function unit serving as a destination based on the information of the header, thereby switching the cell buffer. Store in the memory 12.

  The cell buffer memory 12 stores the ATM cell switched by the ATM switching function unit 11 for each PHY layer function unit 2.

  The cell counter 14 counts the ATM cells for each PHY layer function unit 2 stored in the cell buffer memory 12 as the number of standby cells.

  The ATM cell transmission unit 13 performs ATM cell transmission processing conforming to UTOPIA level 2.

  The threshold setting register 16 stores the threshold of the number of standby cells and the number of transmissions corresponding to the range of the number of standby cells set by this threshold.

  The transmission address control unit 15 compares the number of standby cells for each PHY layer function unit 2 counted by the cell counter 14 with the threshold set in the threshold setting register 16, and based on the comparison result, the ATM cell Address polling is controlled by controlling the transmitter 13. More specifically, the transmission address control unit 15 is based on the comparison result between the number of standby cells for each PHY layer function unit 2 counted by the cell counter 14 and the threshold set in the threshold setting register 16. The number of transmissions in one polling period for each PHY layer function unit 2 is determined, and the address polling frequency control of the ATM cell transmission unit 13 is performed so that the determined number of transmissions is realized.

  For example, it is assumed that 10 cells are destined for the PHY layer function unit (01h) in the cell buffer memory 12. If “5” is set as the threshold for the number of standby cells and “2” is set as the number of transmissions in the threshold setting register 16 at this time, transmission to the address “01” is continued twice in the next address polling. To be implemented.

  In this way, the transmission frequency of each PHY layer function unit 2 is determined from the number of standby cells in the cell buffer memory, and the specific PHY layer function unit 2 is controlled by controlling the number of polls to the PHY layer function unit 2 according to the transmission frequency. In addition to suppressing the retention and discarding of cells, it is possible to achieve efficient ATM cell transfer with uniform cell residence time for each PHY function unit 2.

  Next, FIG. 2 shows the configuration of the transmission address control unit 15 which is a characteristic part in the ATM cell transfer system of this embodiment.

  As shown in FIG. 2, the transmission address control unit 15 includes a polling address monitoring unit 21, a polling frequency determination unit 22, and a polling control unit 23.

  The polling address monitoring unit 21 monitors the address signal (TxADDR) output from the ATM cell transmission unit 13 to each PHY layer function unit 2 and outputs a signal that triggers the determination of the number of times of polling for each polling period. Further, the polling address monitoring unit 21 transfers TxADDR to the polling control unit 23 for polling control.

  The polling frequency determination unit 22 compares the count value of the cell counter 14 with the setting value of the threshold setting register 16 triggered by a signal from the polling address monitoring unit 21, and transmits the number of transmissions in one polling cycle for each PHY layer function unit 2. Is transmitted to the polling control unit 23.

  The polling control unit 23 determines the control timing based on the TxADDR received from the ATM cell transmission unit 13 in the next polling address cycle, based on the information on the number of transmissions for each PHY layer function unit received from the polling number determination unit 22. This is reflected in the polling address generation of the cell transmission unit 13.

  Next, the operation of the ATM cell transfer system of this embodiment will be described in detail with reference to the drawings.

Operations of the cell counter 14 and the transmission address control unit 15 will be described. (See Figure 2.)
The polling address monitoring unit 21 monitors an address signal (TxADDR) output from the ATM cell transmission unit 13 to each PHY layer function unit 2. A signal that triggers the polling count determination is output to the polling count determination unit 22 at every polling cycle (for example, every recognition of TxADDR “00h”).

  The polling frequency determination unit 22 reads the count value of the cell counter 14 in response to a signal from the polling address monitoring unit 21 and simultaneously clears the count value of the cell counter 14. The read value is compared with the set value of the threshold value setting register 16 to determine the number of transmissions in one polling period for each PHY layer function unit 2 and transmit to the polling control unit 23.

  The polling control unit 23 determines the control timing based on the TxADDR received from the polling address monitoring unit 21 after one polling period for the information on the number of transmissions for each PHY layer function unit 2 received from the polling number determination unit 22, and transmits ATM cells. This is reflected in the polling address generation of the unit 13.

  The polling frequency control from the polling control unit 23 to the ATM cell transmission unit 13 is performed by two control signals “REPEAT” and “SKIP”. REPEAT is a signal representing a repeat request for cell transmission to the PHY layer function unit 2. SKIP represents a SKIP request for polling to the next PHY layer function unit 2. SKIP is 5 bits and notifies the SKIP width of the polling address.

  FIG. 3 shows an example of processing in the ATM cell transfer system of this embodiment. Here, in order to simplify the explanation, the number of addresses is changed from 31 to 4. That is, here, description will be made assuming that there are only four addresses 00h, 01h, 02h, and 03h as addresses of the PHY layer function unit 2.

  The threshold value setting register 16 can set a plurality of threshold values. Here, by setting “the number of cells = 0, the number of transmissions = 0” as the threshold value, it is possible to eliminate polling to the PHY layer function unit 2 having no cell to be transmitted and reduce the residence time of useless cells. It is. For the PHY layer function unit 2 with a large number of standby cells, for example, by setting the threshold value as “number of standby cells = 5 or more, the number of transmissions = 2”, for example, It is possible to increase the number of polls in one cycle and reduce the residence time.

  Here, it is assumed that the number of standby cells of each PHY layer function unit (00h, 01h, 02h, 03h) 2 in the cell counter 14 is “1”, “6”, “0”, and “2”, respectively. Then, the polling frequency determination unit 22 refers to the setting value in the threshold setting register 16 and determines that the number of transmissions to the PHY layer function unit (00h) 2 is one, and to the PHY layer function unit (01h) 2 The number of transmissions is determined to be 2, the number of transmissions to the PHY layer function unit (03h) 2 is determined to be 0, and the number of transmissions to the PHY layer function unit (03h) 2 is determined to be 1 .

  For this reason, the polling control unit 23 initially polls each PHY layer function unit (00h, 01h, 02h, 03h) 2 in one polling cycle for each address 00h. Controls the ATM cell transmitter 13 so that polling is performed once, twice for the address 01h, 0 times for the address 02h, and once for the address 03h.

  Next, the operation of the ATM layer function unit 1 in this embodiment will be described with reference to FIG. FIG. 4 is a timing chart of the polling frequency control in the present invention.

  The basic cell transfer operation between the ATM layer function unit 1 and the PHY layer function unit 2 is the same as the operation in the conventional ATM cell transfer system. When the ATM layer function unit 1 polls the PHY layer function unit 2 with TxADDR and recognizes that reception is possible with TxClav from the selected PHY layer function unit 2, the ATM layer function unit 1 drives TxDATA, TxEnb, and TxSOC control signals. Then, the cell is transferred to the PHY layer function unit 2.

  It is assumed that the PHY layer function unit (01h) 2 has been confirmed to stay in the cell by the operation of the transmission address control unit 15 described above and the polling number determination unit 22 has determined “number of transmissions = 2”. In the address polling, when the PHY layer function unit “01h” is selected at the timing of the clock “4”, the polling control unit 23 drives the REPEAT signal at the timing of the clock “5”, and sends the PHY signal to the ATM cell transmission unit 13. The cell function repeat request to the layer function unit (01h) is notified. The ATM cell transmission unit 13 recognizes the repetition of polling to the PHY layer function unit (01h) by the REPEAT signal, and stops address polling while the REPEAT signal is driven. The TxADDR while the address polling is stopped is fixed to the PHY layer function unit (01h) 2 that is transmitting.

  The cell transfer operation from the ATM cell transmission unit 13 to the PHY layer function unit (01h) 2 is performed in the same manner as in the prior art. When the cell transfer to the PHY layer function unit (01h) 2 is completed at the timing of the clock “59”, the second cell from the timing of the clock “61” to the repeatedly requested (01h) with one clock is placed. Start transferring.

  The polling control unit 23 stops driving the REPEAT signal at the timing of the next clock “62” when the transfer to the second cell is started, and repeatedly notifies the ATM cell transmission unit 13 of the request cancellation. The ATM cell transmitter 13 recognizes that the request has been repeatedly canceled by the REPEAT signal and restarts address polling from the timing of the clock “63”.

  As described above, when the number of transmissions of the PHY layer function unit is “N times” in the polling number determination unit 22, the polling control unit 23 sends a REPEAT signal to the ATM cell transmission unit 13 as “N−1 cell”. Multiple output control is realized by outputting the same amount.

  Further, it is assumed that there is no retention of cells in the PHY layer function unit (03h) 2 and the polling frequency determination unit 22 determines that “the number of transmissions = 0”. When the polling control unit 23 recognizes TxADDR (02h) at the timing of the clock “63”, it drives the SKIP signal at the timing of the clock “64”. The ATM cell transmission unit 13 recognizes SKIP using the SKIP signal, and polls the PHY layer function unit (04h) 2 by skipping the PHY layer function unit (03h) 2 at the timing of the clock “65”.

  As described above, when the number of transmissions of the PHY layer function unit 2 is “0” in the polling number determination unit 22, the polling control unit 23 outputs a SKIP signal to the ATM cell transmission unit 13. The polling SKIP to the PHY layer function unit 2 is realized. The SKIP signal is 5 bits and represents the SKIP width with 5 bits. If it is determined that “number of transmissions = 0” from the PHY layer function unit (03h) 2 to the PHY layer function unit (07h) 2, the SKIP signal is notified as “05h”. The ATM cell transmission unit 13 recognizes the SKIP width and performs polling from the PHY layer function unit (08h) 2 that skips five PHY layer function units 2 at the timing of the clock “65”.

  According to the present embodiment, the cell counter 14 for determining the cell transmission frequency and the transmission address control unit 15 for controlling the number of polling times based on the transmission frequency are determined according to the present embodiment. Since the number of polls to the PHY layer function unit 2 is controlled according to the transmission frequency, the bandwidth can be flexibly changed according to the traffic situation. In addition, since the polling of unused PHYs is SKIPed to limit the polling address, efficient ATM cell transfer is enabled. And the retention and discard of the cell for specific PHY layer function part 2 can be controlled by performing polling of the cell with high transmission frequency a plurality of times.

  In addition, similarly, the cell counter 14 for determining the cell transmission frequency and the transmission address control unit 15 for controlling the number of polling based on the transmission frequency are used, and the polling to the unnecessary PHY function unit 2 is controlled by the SKIP control. Shortened and efficient cell transfer becomes possible.

  Furthermore, since the cell transmission frequency is monitored in one polling cycle based on the state of the cell buffer memory 12, it is possible to flexibly respond to difficult traffic situations and change the bandwidth at the physical layer level. It becomes.

(Second Embodiment)
Next, an ATM cell transfer system according to the second embodiment of the present invention will be described.

  The polling control method described in the first embodiment is adapted to polling of cell transmission processing from the ATM layer function unit to the PHY layer function unit. It is possible to apply the present invention to polling of cell reception processing of the ATM layer function unit, that is, cell transmission processing from the PHY layer function unit to the ATM layer function unit in a substantially similar manner. The ATM cell transfer system according to the second embodiment of the present invention is an application of the present invention to cell transmission processing from a PHY layer function unit to an ATM layer function unit.

  FIG. 5 shows the configuration of the ATM cell transfer system according to the second embodiment of the present invention. In this embodiment, an ATM layer function unit 51 and a plurality of PHY layer function units 52 are multi-connected by a UTOPIA level 2 bus interface 3.

  Each PHY layer function unit 52 of the present embodiment stores an ATM cell transmission unit 25 that performs transmission processing of cells destined for the ATM layer function unit 51 as a UTOPIA level 2 slave, and cells destined for the ATM layer function unit. Cell buffer memory 26, cell counter 27 that counts the cells stored in the cell buffer memory, threshold setting register 28, and the number of cells in cell counter 27 is compared with the value of threshold setting register 28 to determine the number of cells. A determination unit 29 is provided for making an address polling control request when the threshold value is exceeded.

  The ATM layer function unit 51 includes an ATM cell reception unit 30 that performs cell reception processing as a UTOPIA level 2 master, and a reception address control unit 31 that controls reception address polling based on a request from the PHY layer function unit 2. And a transmission number setting register 32 which serves as an index in the control of the reception address.

  In UTOPIA level 2, the cell reception operation from each PHY layer function unit 52 of the ATM layer function unit 51 includes received data (RxDATA) for transferring an ATM cell from the PHY layer function unit 52 to the ATM layer function unit 51, and a PHY layer function. A reception address (RxADDR) for polling the unit 52, a reception club (RxClav) for the PHY layer function unit 52 to notify the ATM layer function unit 51 of the presence / absence of a received cell, and an PHY layer function unit 1 at the time of cell reception The layer function unit 52 is realized by a reception enable (RxEnb) indicating that the received data is valid. The PHY layer function unit 52 is realized by a control signal including a reception SOC (RxSOC) that notifies the ATM layer function unit 51 of the start position of the received data. .

  The PHY layer function unit 52 recognizes its own PHY number by RxADDR from the ATM layer function unit 51, and when the cell for the ATM layer function unit 51 is stored in the cell buffer, the ATM layer function unit by RxClav 51 is notified. The ATM layer function unit 51 recognizes the presence / absence of a reception cell by RxClav, and shifts to a cell reception process from the PHY layer function unit 52.

  In the present embodiment, the determination unit 29 of the PHY layer function unit 52 checks the number of cells stored in the cell buffer memory 26 at a constant cycle (polling cycle) from the cell counter 27 and exceeds the value of the threshold setting register 28. When the cell stays, the ATM layer processing unit 51 is notified of a request for reception polling control using a REQUEST signal. The ATM layer processing unit 51 recognizes the cell retention in the PHY layer function unit 52 by the REQUEST signal from the PHY layer function unit 52. Then, the reception address control unit 31 performs repetitive polling control of the PHY layer function unit 52 on the ATM cell reception unit 30 by the number of times set in the transmission number setting register 32 in the next polling cycle.

  As a result, the ATM layer function unit 51 determines the reception frequency based on the REQUEST signal from the PHY layer function unit 52, and controls the number of receptions from the PHY layer function unit 52 in which the cells are retained, so that the PHY layer function unit 52 It is possible to realize efficient cell transfer while suppressing the retention of cells.

It is a block diagram which shows the structure of the ATM layer function part 1 in the ATM cell transfer system of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the transmission address control part 15 in FIG. It is a figure which shows an example of the process in the ATM cell transfer system of the 1st Embodiment of this invention. It is a timing chart which shows operation | movement of the ATM cell transfer system of FIG. It is a block diagram which shows the structure of the ATM cell transfer system of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the conventional ATM cell transfer system. It is a block diagram which shows the structure of the ATM layer function part 71 in the conventional ATM cell transfer system. It is a timing chart which shows operation | movement of the ATM layer function part 71 shown in FIG.

Explanation of symbols

1 ATM layer functional part 2 PHY layer functional part 3 UTOPIA level 2 bus interface (UTOPIA L2 bus)
DESCRIPTION OF SYMBOLS 11 ATM switching function part 12 Cell buffer memory 13 ATM cell transmission part 14 Cell counter 15 Transmission address control part 16 Threshold setting register 17 Transmission clock generation part 21 Polling address control part 22 Polling frequency determination part 23 Polling control part 25 ATM cell transmission part 26 Cell Buffer Memory 27 Cell Counter 28 Threshold Setting Register 29 Judgment Unit 30 ATM Cell Receiving Unit 31 Reception Address Control Unit 32 Transmission Count Setting Register 33 Reception Clock Generation Unit 51 ATM Layer Function Unit 52 PHY Layer Function Unit 71 ATM Layer Function Unit 71

Claims (5)

In an ATM cell transfer system in which an ATM layer functional unit and a plurality of PHY layer functional units are connected by a UTOPIA level 2 bus interface, an address for polling the plurality of PHY layer functional units from the ATM layer functional unit is set. An address polling control method for determining,
Switching ATM cells to be transmitted from the ATM layer functional unit to the PHY layer functional unit for each PHY layer functional unit serving as a destination based on information in the header;
Storing the switched ATM cells for each of the PHY layer functional units;
Counting the stored ATM cells for each PHY layer function unit as the number of standby cells;
The counted number of standby cells for each PHY layer function unit is compared with a preset threshold value of the number of standby cells, and address polling is performed by controlling the ATM cell transmission unit based on the comparison result. Performing the control;
Address polling method with   In the step of controlling the address polling, one polling period for each PHY layer function unit based on a comparison result between the counted number of standby cells for each PHY layer function unit and a preset threshold value 2. The address polling method according to claim 1, wherein the number of transmissions is determined and transmission control of ATM cells is performed so that the determined number of transmissions is realized. An ATM cell transfer system in which an ATM layer functional unit and a plurality of PHY layer functional units are connected by a UTOPIA level 2 bus interface,
The ATM layer function unit is
An ATM switching function unit that switches an ATM cell to be transmitted to the PHY layer function unit for each PHY layer function unit serving as a destination based on information in the header;
A cell buffer memory for storing each ATM cell switched by the ATM switching function unit for each PHY layer function unit;
A cell counter that counts the ATM cells for each of the PHY layer function units stored in the cell buffer memory as the number of standby cells;
An ATM cell transmitter for performing ATM cell transmission processing in conformity with UTOPIA level 2;
A threshold setting register in which the number of transmissions corresponding to the threshold of the number of standby cells and the range of the number of standby cells set by the threshold is stored;
Comparing the number of standby cells for each of the PHY layer function units counted by the cell counter with a threshold set in the threshold setting register, and controlling the ATM cell transmission unit based on the comparison result A transmission address control unit for controlling address polling by
ATM cell transfer system.   The transmission address control unit, based on a comparison result between the number of standby cells for each PHY layer function unit counted by the cell counter and a threshold value set in the threshold setting register, each PHY layer function unit 4. The ATM cell transfer system according to claim 3, wherein the number of transmissions in each polling period is determined, and the ATM cell transmission unit is controlled so that the determined number of transmissions is realized. The transmission address control unit
Polling that monitors the address signal output from the ATM cell transmission unit to each PHY layer function unit, outputs a signal that triggers the determination of the number of polls for each polling period, and transfers the address signal for polling control An address monitoring unit;
In response to a signal from the polling address monitoring unit, the number of cells waiting in the cell counter is compared with a threshold value set in the threshold value setting register to determine the number of transmissions in one polling period for each PHY layer function unit. A polling frequency determination unit to perform,
The number of transmissions for each PHY layer function unit determined by the polling number determination unit is determined based on an address signal transferred from the polling address monitoring unit in the next polling address period, A polling control unit for reflecting the polling address generation of the ATM cell transmission unit;
The ATM cell transfer system according to claim 3 or 4, comprising:

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