JP2003109957A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and its manufacturing method, in which a via-hole opening failure, stepping of an overlying interconnect layer, increase of via hole resistance, lowering of interconnect reliability, and the like, can be prevented without requiring any extra step for planarization by setting the layout rule of an underlying wiring layer appropriately. SOLUTION: The semiconductor device comprises an underlying wiring layer 2, an overlying wiring layer 7, and an interlayer insulation film 6 including an SOG film 4 for insulating these wiring layers wherein the underlying wiring layer 2 is connected electrically with the overlying wiring layer 7 through a via hole made in the interlayer insulation film 6. The underlying wiring layer 2 is patterned such that the ratio of line width/space interval is not larger than 2, or it has more than one slit and is patterned such that the ratio of line width/slit width between the slits is not larger than 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including an SOG (Spin on Glass) film as an inter-layer insulating film of a multi-layer metal wiring layer and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent semiconductor devices, a multi-layer metal wiring structure is generally used in order to increase the operating speed, increase the degree of freedom in layout, and achieve high integration. ing. In a multi-layer wiring structure, a plurality of metal wiring layers are insulated and separated by an interlayer insulating film, and a so-called via hole is opened in the interlayer insulating film at a place where conduction is required between the plurality of metal wiring layers, and through the portion. The structure is such that the upper and lower metal wiring layers are electrically connected. The upper surface of the interlayer insulating film is not affected by the steep step of the pattern of the metal wiring layer below the interlayer insulating film,
It needs to be flattened.

If the upper surface of the interlayer insulating film is not sufficiently flattened, (1) the metal wiring formed on the interlayer insulating film is disconnected due to the step of the interlayer insulating film. (2) Via holes or interlayer insulating At the time of exposure of the photoresist when patterning the metal wiring formed on the film, defocus due to the step occurs, and the desired pattern cannot be obtained. (3) When performing dry etching of the via hole opening, Due to insufficient flatness, the etching at the location where the interlayer insulating film becomes thicker does not reach the surface of the lower metal wiring, so that necessary conduction cannot be obtained or via holes are opened in a thick insulating film to obtain conduction. If the dry etching conditions of are matched, the thin part will be over-etched. (4) When forming the metal wiring layer after opening the via hole,
The aspect ratio of the via hole becomes large at the portion where the interlayer insulating film becomes thick, and the sufficient metal wiring material is not embedded in the via hole, so that the via hole resistance becomes high. As a result, the yield of semiconductor devices and the reliability thereof are deteriorated.

Therefore, as a technique for flattening the interlayer insulating film,
A method using an SOG film or CMP (Chemical Mechanical
Polish) is available. The former is relatively easy to introduce into the manufacturing process because it can be performed with equipment equivalent to photoresist coating, and the running cost is low, but the manufacture of semiconductor devices using the latest miniaturization technology In, the precision of flattening is inferior to the latter. The latter is capable of flattening that is compatible with cutting-edge miniaturization technology,
A large amount of capital investment is required for introduction into the manufacturing process, and running costs are also high.

From the above, the manufacturing line of the semiconductor device, in which the manufacturing cost is more important than the precision of the planarization, more specifically, the line width of the metal wiring which is the base of the interlayer insulating film. For manufacturing a semiconductor device having a space interval of about 0.8 μm or more, generally,
A planarization technique using an SOG film as shown in FIGS. 5 and 6 has been performed.

First, as shown in FIG. 5A, a first insulating film 1 is deposited on a semiconductor substrate on which transistors and capacitors (not shown) are formed, and a lower wiring layer 2 is formed thereon. And the second insulating film 3 is formed on the entire surface. Next, as shown in FIG. 5B, an SOG film is deposited as a third insulating film 4 on the entire surface of the second insulating film 3 by a coating method. At this time, the SOG film having high fluidity flows into the space of the patterned lower wiring layer 2, whereby the surface can be flattened. In addition, S
In some cases, after the OG film is applied, the interlayer insulating film is thinned by performing etch back by dry etching, or a plurality of SOG films are applied in layers for further planarization.

Next, as shown in FIG. 5C, an insulating film containing SiO ₂ as a main component is formed as the fourth insulating film 5 on the entire surface of the third insulating film 4 to form the interlayer insulating film 6. Form. Then, as shown in FIG. 5D and FIG.
With respect to the interlayer insulating film 6, a via hole 8 is opened in a portion where electrical continuity is required between the lower wiring layer 2 serving as the lower layer and the upper wiring layer 7 serving as the upper layer, and the upper wiring layer is formed on the interlayer insulating film 6. Form 7.

However, according to this method, as shown in FIGS. 5D and 6, the layout is such that the lower wiring layers 2 are densely arranged (the space between the lower wirings is narrow), so that the space interval 10 into which the SOG film flows is reduced. Therefore, the third insulating film 4 made of the SOG film is formed thicker on the lower wiring layer 2 at that portion. Therefore, when the via hole is opened at that portion, the aspect ratio of the via hole becomes large, and it is difficult to fill the wiring material of the upper wiring layer 7 into the via hole (portion D in FIG. 5D). as a result,
The contact resistance in the via hole increases.

On the other hand, as shown in FIG. 7, if the film thickness of the third insulating layer 4 made of the SOG film is made small, the film thickness of the SOG film formed on the lower wiring layer 2 can be made thin, but on the other hand, Since the thickness of the SOG film at the other portions is also thinner, sufficient flatness cannot be achieved and the step becomes large. As a result, when the upper wiring layer 7 is formed thereon, the thickness of the wiring material becomes thin due to the step, and the resistance of the upper wiring layer 7 increases. When the step is extremely large, disconnection occurs due to step breakage (E portion in FIG. 7).

Therefore, there are problems that the operation and speed as designed cannot be obtained, and the reliability decreases due to migration. Further, as shown in FIGS. 8A and 8B, a method of providing a slit 11 on the large-area metal wiring 2 itself has been proposed (Japanese Patent Laid-Open No. 9-199587). However, when the space interval of the lower wiring layer 2 by the opening slit 11 is insufficient, the filling of the wiring material into the via hole is still insufficient (G portion in FIG. 8B), and Similar problems occur.

The present invention has been made in view of such a problem, and by setting the layout rule of the lower wiring layer to an appropriate one, it is possible to add a new step for flattening. The present invention provides a semiconductor device and a method for manufacturing the same which can prevent defective opening of a via hole, disconnection of an upper wiring layer, an increase in via hole resistance, and a decrease in wiring reliability.

[0012]

According to the present invention, a lower wiring layer, an upper wiring layer, and S for insulating these wiring layers from each other.
An interlayer insulating film including an OG film, wherein the lower wiring layer is electrically connected to an upper wiring layer via a via hole formed in the interlayer insulating film. Is patterned so that the ratio of line width / spacing is 2 or less, or the lower wiring layer has two or more slits, and the line width / slit width between the slits is Provided is a semiconductor device which is patterned so that the ratio is 2 or less.

Further, according to the present invention, the lower wiring layer is provided on the semiconductor substrate or the insulating film so that the ratio of the line width / the space interval is 2 or less, or the line width between the slits /
Two or more slits are formed by patterning so that the slit width ratio is 2 or less, and S is formed on the lower wiring layer.
An interlayer insulating film including an OG film is formed, a via hole reaching the lower wiring layer is formed in the interlayer insulating film, and an upper layer electrically connected to the lower wiring layer via the via hole on the interlayer insulating film. A method for manufacturing a semiconductor device, which comprises forming a wiring layer, is provided.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor device of the present invention has at least a lower wiring layer, an upper wiring layer, and an interlayer insulating film including an SOG film for insulating these wiring layers. The lower wiring layer and the upper wiring layer are not particularly limited as long as they are formed of a conductive material. For example, an amorphous, single crystal or polycrystalline N-type or P-type elemental semiconductor (for example, silicon) is used. , Germanium, etc.) or compound semiconductors (eg, GaAs, InP, ZnSe, CsS)
Etc.); metals such as gold, platinum, silver, copper, and aluminum; refractory metals such as titanium, tantalum, and tungsten; silicides with refractory metals, polycides, etc .; SnO ₂ , InO ₂ ,
It can be formed of a single layer or a laminated layer of a transparent conductive material such as ZnO or ITO. The film thickness of these is not particularly limited, and usually, it can be formed at about 400 to 11000 nm. These wiring layers are made of a conductive material, for example, a vacuum deposition method, a sputtering method, an EB method, a CVD method.
It can be formed by forming it into a film shape by a known method such as a method, and then patterning it into a desired shape by photolithography and etching steps.

The lower wiring layer is patterned into a predetermined shape according to a desired layout rule according to the type and characteristics of the semiconductor device, but the line width / space interval ratio is 2 or less, preferably 0.2. It is patterned so as to be about ˜2. In this case, the line width is, for example, about 800 to 10,000 nm, and the space interval is, for example, 400 to 5,000.
It can be about nm.

When the width of the lower wiring layer itself is wide, the lower wiring layer has two or more slits in a wide area, and the line width / slit width ratio between the slits is 2 or less. To be patterned. In this case, the large area of the lower layer wiring means, for example, 10,000 to 1
Approximately 00000 nm. The line width is, for example, about 800 to 3500 nm, and the slit width is, for example, about 400 to 1700 nm. The length of the slit is not particularly limited, but can be appropriately adjusted depending on the size of the overlap with the upper wiring layer. For example, a width equal to or larger than the width of the upper wiring layer is suitable.

The lower wiring layer is electrically connected to the upper wiring layer through a via hole formed in an interlayer insulating film, which will be described later. The lower wiring layer has one line width at a position where the via hole is located. It is preferable that patterning is performed such that the pitch of one space interval is less than about 10 μm, and further about 5 μm or less. In addition,
The upper wiring layer and the lower wiring layer may be electrically connected to each other by filling the via hole with the same conductive material as that of the upper wiring layer, but a single layer film or a laminated film of different conductive material is buried as a contact plug. Connected.

The interlayer insulating film is not particularly limited in material, film thickness and the like as long as it can insulate and separate the lower wiring layer and the upper wiring layer from each other. It is preferable to use an SOG film. As the SOG film, any film can be used as long as it is used in this field, but it is preferably made of a SiO ₂ based resin. The thickness of the SOG film is preferably equal to or more than the thickness of the lower wiring layer, for example, 30
The thickness is about 0 to 1200 nm. The SOG film can be formed by a known method such as a spin coating method. The interlayer insulating film may be formed of a single-layer film of SOG film, but may be formed of a laminated film with other one kind or two or more kinds of insulating films. The insulating film in this case is, for example, a silicon oxide film (low temperature oxide film: LTO film, high temperature oxide film: HTO film, plasma TE, etc.).
Examples include various films such as an OS (Tetra-Ethoxy Silane) film, a silicon nitride film or a plasma nitride film, a PSG film, a BSG film, a BPSG film, and the like, and among them, a stack of a plasma oxide film and / or a plasma nitride film. It is preferably composed of a membrane. In particular, it is more preferable that the SOG film has a three-layer structure and a plasma oxide film or a plasma nitride film is laminated on and under the SOG film. The film thickness of the interlayer insulating film is preferably about 250 to 1000 nm regardless of whether it is a single layer film or a laminated film.
These insulating films can be formed by various methods such as normal pressure, reduced pressure, plasma CVD method, sol-gel method, sputtering method and vapor deposition method.

A via hole reaching the lower wiring layer is formed in the interlayer insulating film. The shape, size, number and the like of the via holes can be appropriately adjusted depending on the function and characteristics of the semiconductor device to be obtained, but for example, 1.0 to 2.0 μm.
It is preferable that the via hole has a bottom surface area of about 0.5 to 3 μm ² . From another viewpoint, the via hole has a via hole resistance of 4Ω or less, preferably 3Ω or less, and more preferably 2Ω or less when the upper wiring layer is embedded in the via hole and the upper and lower wiring layers are connected. It is appropriate to set to. The via hole can be formed by a known method such as photolithography and etching.

The semiconductor device and the manufacturing method thereof according to the present invention are
It can be applied not only to a two-layer wiring structure but also to a wiring structure of three or more layers. That is, the lower wiring layer and the upper wiring layer may be the second wiring layer, the third wiring layer, the third wiring layer, the fourth wiring layer, and the like. Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. The steps, conditions, etc. described in the following description are the same as those usually used in the manufacturing process of semiconductor devices, and detailed description thereof will be omitted except for special cases.

Embodiment 1 In the semiconductor device of the present invention, as shown in FIGS. 1D and 2, the interlayer insulating film 6 including the lower wiring layer 2 and the SOG film 4 is formed on the first insulating film 1. And the upper wiring layer 7 are laminated in this order. The lower wiring layer 2 is electrically connected to the upper wiring layer 7 via a via hole formed in the interlayer insulating film 6. The line width 9 of the lower wiring layer 2 is 0.8.
~ 3.3μm, space interval 10 0.4 ~
It is set to 1.7 μm and the pitch 12 is 1 to 5 μm.
Is set to. Also, line width 9 / space interval 1
It is patterned so that the ratio of 0 is 2 or less. This semiconductor device can be formed by the following method.

First, as shown in FIG. 1A, a first layer containing SiO ₂ as a main component is formed above a transistor or a capacitive element (not shown) formed on the surface of a semiconductor substrate (not shown). The insulating film 1 is formed, and a metal thin film, for example, an alloy containing aluminum as a main component is deposited on the entire surface of the insulating film 1 to a thickness of about 400 nm to 1100 nm by using a sputtering device, and photolithography technology and etching technology. Is used to form the lower wiring layer 2 having a desired shape. At this time, the width and space of the lower wiring layer 2, that is, the line width 9 / space space 10 and the pair of line width 9 and space space 10
The pitch 12 consisting of is set to a predetermined value.

Then, an insulating film made of, for example, SiO ₂ and / or SiN is formed on the entire surface of the obtained substrate as the second insulating film 3 by plasma CVD or the like for about 200 to 30.
Deposit 0 nm thick. Then, as shown in FIG. 1B, S is formed as a third insulating film 4 on the entire surface of the obtained substrate.
An SOG film containing an iO ₂ based resin material as a main component is formed to a thickness of about 300 to 1200 nm by a coating method. As a result, the space of the lower wiring layer 2 is filled with the SOG film,
The surface is flattened. Then, heat treatment is performed in a nitrogen atmosphere at about 350 to 400 ° C. for about 30 minutes to densify the SOG film.

On top of that, as shown in FIG.
As the insulating film 5, an insulating film containing SiO ₂ as a main component is deposited to a thickness of about 50 to 400 nm by plasma CVD or the like to form an interlayer insulating film 6. Subsequently, as shown in FIG. 1D, at a predetermined position in the interlayer insulating film 6, that is, at a position where electrical continuity is required between the lower wiring layer 2 and an upper wiring layer 7 formed later. The via hole 8 is opened by the photolithography technology and the etching technology of the interlayer edge film,
After that, a metal thin film, for example, an alloy containing aluminum as a main component is deposited to a thickness of about 1000 nm on the interlayer insulating film 6 using a sputtering device, and the upper wiring layer 7 is formed by the photolithography technique and the metal thin film etching technique. . Thereafter, after undergoing a predetermined process for manufacturing the semiconductor device, it is divided into semiconductor chips and mounted in a predetermined housing to complete the semiconductor device.

In the semiconductor device obtained above, the relationship between the resistance in the via hole for electrically connecting the lower wiring layer 2 and the upper wiring layer 7 and the L / S ratio of the lower wiring layer 2 is shown in FIG. Shown in. In addition, in FIG. 3, pitch 1
2 is about 1 to 5 μm, and the line width of the lower wiring layer 2 is 0.8 to
The design dimension of 3.3 μm is applied. Also, the values are shown when the via hole resistance value of L / S ratio is 0.2 is 1. Furthermore, the via hole resistance changes depending on the via hole diameter, the interlayer film thickness, the metal filling rate in the via hole, the aspect ratio, and the like, and these parameters and the via hole resistance value can be explained by a known relationship.

According to FIG. 3, when the L / S ratio is in the range of 0.2 to 2 (first region), the via hole resistance is small and the range of its variation is also small. Further, the maximum value of the variation is almost the same as the L / S ratio, and satisfies the value of 4 or less which is the specification of the via hole resistance.
That is, by setting the L / S ratio in the range of 0.2 to 2, the depth of the via hole can be made substantially constant, and the via hole resistance can be stabilized without variation and controlled within the specifications. Therefore, at the pitch of 5 μm or less, it is advantageous to set the L / S ratio to 2 or less, and it is understood that the wiring width of about 3.3 μm or less is suitable. Further, in the layout in which the pitch 12 is less than 1 μm, the flattening technique using the SOG film is not generally applied, but the present invention is considered applicable.

On the other hand, when the L / S ratio becomes larger than 2 (second region), the range of its variation and its maximum value are L.
The L / S ratio is 3.5, which spreads as the / S ratio increases.
With the above, the specifications as the resistance of the via hole are exceeded.
This result is due to the unevenness of the thickness of the interlayer insulating film 6 and the step, and the defocus caused during photolithography caused by the unevenness.
This is a general confirmation of etching unevenness at the time of opening a via hole, and by laying out so that the L / S ratio is 2 or less, these problems regarding flatness can be solved.

Further, in the layout in which the pitch 12 is 10 μm or more, there is no L / S ratio with which the stability of the via hole resistance as shown in FIG. 3 is obtained. From this, it is advantageous to set the L / S ratio at the place where the via hole exists and at the place where the pitch 12 is less than 10 μm. In the prior art, the SOG is used for the purpose of ensuring flatness and suppressing an increase in the thickness of the interlayer insulating film.
The film may be formed by coating a plurality of times, or the SOG film may be applied and then the entire surface may be etched back by dry etching. However, in the present embodiment, such a step is not required and flatness is improved. Can be secured. Therefore, an increase in the number of manufacturing processes can be suppressed.

Second Embodiment As shown in FIGS. 4A and 4B, the semiconductor device according to the second embodiment includes an interlayer including a lower wiring layer 2 and an SOG film 4 on a first insulating film 1. The insulating film 6 and the upper wiring layer 7 are laminated in this order. The lower wiring layer 2 is
It is electrically connected to the upper wiring layer 7 through a via hole formed in the interlayer insulating film 6. The lower wiring layer 2 has a width of about 0.8 μm in a region intersecting with the upper wiring layer 7 and has two slits formed therein. The line width 9 between the slits is 0.8 to 3.3 μm, the slit width 10 is 0.4 to 1.7 μm, the length is set slightly longer than the width of the upper wiring layer 7, and the pitch 12 is 1 to 5 μm.
Is set to. Also, line width 9 / space interval 1
It is patterned so that the ratio of 0 is 2 or less. This semiconductor device can be formed by a method substantially similar to that of the first embodiment. Also in this semiconductor device, substantially the same effects as in the first embodiment can be obtained.

[0030]

According to the present invention, the layout rule of the lower wiring layer is patterned so that the line width / space interval ratio is 2 or less, or the lower wiring layer has two or more slits. By improving the flatness of the surface of the inter-layer insulating film formed on the lower wiring layer, the patterning is performed so that the line width / slit width ratio between the slits is 2 or less. You can As a result, the opening defect of the via hole formed in the interlayer insulating film or the variation in the depth, the step disconnection of the upper wiring layer,
It is possible to prevent variation and increase in via hole resistance, and to obtain a highly reliable semiconductor device.

Further, according to the method of manufacturing a semiconductor device of the present invention, the highly reliable and high quality semiconductor device as described above can be simply manufactured without adding a new step for flattening the interlayer insulating film. And it can be manufactured reliably. In other words, SOG film etch-back and SOG
A flat interlayer insulating film can be manufactured without performing coating and forming of the film a plurality of times, and a semiconductor device can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional process diagram of a main part for explaining a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic plan view of a main part in FIG.

FIG. 3 is a graph showing a relationship between a via hole resistance and a line width / space interval ratio of a first metal wiring.

FIG. 4 is a schematic plan view and a sectional view for explaining another embodiment of a semiconductor device of the present invention.

FIG. 5 is a schematic cross-sectional manufacturing process diagram showing a conventional method of manufacturing a semiconductor device.

FIG. 6 is a schematic plan view of a main part in FIG.

FIG. 7 is a schematic cross-sectional view showing another conventional semiconductor device.

FIG. 8 is a schematic plan view and a schematic sectional view of still another conventional semiconductor device.

[Explanation of symbols]

1: first insulating film 2: first metal wiring layer (lower wiring layer) 3: second insulating film 4: third insulating film 5: fourth insulating film 6: interlayer insulating film 7: second metal wiring layer (upper layer Wiring layer) 8: Via hole 9: Line width of first metal wiring layer (line width of lower wiring layer) 10: Space interval of first metal wiring layer (space width of lower wiring layer) 11: Slit 12: Pitch

Continued front page    F term (reference) 5F033 HH03 HH04 HH05 HH06 HH07                       HH08 HH09 HH11 HH13 HH14                       HH18 HH19 HH21 HH27 HH28                       HH30 HH38 JJ01 JJ03 JJ04                       JJ05 JJ06 JJ07 JJ08 JJ09                       JJ11 JJ13 JJ14 JJ18 JJ19                       JJ21 JJ27 JJ28 JJ30 JJ38                       KK03 KK04 KK05 KK06 KK07                       KK08 KK09 KK11 KK13 KK14                       KK18 KK19 KK21 KK27 KK28                       KK30 KK38 MM07 PP06 PP15                       QQ09 QQ74 RR04 RR06 RR09                       RR13 RR14 RR15 SS08 SS10                       SS12 SS13 SS15 SS21 TT02                       UU04 WW00 WW01 XX01 XX04                       XX34

Claims (11)

[Claims] 1. A lower wiring layer, an upper wiring layer, and an interlayer insulating film including an SOG film that insulates these wiring layers from each other, and the lower wiring layer has a via hole formed in the interlayer insulating film. A semiconductor device electrically connected to an upper wiring layer, wherein the lower wiring layer has a line width / space interval ratio of 2
A semiconductor device characterized by being patterned as described below. 2. The line width / space interval ratio is 0.2.
The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 1, wherein the lower wiring layer is patterned so that the pitch of one line width and one space interval is 5 μm or less at the position where the via hole is located. . 4. A lower wiring layer, an upper wiring layer, and an interlayer insulating film including an SOG film that insulates these wiring layers from each other, wherein the lower wiring layer has a via hole formed in the interlayer insulating film. A semiconductor device electrically connected to an upper wiring layer, wherein the lower wiring layer has two or more slits, and a line width / slit width ratio between the slits is 2 or less. A semiconductor device characterized by being patterned as described above. 5. The semiconductor device according to claim 4, wherein the lower wiring layer is patterned so that a pitch of one line width and one slit width is 5 μm or less at a position where the via hole is located. 6. The semiconductor device according to claim 1, wherein the interlayer insulating film further includes a plasma oxide film and / or a plasma nitride film. 7. The semiconductor device according to claim 1, wherein the SOG film is made of SiO ₂ resin. 8. A lower wiring layer having a line width / space interval ratio of 2 or less or a line width / slit width ratio between slits of 2 on a semiconductor substrate or an insulating film.
Two or more slits are patterned and formed as described below, an interlayer insulating film including an SOG film is formed on the lower wiring layer, and a via hole reaching the lower wiring layer is formed in the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: forming an upper wiring layer electrically connected to the lower wiring layer via a via hole on the interlayer insulating film. 9. The via holes are formed with a pitch of 1 line width and 1 space interval in the lower wiring layer or 1.
The pitch consisting of one line width and one slit width is 5μ
9. The method according to claim 8, which is formed above the lower wiring layer in a region patterned to m or less. 10. A plasma oxide film and / or a plasma nitride film is further formed as an interlayer insulating film.
Or the method according to 9. 11. The method according to claim 8, wherein the SOG film is made of SiO ₂ resin.