JP2003101406A - Signal transmission circuit, solid-state imaging apparatus, camera and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission circuit as a shift register, with which stable operation is enabled even when the voltage of a circuit power source is lowered. SOLUTION: The plus side terminal (node N11) of a capacitor (C1) for boot strap is connected to the gate of a capacitance charging transistor (T21) for boot strap on the next stage. Thus, since the boosted voltage of the plus side terminal of the capacitor for boot strap on the preceding stage is applied to the gate of the capacitance charging transistor for boot strap on the next stage at all the time, even when a power supply voltage VDD is lowered, a capacitor (C2) for boot strap on the next stage can be surely charged to the power supply voltage VDD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit which is applied to a shift register for driving a liquid crystal display or a MOS type image pickup device and can be driven at a low voltage.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration example of a conventional signal transmission circuit. In FIG. 5, for convenience of explanation,
Only the four-stage portion of the multi-stage configuration is shown. This signal transmission circuit includes output transistors T12 and T2 for the next stage.
2, T32, T42 and bootstrap capacitance C1,
C2, C3, C4, bootstrap capacitance charging transistors T11, T21, T31, T41, and discharging transistors T13, T14, T23, T24, T33, T.
34, T43, and T44, the power supply voltage VDD,
The drive pulses V1 and V2 and the start pulse VST are supplied.

Next, the operation of the conventional signal transmission circuit thus constructed will be described.

The start pulse VST is logic "High".
When the voltage reaches the level, the first stage bootstrap capacitor charging transistor T11 is turned on, the bootstrap capacitor C1 is charged to the power supply voltage VDD, and the charging voltage of the bootstrap capacitor C1 exceeds the threshold voltage level of the output transistor T12. And the output transistor T1 of the first stage
2 turns on.

After that, when the drive pulse V1 of the logic "High" level is input to the drain of the output transistor T12, the voltage of the drive pulse V1 and the potential difference across the bootstrap capacitor C1 are added to the gate of the output transistor T12. When the gate potential of the output transistor T12 rises above the potential of the drive pulse V1, the drive pulse V1 is used as the output pulse OUT1 from the node N12.

At the same time, the voltage of the node N12 is applied to the gate of the bootstrap capacitance charging transistor T21 in the second stage, the transistor T21 is turned on, and the bootstrap capacitance C2 is charged to the power supply voltage VDD. , When the charging voltage of the bootstrap capacitor C2 exceeds the threshold voltage level of the output transistor T22, 2
The output transistor T22 of the stage turns on.

After that, when the drive pulse V2 of the logic "High" level is input to the drain of the output transistor T22, the potential of the drive pulse V2 and the potential difference between both ends of the bootstrap capacitor C2 are added to the gate of the output transistor T22. When the gate potential of the output transistor T22 rises above the potential of the drive pulse V2, the drive pulse V2 is used as the output pulse OUT2 from the node N22.

At the same time, the voltage of the node N22 is applied to the gate of the bootstrap capacitance charging transistor T31 of the third stage, the transistor T31 is turned on, and the bootstrap capacitance C3 is charged to the power supply voltage VDD. , If the charging voltage of the bootstrap capacitor C3 exceeds the threshold voltage level of the output transistor T32, 3
The output transistor T22 of the stage turns on.

By repeating such an operation, the signal transmission circuit further sequentially outputs the output pulses OUT3 and OUT4.

[0010]

Problems of the conventional signal transmission circuit will be described with reference to FIG.

FIG. 6 is a timing chart showing the pulse voltage of each part in the conventional signal transmission circuit using only NMOS. This circuit is a 5V system circuit, and the voltage amplitudes of the drive pulses V1 and V2 and the power supply voltage VDD are 5V.
The case of V is shown.

In FIG. 5, when the start pulse VST rises to 5V at time t0, the bootstrap capacitance charging transistor T11 in the first stage is turned on,
Bootstrap capacitance C1 is power supply voltage VDD 5
However, when the bootstrap capacitance charging transistor T11 is an enhancement type NMOS, the threshold voltage Vt of the transistor T11 affects the node N11 to which the gate of the output transistor T12 is connected. Of the power supply voltage VDD
(5V-ΔH0), which is lower than 5V, which is 5V, by which the output transistor T12 is turned on.

Next, at time t1, when a drive pulse V1 of 5V is input to the drain of the output transistor T12, the gate of the output transistor T12 (node N11).
Is applied with a voltage HB1 obtained by adding the voltage 5V of the drive pulse V1 and the potential difference (5V-ΔH0) across the bootstrap capacitor C1 to each other, and a pulse of amplitude H1 is output from the node N12.

At the same time, the pulse voltage of the amplitude H1 of the node N12 is applied to the gate of the bootstrap capacitance charging transistor T21 of the second stage, and the transistor T2 is applied.
21 turns on, but the threshold voltage V of the transistor T21
Due to the influence of T, the voltage of the node 21 to which the gate of the output transistor T22 is connected becomes a voltage (H1-ΔH1) lower than the voltage H1 by ΔH1, and the bootstrap capacitance C2 is charged to the voltage (H1-ΔH1). The Rukoto.

Similarly, at times t2, t3, and t4,
The operation at time t1 is repeated.

Thus, in the case of the conventional signal transmission circuit,
Since a voltage of less than 5V is applied to the gate of the bootstrap capacitance charging transistor at the maximum, the bootstrap capacitance can be charged only to a voltage lower than the power supply voltage VDD of 5V. Therefore, the voltages of the nodes N21, N31, and N41 gradually drop,
The signal transmission circuit cannot generate the output pulse after several stages.

In particular, the operation becomes more difficult when the voltage of the power supply system of the circuit is lowered, for example, in the case of a 3V system circuit.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal transmission circuit which is capable of performing stable operation even when the circuit power supply has a low voltage, and which is suitable for low power consumption, Another object of the present invention is to provide a solid-state imaging device to which the signal transmission circuit is applied, a camera equipped with the solid-state imaging device, and a liquid crystal display device to which the signal transmission circuit is applied.

[0019]

In order to achieve the above-mentioned object, a signal transmission circuit according to the present invention comprises a multi-stage circuit, and a signal in which a pulse voltage according to a drive pulse is sequentially output from each stage circuit. In the transmission circuit, each stage circuit has an output transistor that outputs a drive pulse as a pulse voltage to the source, a bootstrap capacitor connected between the gate and the source of the output transistor, and a bootstrap capacitor. To do this, the drain is connected to the power supply or ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the gate is connected to the output transistor in the previous stage in the second and subsequent stages. And a charging transistor connected to the gate.

According to this structure, a voltage higher than the conventional voltage is applied to the gate of the bootstrap capacitance charging transistor at the next stage, so that the gate potential of the bootstrap capacitance charging transistor is higher than the power supply voltage VDD. can do. As a result, the bootstrap capacitor in the next stage can be charged to the power supply voltage VDD, and a drop in the charging voltage to the bootstrap capacitor can be prevented. Therefore, it is possible to prevent the output pulse voltage from gradually decreasing and the output pulse from being stopped at some stages after the number of transmission stages increases.

A signal transmission circuit according to the present invention includes a first discharge transistor whose drain is connected to one end of a bootstrap capacitor and a second discharge transistor whose drain is connected to the other end of a bootstrap capacitor. And a common pulse voltage is applied to the gates of the first and second discharge transistors. In this case, the common pulse voltage is preferably supplied from the source of the output transistor of the next stage.

According to this structure, two discharge transistors are provided.
The present invention can be applied to a small-scale circuit configuration in which the bootstrap capacitor can be discharged by adding only one and there is no external input pulse.

Further, the signal transmission circuit according to the present invention preferably comprises a malfunction preventing transistor whose drain is connected to the gates of the output transistors in the third and subsequent stages.

According to this structure, malfunction can be prevented even when the threshold voltage of the output transistor is low, and the threshold voltage range can be widened.

Further, in the signal transmission circuit according to the present invention, in each of the third and subsequent stages, the malfunction preventing transistor has a drain connected to the gate of the output transistor,
It is preferable to provide a malfunction prevention transistor whose gate is connected to the source of the output transistor of the previous stage.

According to this structure, the source of the output transistor in the previous stage is connected to the gate of the malfunction preventing transistor, which is suitable for a small-scale circuit structure without other external input pulses. The invention can be applied.

Further, it is preferable that the conductance of the charging transistor is smaller than that of the malfunction preventing transistor.

According to this structure, the plus terminal side of the bootstrap capacitor can be brought closer to 0 V, and the malfunction can be more surely prevented.

Alternatively, in the signal transmission circuit according to the present invention, the charging transistor of the next stage is enabled and the charging transistor of the next stage is disabled while the pulse voltage is being output to the source of the output transistor of a certain stage. It is preferred that a power supply voltage pulse such as For example, when the charging transistor is composed of an NMOS, a “High” level voltage is supplied to the drain of the charging transistor of the next stage as a power supply voltage pulse, and “Lo” is supplied.
The w "level voltage is supplied to the drain of the next-stage charging transistor. When the charging transistor is composed of a PMOS, a “Low” level voltage is supplied to the drain of the charging transistor of the next stage as a power supply voltage pulse, and “Hi” is supplied.
The gh "level voltage is supplied to the drain of the next-stage charging transistor.

According to this structure, the malfunction preventing transistor can be omitted, and the circuit scale can be reduced.

In the signal transmission circuit according to the present invention, the voltage amplitude of the start pulse supplied to the gate of the first-stage charging transistor is preferably larger than the voltage amplitude of the drive pulse.

According to this structure, it is possible to prevent the voltage drop due to the charging transistor in the first stage and charge the bootstrap capacitor in the first stage to the power supply voltage VDD.

In the signal transmission circuit according to the present invention, when all the transistors are NMOS transistors, the first
And at least one of the source of the second discharge transistor and the source of the malfunction prevention transistor,
Ground potential is supplied.

Alternatively, in the signal transmission circuit according to the present invention, when all the transistors are NMOS transistors, the sources of the first and second discharge transistors and the source of the malfunction prevention transistor are higher than the threshold voltage of the output transistor. Low voltage is supplied.

In the signal transmission circuit according to the present invention, when all the transistors are PMOS transistors, the first
And at least one of the source of the second discharge transistor and the source of the malfunction prevention transistor,
Power supply voltage is supplied.

Alternatively, in the signal transmission circuit according to the present invention, when all the transistors are PMOS transistors, the sources of the first and second discharge transistors and the sources of the malfunction prevention transistors are higher than the threshold voltage of the output transistor. High voltage is supplied.

In order to achieve the above-mentioned object, a solid-state image pickup device according to the present invention comprises a multi-stage circuit, and a solid-state image pickup device having a signal transmission circuit for sequentially outputting a scanning pulse voltage according to a drive pulse from each stage circuit. In the imaging device, each stage circuit of the signal transmission circuit includes an output transistor that outputs a driving pulse as a scan pulse voltage to a source, a bootstrap capacitor connected between the gate and the source of the output transistor, and a boot circuit. To charge the strap capacity,
The drain is connected to the power supply or ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the gate is connected to the gate of the output transistor in the previous stage in the second and subsequent stages. And a charging transistor.

In order to achieve the above object, a camera according to the present invention is equipped with the solid-state image pickup device according to the present invention.

In order to achieve the above object, the liquid crystal display device according to the present invention is a liquid crystal device having a signal transmission circuit which is composed of a multi-stage circuit and sequentially outputs a scanning pulse voltage according to a drive pulse from each stage circuit. In the display device, each stage circuit of the signal transmission circuit includes an output transistor that outputs a drive pulse as a scan pulse voltage to a source, a bootstrap capacitor connected between the gate and the source of the output transistor, and a boot transistor. To charge the strap capacity,
The drain is connected to the power supply or ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the gate is connected to the gate of the output transistor in the previous stage in the second and subsequent stages. And a charging transistor.

According to the above structure, a stable operation can be guaranteed even when the voltage of the circuit power supply is lowered, and the solid-state image pickup device, which is particularly applied to a portable device which requires low power consumption, The effect can be exhibited in a camera equipped with it and a liquid crystal display device.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration example of a signal transmission circuit according to the first embodiment of the present invention. The present embodiment is different from the conventional example shown in FIG. 5 in that the gate of the output transistor in the previous stage is connected to the gate of the capacitance charging transistor for bootstrap in the next stage. Other configurations are the same as those of the conventional example of FIG. 5, and are denoted by the same reference numerals in FIG.

In FIG. 1, when the start pulse VST becomes the logic "High" level, the bootstrap capacitor charging transistor T11 in the first stage is turned on, and the bootstrap capacitor C1 is charged to the power supply voltage VDD.
When the charging voltage of the bootstrap capacitor C1 exceeds the threshold voltage level of the output transistor T12, the first stage output transistor T12 is turned on.

After that, when the drive pulse V1 of the logic "High" level is input to the drain of the output transistor T12, the voltage of the drive pulse V1 and the potential difference across the bootstrap capacitor C1 are added to the gate of the output transistor T12. When the gate potential of the output transistor T12 rises above the potential of the drive pulse V1, the drive pulse V1 is used as the output pulse OUT1 from the output node N12 in the first stage.

Here, the advantage of the signal transmission circuit according to the present embodiment is that the voltage of the node N11 connected to the positive terminal of the bootstrap capacitance C1 is the gate of the bootstrap capacitance charging transistor T21 of the second stage. Therefore, a high voltage can be applied to the gate of the transistor T21. As a result, the second-stage bootstrap capacitance charging transistor T21 is
Even if the enhancement type NMOS is used, the bootstrap capacitance C21 can be reliably charged to the power supply voltage VDD and the output transistor T22 can be turned on.

After that, when the drive pulse V2 of the logic "High" level is input to the drain of the output transistor T22, the gate of the output transistor T22 is added with the potential of the drive pulse V2 and the potential difference between both ends of the bootstrap capacitor C2. When the gate potential of the output transistor T22 rises above the potential of the drive pulse V2, the drive pulse V2 is applied to the output node N22 of the second stage.
Is used as the output pulse OUT2.

At the same time, the bootstrap capacitance C2
The high voltage of the node N21 connected to the plus side terminal of is applied to the gate of the bootstrap capacitance charging transistor T31 of the third stage, the transistor T31 is turned on, and the bootstrap capacitance C3 is supplied to the power supply voltage VDD.
Is reliably charged and the output transistor T32 is turned on.

By repeating such an operation, the signal transmission circuit further sequentially outputs the output pulses OUT3 and OUT4.

In this way, in all the signal transmission stages, the terminal voltage on the positive side of the bootstrap capacitor is
Since it is added to the gate of the bootstrap capacitance charging transistor of the next stage, the bootstrap capacitance of the next stage can be reliably charged to the power supply voltage VDD, and a signal transmission circuit that can generate a low-voltage output pulse without voltage drop is provided. realizable.

As a means for discharging the voltage charged in the bootstrap capacitor, in order to reduce the number of transistors and power supply in the circuit, in the case of the bootstrap capacitor C1, the drain of the discharge transistor T13 is connected to the bootstrap capacitor C1. Of the discharge transistor T14 connected to the positive terminal of the bootstrap capacitor C1.
Of the second output transistor T2 to the gates of the discharge transistors T13 and T14.
The output node N22 which is connected to the source of No. 2 is connected.
As a result, the drive pulse V is applied to the output node N22 of the second stage.
When 2 is output, the bootstrap capacitance C1 is discharged.

With this structure, the bootstrap capacitor can be discharged by adding two discharge transistors, and the signal transmission circuit of this embodiment can be realized even with a small-scale circuit structure having no other external input pulse. can do.

As shown in FIG. 2, the negative side discharge of the bootstrap capacitor may be performed using the drive pulse V1 or V2 as in the conventional case.

FIG. 3 is a timing chart showing the pulse voltage of each part in the signal transmission circuit of FIG. 1 using only NMOS. This circuit is a 3V system circuit, and the voltage amplitudes of the drive pulses V1 and V2 and the power supply voltage VDD are 3V.
The case of V is shown. However, the voltage amplitude of the start pulse VST is 5V. Here, the voltage amplitude of the start pulse VST is set to 5 V only in the case of the bootstrap capacitance charging transistor T11 in the first stage to which the start pulse VST is input, since the high voltage from the previous stage cannot be supplied, only the start pulse VST Drive pulse V1, V
This is because by driving the transistor T11 with 5V which is higher than 3V which is the voltage amplitude of 2, the voltage drop due to the transistor T11 is prevented and the bootstrap capacitance C1 can be charged to 3V which is the power supply voltage VDD.

In FIG. 3, even if the voltage of the start pulse VST rises to 5V at time t0 and there is the threshold voltage Vt of the bootstrap capacitance charging transistor T11 which is an enhancement type NMOS,
Bootstrap capacitance C via transistor T11
1 is charged to 3V which is the power supply voltage VDD, and the output transistor T12 is turned on.

Next, at time t1, drive pulse V1
Rises to 3V and is input to the drain of the output transistor T12, a high voltage HB1 voltage obtained by adding the voltage 3V of the drive pulse V1 and the potential difference 3V across the bootstrap capacitor C1 is applied to the gate of the output transistor T12. Therefore, the drive pulse V1 having an amplitude of 3V is surely output from the output node N12 as the output pulse OUT1.

At the same time, the bootstrap capacitance C1
High voltage H of node N11 connected to the positive terminal of
B1 is input to the gate of the bootstrap capacitance charging transistor T21 of the second stage, the transistor T21 is turned on, and the bootstrap capacitance C2 is reliably charged to the power supply voltage VDD of 3V.

Similarly, at times t2, t3, and t4, the operation at time t1 is repeated.

As described above, according to this embodiment, the gate voltage of the bootstrap capacitance charging transistor of the next stage is always applied with the positive terminal voltage of the bootstrap capacitance of the previous stage, so that the boot of the next stage is booted. Since the strap capacitance can be reliably charged to the power supply voltage of 3V, it is possible to realize a signal transmission circuit that can generate a low-voltage output pulse of 3V without a voltage drop.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
3 is a circuit diagram showing a configuration example of a signal transmission circuit according to the embodiment of FIG. The second embodiment is different from the first embodiment in that malfunction preventing transistors (T35, T45) are added to the plus side terminal of the bootstrap capacitor. Hereinafter, only this difference will be described.

The bootstrap capacitance C2 of the second stage is 3
When the threshold voltage of the bootstrap capacitance charging transistor T31, which is an enhancement type NMOS, is low when charged to V, the node N21 (3V) connected to the positive side terminal of the bootstrap capacitance C2 is the gate. There is a possibility that the bootstrap capacitance charging transistor T31 connected to is turned on and the bootstrap capacitance C3 in the third stage is charged to a low voltage of 3 V or less. In this state, the drive pulse V1 is logically "High".
In the case of 3V which is the "h" level, the output node N12 of the first stage
While the drive pulse V1 is being output to the second stage, the drive pulse V1 may be simultaneously output to the output node N32 of the third stage.

Therefore, as shown in FIG. 4, the plus terminal side of the bootstrap capacitor C3 is brought closer to the ground potential so that the output transistor T32 of the third stage is turned off so that the plus terminal side of the bootstrap capacitor C3 is turned off. A malfunction preventing transistor T35 was connected between the ground potential and the ground potential. That is, the drain of the malfunction prevention transistor T35 is connected to the plus side of the bootstrap capacitance C3, the source is connected to the ground potential, and the gate is connected to the output node N12 of the first stage, and the drive pulse V1 is output to the output node N12 of the first stage. Occasionally, the malfunction prevention transistor is turned on to bring the node N31 near 0 V and the output node N32 of the third stage.
The drive pulse V1 is prevented from being output.

At this time, by making the conductance of the bootstrap capacitance charging transistor T31 smaller than the conductance of the malfunction prevention transistor T35, the plus terminal side of the bootstrap capacitance C3 can be brought closer to 0 V, and malfunction occurs. It can be prevented more reliably.

Similarly, the bootstrap capacitance C in the subsequent stage
The drain and the source of the malfunction prevention transistor T45 are respectively connected between the positive terminal side of 4 and the ground potential, and the output node N22 of the previous stage is connected to the gate to prevent malfunction in all stages. Can be prevented.

As described above, according to this embodiment, by providing the malfunction prevention transistor, malfunction can be prevented even when the threshold voltage of the output transistor is low, and the range of the threshold voltage can be widened.

Further, since the source of the output transistor in the previous stage is connected to the gate of the malfunction preventing transistor, the present embodiment is realized even in the case of a small-scale circuit configuration without other external input pulses. The signal transmission circuit can be realized.

In the first and second embodiments, the sources of the discharge transistor and the malfunction prevention transistor are set to the ground potential (0V), but the source voltage is smaller than the threshold voltage of the output transistor. If so, the same effect can be obtained even if it is not 0V.

Further, in the first and second embodiments, since the DC voltage is applied as the power supply voltage VDD to the drain of the bootstrap capacitance charging transistor,
Although a malfunction may occur and it is necessary to incorporate a malfunction prevention transistor, the malfunction can be prevented by applying a pulse voltage as the power supply voltage VDD to the drain of the bootstrap capacitance charging transistor. That is, while the output voltage is being generated at the source of the output transistor, the drain of the bootstrap capacitance charging transistor of the next stage is set to “High” level, and the drain of the bootstrap capacitance charging transistor of the next stage is set to “Low” level. By doing so, the malfunction prevention transistor can be omitted.

In the first and second embodiments, N
Although the case of MOS transistors has been illustrated and described, the case where all are PMOS transistors
Similar effects can be obtained.

[0069]

As described above, according to the present invention,
The bootstrap capacitor in the next stage can be charged to the power supply voltage VDD, and a drop in the charging voltage to the bootstrap capacitor can be prevented. Therefore, as the number of transmission stages increases, the output pulse voltage gradually decreases,
It is possible to prevent the output pulse from being stopped after several steps. As a result, it is possible to realize a signal transmission circuit capable of stable low voltage driving.

In addition, the signal transmission circuit uses the signal transmission circuit as a shift register while meeting the demand for realizing low voltage driving of the liquid crystal display and the MOS type image pickup device.
It realizes low voltage and is extremely useful industrially.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a signal transmission circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing another configuration example of the signal transmission circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing pulse voltages of respective parts in the signal transmission circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a signal transmission circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a conventional signal transmission circuit.

FIG. 6 is a timing chart showing pulse voltages of various parts in a conventional signal transmission circuit.

[Explanation of symbols]

C1, C2, C3, C4 Bootstrap capacitance OUT1, OUT2, OUT3, OUT4 Output pulse (scan pulse) T11, T21, T31, T41 Bootstrap capacitance charging transistor (charging transistor) T12, T22, T32, T42 Output transistor T13, T23, T33, T43 Discharge transistor (first discharge transistor) T14, T24, T34, T44 Discharge transistor (second discharge transistor) T35, T45 Malfunction prevention transistor V1, V2 Drive pulse VDD Power supply voltage VST Start pulse

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/36 5J055 3/36 H04N 5/335 Z 5J056 H03K 17/687 5/66 102B H04N 5 / 335 H03K 19/094 B 5/66 102 17/687 G F Term (reference) 2H093 NC22 ND38 ND39 5C006 BC03 BC11 BF03 BF34 BF37 FA46 FA47 5C024 BX01 HX02 5C058 AA06 BA01 5C080 AA10 DD09 DD26 DD30J22X22 DX0 JJ03 JJ04 JJ04 JJ04 EY10 EY21 EZ18 FX05 FX12 FX27 GX01 5J056 AA00 BB17 BB18 CC18 CC29 DD28 DD51 FF08 GG10

Claims (19)

[Claims] 1. A signal transmission circuit comprising a multi-stage circuit, wherein each stage circuit sequentially outputs a pulse voltage according to a drive pulse, wherein each stage circuit uses the drive pulse as the pulse voltage as a source. An output transistor for outputting to, a bootstrap capacitance connected between the gate and the source of the output transistor, and a drain connected to a power supply or a ground line to charge the bootstrap capacitance, and the source is A charging transistor connected to the gate of the output transistor, the start pulse being supplied to the gate in the case of the first stage, and the gate being connected to the gate of the output transistor in the stage in the second and subsequent stages. Signal transmission circuit. 2. The signal transmission circuit includes: a first discharge transistor having a drain connected to one end of the bootstrap capacitor, and a second discharge transistor having a drain connected to the other end of the bootstrap capacitor. 2. The signal transmission circuit according to claim 1, further comprising: a common pulse voltage applied to the gates of the first and second discharge transistors. 3. The signal transmission circuit according to claim 2, wherein the common pulse voltage is supplied from the source of the output transistor of the next stage. 4. The signal transmission circuit according to claim 1, further comprising a malfunction preventing transistor having a drain connected to a gate of the output transistor in the third and subsequent stages. Signal transmission circuit. 5. The signal transmission circuit according to claim 3, wherein, in each of the third and subsequent stages, the drain is connected to the gate of the output transistor and the gate is connected to the source of the output transistor in the previous stage. The signal transmission circuit according to any one of claims 1 to 3, further comprising a transistor. 6. A power supply voltage that enables the charging transistor of the next stage to operate and disables the charging transistor of the next stage while a pulse voltage is being output to the source of the output transistor of a certain stage. 4. The signal transmission circuit according to claim 1, wherein the pulse is supplied to the drain. 7. The signal transmission circuit according to claim 4, wherein a conductance of the charging transistor is smaller than a conductance of the malfunction prevention transistor. 8. The voltage amplitude of the start pulse supplied to the gate of the charging transistor in the first stage is larger than the voltage amplitude of the drive pulse, according to any one of claims 1 to 7. Signal transmission circuit. 9. The signal transmission circuit according to claim 2, wherein the transistors are all NMOS transistors, and the ground potential is supplied to the sources of the first and second discharge transistors. 10. The transistor according to claim 2, wherein the transistors are all NMOS transistors, and the sources of the first and second discharge transistors are supplied with a voltage lower than a threshold voltage of the output transistor. Alternatively, the signal transmission circuit according to item 3. 11. The signal transmission circuit according to claim 4, wherein all the transistors are NMOS transistors, and a ground potential is supplied to a source of the malfunction prevention transistor. 12. The transistor according to claim 4, wherein the transistors are all NMOS transistors, and a voltage lower than a threshold voltage of the output transistor is supplied to a source of the malfunction prevention transistor. Signal transmission circuit. 13. The signal transmission circuit according to claim 2, wherein all the transistors are PMOS transistors, and a power supply voltage is supplied to the sources of the first and second discharge transistors. 14. The transistors are all PMOS transistors, and the sources of the first and second discharge transistors are supplied with a voltage higher than a threshold voltage of the output transistor. Alternatively, the signal transmission circuit according to item 3. 15. The signal transmission circuit according to claim 4, wherein all the transistors are PMOS transistors, and a power supply voltage is supplied to a source of the malfunction prevention transistor. 16. The transistor according to claim 4, wherein the transistors are all PMOS transistors, and a voltage higher than a threshold voltage of the output transistor is supplied to a source of the malfunction prevention transistor. Signal transmission circuit. 17. A solid-state imaging device comprising a signal transmission circuit configured by a plurality of stage circuits, in which scanning pulse voltages according to drive pulses are sequentially output from each stage circuit, wherein each stage circuit of the signal transmission circuit is An output transistor for outputting the drive pulse to the source as the scan pulse voltage, a bootstrap capacitor connected between the gate and the source of the output transistor, and a drain for charging the bootstrap capacitor. Is connected to the power supply or ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the gate is connected to the gate of the output transistor in the previous stage in the second and subsequent stages. A solid-state image pickup device, comprising: 18. A camera equipped with the solid-state imaging device according to claim 17. 19. A liquid crystal display device comprising a signal transmission circuit configured by a plurality of stage circuits, in which scanning pulse voltages according to drive pulses are sequentially output from each stage circuit, wherein each stage circuit of the signal transmission circuit is An output transistor for outputting the drive pulse to the source as the scan pulse voltage, a bootstrap capacitor connected between the gate and the source of the output transistor, and a drain for charging the bootstrap capacitor. Is connected to the power supply or ground line, the source is connected to the gate of the output transistor, the start pulse is supplied to the gate in the first stage, and the gate is connected to the gate of the output transistor in the previous stage in the second and subsequent stages. And a charging transistor.