JP2003101394A5

JP2003101394A5 -

Info

Publication number: JP2003101394A5
Application number: JP2002152745A
Authority: JP
Filing date: 2002-05-27
Publication date: 2005-10-27

Claims

A first transistor having a first signal input to a gate and a second signal input to one of a source and a drain;
A second transistor having a gate electrically connected to the other of the source and the drain of the first transistor and a third signal input to one of the source and the drain;
The third signal in which the first signal is input to the gate, the predetermined potential is input to one of the source and the drain, and the other of the source and the drain is electrically connected to the other of the source and the drain of the second transistor. Transistors
A semiconductor device comprising:

A first transistor having a gate electrically connected to the first wiring and one of a source and a drain electrically connected to the second wiring;
The gate is electrically connected to the other of the source and the drain of the first transistor, one of the source and the drain is electrically connected to the third wiring, and the other of the source and the drain is electrically connected to the fourth wiring. A second transistor connected to
A gate is electrically connected to the first wiring, one of a source or a drain is electrically connected to the fifth wiring, and the other of the source or the drain is electrically connected to the fourth wiring. 3 transistors,
A semiconductor device comprising:

Have a first transistor to the third transistor,
A gate of the first transistor is electrically connected to a first wiring ;
One of a source and a drain of the first transistor is electrically connected to a second wiring ;
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
One of a source and a drain of the second transistor is electrically connected to a third wiring ;
The other of the source and the drain of the second transistor is electrically connected to a fourth wiring ;
A gate of the third transistor is electrically connected to the first wiring ;
One of a source and a drain of the third transistor is electrically connected to a fifth wiring ;
The other of the source and the drain of the third transistor is electrically connected to the fourth wiring ;
A first clock signal is supplied to the first wiring;
A second clock signal is supplied to the third wiring;
A predetermined potential is applied to the fifth wiring,
A pulse is supplied to the second wiring,
A semiconductor device, wherein a pulse is supplied to the fourth wiring.

4. The capacitor unit according to claim 1, wherein a capacitor is provided between the gate and the source or the drain of the second transistor or between the gate and the other of the source or the drain of the second transistor. A semiconductor device comprising:

5. The semiconductor device according to claim 1, wherein the first to third transistors are all of the same conductivity type.

In claim 5 ,
The semiconductor device is an N-channel semiconductor device .

In claim 5 ,
The semiconductor device is a P-channel semiconductor device .

Having a first pulse output circuit and a second pulse output circuit comprising an input terminal and an output terminal;
Each of the first pulse output circuit and the second pulse output circuit includes a first transistor to a third transistor,
A gate of the first transistor of the first pulse output circuit is electrically connected to a first wiring;
One of a source and a drain of the first transistor of the first pulse output circuit is electrically connected to an input terminal of the first pulse output circuit;
The other of the source and the drain of the first transistor of the first pulse output circuit is electrically connected to the gate of the second transistor of the first pulse output circuit;
One of a source and a drain of the second transistor of the first pulse output circuit is electrically connected to a third wiring;
The other of the source and the drain of the second transistor of the first pulse output circuit is electrically connected to the output terminal of the first pulse output circuit;
A gate of the third transistor of the first pulse output circuit is electrically connected to the first wiring;
One of a source and a drain of the third transistor of the first pulse output circuit is electrically connected to a fifth wiring;
The other of the source and the drain of the third transistor of the first pulse output circuit is electrically connected to the output terminal of the first pulse output circuit;
A gate of the first transistor of the second pulse output circuit is electrically connected to a second wiring;
One of the source and the drain of the first transistor of the second pulse output circuit is electrically connected to the input terminal of the second pulse output circuit;
The other of the source and the drain of the first transistor of the second pulse output circuit is electrically connected to the gate of the second transistor of the second pulse output circuit;
One of a source and a drain of the second transistor of the second pulse output circuit is electrically connected to a fourth wiring;
The other of the source and the drain of the second transistor of the second pulse output circuit is electrically connected to the output terminal of the second pulse output circuit;
A gate of the third transistor of the second pulse output circuit is electrically connected to the second wiring;
One of a source and a drain of the third transistor of the second pulse output circuit is electrically connected to the fifth wiring;
The other of the source and the drain of the third transistor of the second pulse output circuit is electrically connected to the output terminal of the second pulse output circuit;
The pulse output circuit, wherein the output terminal of the first pulse output circuit and the input terminal of the second pulse output circuit are electrically connected.

The first clock signal is supplied to the first wiring according to claim 8,
A second clock signal is supplied to the second wiring;
A third clock signal is supplied to the third wiring;
A fourth clock signal is supplied to the fourth wiring;
A pulse output circuit, wherein a predetermined potential is applied to the fifth wiring.

10. The capacitor according to claim 8, further comprising a capacitor between the gate of the second transistor and one of the source and the drain, or between the gate of the second transistor and the other of the source and the drain. Pulse output circuit.

11. The pulse output circuit according to claim 8, wherein the first to third transistors have the same conductivity type.

In claim 11,
The pulse output circuit according to claim 1, wherein the conductivity type is an N channel type.

In claim 11,
The pulse output circuit, wherein the conductivity type is a P-channel type.

A first transistor to a third transistor;
A gate of the first transistor is electrically connected to a first wiring;
One of a source and a drain of the first transistor is electrically connected to a second wiring;
The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor;
One of a source and a drain of the second transistor is electrically connected to a third wiring;
The other of the source and the drain of the second transistor is electrically connected to a fourth wiring;
A gate of the third transistor is electrically connected to the first wiring;
One of a source and a drain of the third transistor is electrically connected to a fifth wiring;
The other of the source and the drain of the third transistor has a plurality of stages of pulse outputs electrically connected to the fourth wiring;
A first clock signal line to a fourth clock signal line, and a start pulse input line;
In the pulse output of the 4n-3rd stage (n is a natural number, 1 ≦ n),
The first wiring is electrically connected to the first clock signal line;
The second wiring is electrically connected to the start pulse input line when n = 1, and when n ≠ 1, the fourth wiring of the pulse output circuit at the 4 (n−1) th stage. Electrically connected with
The third wiring is electrically connected to the third clock signal line;
In the pulse output circuit at the 4n-2 stage,
The first wiring is electrically connected to the second clock signal line;
The second wiring is the fourth wiring electrically connected to the pulse output circuit of the 4n-3-stage,
The third wiring is electrically connected to the fourth clock signal line;
In the pulse output circuit at the 4n-1 stage,
The first wiring is electrically connected to the third clock signal line;
The second wiring is the fourth wiring electrically connected to the pulse output circuit of the 4n-2 stage,
The third wiring is electrically connected to the first clock signal line;
In the 4n stage pulse output circuit,
The first wiring is electrically connected to the fourth clock signal line;
The second wiring is the fourth wiring electrically connected to the pulse output circuit of the 4n-1 stage,
The third wiring is electrically connected to the second clock signal line;
A shift register which sequentially outputs sampling pulses in accordance with the first to fourth clock signals and a start pulse.

15. The shift according to claim 14, further comprising capacitance means between the gate of the second transistor and one of the source and the drain or between the gate of the second transistor and the other of the source and the drain. register.

16. The shift register according to claim 14, wherein the first to third transistors have the same conductivity type.

In claim 16,
The conductivity type is an N channel type shift register.

In claim 16,
The conductivity type is a P-channel type shift register.

19. A gate signal line driver circuit using the semiconductor device, the pulse output circuit, or the shift register according to claim 1.

19. A source signal line driver circuit using the semiconductor device according to claim 1, a pulse output circuit, or a shift register .

21. A display device using the gate signal line drive circuit or the source signal line drive circuit according to claim 19 or 20.

An electronic apparatus using the display device according to claim 21 .