JP2003101090A - Manufacturing method for high integrated superconducting circuit - Google Patents
Manufacturing method for high integrated superconducting circuitInfo
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- JP2003101090A JP2003101090A JP2001286597A JP2001286597A JP2003101090A JP 2003101090 A JP2003101090 A JP 2003101090A JP 2001286597 A JP2001286597 A JP 2001286597A JP 2001286597 A JP2001286597 A JP 2001286597A JP 2003101090 A JP2003101090 A JP 2003101090A
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- superconducting electrode
- interlayer insulating
- insulating film
- electrode
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、通信、コンピュー
タ、計測などの分野で用いられつつある超伝導回路を高
集積化するのに好適な高集積超伝導回路の製造方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated superconducting circuit manufacturing method suitable for highly integrating a superconducting circuit which is being used in fields such as communication, computers, and measurement.
【０００２】[0002]
【従来の技術】現在、通信用ルーター、サーバー、ＡＤ
変換器、磁束計（ＳＱＵＩＤ）、サンプラーなどに超伝
導回路が用いられつつある。2. Description of the Related Art Currently, communication routers, servers, AD
Superconducting circuits are being used in converters, magnetometers (SQUIDs), samplers, and the like.
【０００３】この超伝導回路を構成するのに酸化物超伝
導接合が多用されているが、その超伝導接合の種類の一
つにランプエッジ接合が知られている。Oxide superconducting junctions are often used to form this superconducting circuit, and ramp edge junction is known as one of the types of the superconducting junctions.
【０００４】図１０乃至図１２は従来の酸化物超伝導回
路を製造する工程を説明する為の工程要所に於ける酸化
物超伝導回路の要部切断側面図及び要部切断平面図（図
１２のみ）であり、以下、これ等の図を参照しつつ説明
する。10 to 12 are side views and a plan view of a main part of an oxide superconducting circuit at a process step for explaining a conventional process for manufacturing an oxide superconducting circuit (FIG. 12 only), and will be described below with reference to these figures.
【０００５】図１０（Ａ）参照 （１）支持基板１に下部超伝導電極２を形成する。See FIG. 10 (A). (1) The lower superconducting electrode 2 is formed on the supporting substrate 1.
【０００６】図１０（Ｂ）参照 （２）下部超伝導電極２上に層間絶縁膜３を形成する。See FIG. 10B. (2) The interlayer insulating film 3 is formed on the lower superconducting electrode 2.
【０００７】図１０（Ｃ）参照
（３）レジスト膜４をマスクとして層間絶縁膜３の斜め
回転ミリングを行って層間絶縁膜３を塁状にする。Referring to FIG. 10C, (3) the interlayer insulating film 3 is obliquely milled by using the resist film 4 as a mask to form the interlayer insulating film 3 in a base shape.
【０００８】図１１（Ａ）参照
（４）レジスト膜４を除去してから層間絶縁膜３及び下
部超伝導電極２の斜め回転ミリングを行って下部超伝導
電極２も塁状にする。Referring to FIG. 11 (A) (4) After removing the resist film 4, the interlayer insulating film 3 and the lower superconducting electrode 2 are obliquely milled to make the lower superconducting electrode 2 in a base shape.
【０００９】図１１（Ｂ）参照
（５）全面に上部超伝導電極５を形成する。このように
すると、上部超伝導電極５は台形状をなす下部超伝導電
極２の斜面で接触して超伝導接合６を生成し、ここにラ
ンプ・エッジ接合が実現される。Referring to FIG. 11B, (5) the upper superconducting electrode 5 is formed on the entire surface. In this way, the upper superconducting electrode 5 comes into contact with the trapezoidal lower superconducting electrode 2 on the inclined surface to form the superconducting junction 6, where the ramp-edge junction is realized.
【００１０】図１１（Ｃ）及び図１２参照
（６）上部超伝導電極５のパターニングを行う。この場
合の上部超伝導電極５のパターンは図１２で明らかであ
るが、ストライプをなしている。11C and 12 (6) The upper superconducting electrode 5 is patterned. Although the pattern of the upper superconducting electrode 5 in this case is clear in FIG. 12, it has a stripe shape.
【００１１】前記したように、超伝導接合６が二つ以上
連続するような構造の場合、図示されているように、下
部超伝導電極２は塁状形にして用いることが多く、ま
た、超伝導接合６の分離は上部超伝導電極５のパターニ
ングと同時に実施している。As described above, in the case of a structure in which two or more superconducting junctions 6 are continuous, the lower superconducting electrode 2 is often used in the form of a base as shown in the drawing. The separation of the conductive junction 6 is carried out at the same time as the patterning of the upper superconducting electrode 5.
【００１２】上部超伝導電極５をパターニングする場
合、フォト・リソグラフィ技術を適用することで実施し
ているので、光露光に依るレジスト層のパターニングを
行う場合のマスク合わせマージンを考慮し、上部超伝導
電極５の端部は超伝導接合６を遙に越えて層間絶縁膜３
の頂面上にまで延在した状態にパターニングされる。Since patterning of the upper superconducting electrode 5 is carried out by applying a photolithography technique, the upper superconducting layer is considered in consideration of the mask alignment margin when patterning the resist layer by light exposure. The end of the electrode 5 far exceeds the superconducting junction 6 and the interlayer insulating film 3
Is patterned so as to extend to the top surface of the.
【００１３】その結果、図１１（Ｃ）と図１２から明ら
かなように、上部超伝導電極５の端部がマスク合わせマ
ージンの為に延在しなければならない部分が２〔μ
ｍ〕、従って、左右両端で４〔μｍ〕が必要であって、
その分、塁状の層間絶縁膜３及び下部超伝導電極２は大
きくなり、同じく、左右両端で８〔μｍ〕になってい
る。As a result, as is apparent from FIGS. 11C and 12, the end portion of the upper superconducting electrode 5 has to extend for a mask alignment margin of 2 [μ].
m], therefore, 4 [μm] is required at the left and right ends,
Correspondingly, the base-shaped interlayer insulating film 3 and the lower superconducting electrode 2 are increased in size, and are also 8 [μm] at both left and right ends.
【００１４】従って、ランプエッジ接合構造をもつ酸化
物超伝導回路では集積度を向上させることが困難であ
り、また、回路全体のインダクタンス低減も困難であ
り、更にまた、上部超伝導電極５の前記延在部分のばら
つきの為、隣合う接合のインダクタンスにもばらつきが
生じ、回路動作を困難にする原因になっている。Therefore, it is difficult to improve the degree of integration in the oxide superconducting circuit having the ramp edge junction structure, and it is also difficult to reduce the inductance of the entire circuit. Due to the variation of the extending portion, the inductance of the adjacent junction also varies, which makes the circuit operation difficult.
【００１５】[0015]
【発明が解決しようとする課題】本発明では、上部超伝
導電極の位置合わせずれとは関係なく、均一なインダク
タンス配分で超伝導接合を分離することを極めて簡単な
手段で実現できるようにする。SUMMARY OF THE INVENTION In the present invention, it is possible to realize separation of a superconducting junction with a uniform inductance distribution by a very simple means regardless of misalignment of the upper superconducting electrode.
【００１６】[0016]
【課題を解決するための手段】本発明に依る高集積超伝
導回路の製造方法に於いては、上部超伝導電極のパター
ニングは、単にライン状に加工するに止め、超伝導接合
の分離は、その後に実施する研磨に依って行うことが基
本になっている。In the method of manufacturing a highly integrated superconducting circuit according to the present invention, the patterning of the upper superconducting electrode is stopped by simply processing it into a line, and the superconducting junction is separated. It is basically performed by polishing performed thereafter.
【００１７】前記手段を採ることに依り、上部超伝導電
極をパターニングする際のマスク合わせマージンは不要
であり、しかも、均一なインダクタンス配分で超伝導接
合の分離を行うことができるので、下部超伝導電極の塁
状構造を縮小化することが可能となって回路全体の集積
度は向上し、又、インダクタンスの低減が可能となるの
で高速動作性及び実用性に優れた高集積超伝導回路を実
現することができる。By adopting the above means, no mask alignment margin is required when patterning the upper superconducting electrode, and the superconducting junction can be separated with a uniform inductance distribution. It is possible to downsize the base structure of the electrodes and improve the degree of integration of the entire circuit. Also, because it is possible to reduce the inductance, a highly integrated superconducting circuit with excellent high-speed operability and practicality is realized. can do.
【００１８】[0018]
【発明の実施の形態】図１乃至図４は本発明の原理的な
実施の形態を説明する為の工程要所に於ける超伝導回路
を表す要部切断側面図及び要部切断平面図（図３（Ｂ）
と図４（Ｂ）のみ）である。以下、これ等の図を参照し
つつ説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 4 are side views and a plan view of a main section showing a superconducting circuit in a process step for explaining a principle embodiment of the present invention ( Figure 3 (B)
And FIG. 4B only). Hereinafter, description will be given with reference to these drawings.
【００１９】図１（Ａ）参照 （１）支持基板１に下部超伝導電極２を形成する。See FIG. 1A. (1) The lower superconducting electrode 2 is formed on the supporting substrate 1.
【００２０】図１（Ｂ）参照 （２）下部超伝導電極２上に層間絶縁膜３を形成する。See FIG. 1 (B) (2) The interlayer insulating film 3 is formed on the lower superconducting electrode 2.
【００２１】図１（Ｃ）参照
（３）レジスト膜４をマスクとして層間絶縁膜３の斜め
回転ミリングを行って層間絶縁膜３を塁状にする。Referring to FIG. 1C, (3) the interlayer insulating film 3 is obliquely milled by using the resist film 4 as a mask to form the interlayer insulating film 3 in a base shape.
【００２２】図２（Ａ）参照
（４）レジスト膜４を除去してから層間絶縁膜３及び下
部超伝導電極２の斜め回転ミリングを行って下部超伝導
電極２も塁状にする。Referring to FIG. 2 (A) (4) After removing the resist film 4, the interlayer insulating film 3 and the lower superconducting electrode 2 are obliquely milled to make the lower superconducting electrode 2 in a base shape.
【００２３】図２（Ｂ）参照
（５）全面に上部超伝導電極５を形成する。これに依っ
て、上部超伝導電極５は台形状をなす下部超伝導電極２
の斜面と接触して超伝導接合６を生成し、ここにランプ
・エッジ接合が実現される。Referring to FIG. 2B (5), the upper superconducting electrode 5 is formed on the entire surface. Accordingly, the upper superconducting electrode 5 is trapezoidal in shape.
To form a superconducting junction 6 where the ramp edge junction is realized.
【００２４】図３（Ａ）及び（Ｂ）参照
（６）上部超伝導電極５のパターニングを行う。この場
合の上部超伝導電極５のパターンは、図３（Ｂ）に明ら
かであるが、１本の連続したストライプをなしているの
で、この段階では、超伝導接合６の分離は行われていな
い。3A and 3B (6) The upper superconducting electrode 5 is patterned. The pattern of the upper superconducting electrode 5 in this case is clear in FIG. 3B, but since it forms one continuous stripe, the superconducting junction 6 is not separated at this stage. .
【００２５】図４（Ａ）及び（Ｂ）参照
（７）台形の層間絶縁膜３上に在る上部超伝導電極５の
研磨を行って、その下地になっている層間絶縁膜３の部
分を表出させる。4 (A) and 4 (B) (7) The upper superconducting electrode 5 on the trapezoidal interlayer insulating film 3 is polished to remove the underlying interlayer insulating film 3 portion. Show it up.
【００２６】このようにすることで、超伝導接合６は分
離され、そして、この場合、上部超伝導電極５の延在方
向に沿う層間絶縁膜３の頂面の幅は２〔μｍ〕程度であ
り、また、同方向の下部超伝導電極２に於ける頂面の幅
は２．７〔μｍ〕程度である。By doing so, the superconducting junction 6 is separated, and in this case, the width of the top surface of the interlayer insulating film 3 along the extending direction of the upper superconducting electrode 5 is about 2 [μm]. In addition, the width of the top surface of the lower superconducting electrode 2 in the same direction is about 2.7 [μm].
【００２７】図５乃至図８は本発明に於ける具体的な実
施例１を説明する為の工程要所に於ける超伝導回路を表
す要部切断側面図及び要部平面図（図７（Ｂ）と図８
（Ｂ）のみ）であり、以下、これ等の図を参照しつつ説
明する。FIGS. 5 to 8 are sectional side views and a plan view of a main part showing a superconducting circuit in a process main part for explaining a specific embodiment 1 of the present invention (see FIG. B) and FIG.
(B) only), and will be described below with reference to these drawings.
【００２８】図５（Ａ）及び（Ｂ）参照
（１）レジスト・プロセスとイオン・ミリング法を適用
することに依り、ＬＳＡＴ（ＬａＳｒＡｌＴａＯx ）か
らなる支持基板１１に深さを５００〔ｎｍ〕のグランド
・プレーン形成用凹所を形成する。See FIGS. 5A and 5B. (1) By applying the resist process and the ion milling method, the depth of the support substrate 11 made of LSAT (LaSrAlTaO x ) is 500 nm. Form a recess for forming the ground plane.
【００２９】（２）レーザ・アブレーション法を適用す
ることに依り、グランド・プレーン形成用凹所を含めた
支持基板１１上にグランド・プレーン形成用凹所が充分
に埋まる程度の厚さのＹＢＣＯ（ＹＢａ2 Ｃｕ
3 Ｏ7-x ）からなるグランド・プレーン層１２を形成す
る。(2) By applying the laser ablation method, YBCO (thickness enough to completely fill the recess for forming the ground plane on the supporting substrate 11 including the recess for forming the ground plane) YBa 2 Cu
A ground plane layer 12 of 3 O 7-x ) is formed.
【００３０】（３）レジスト・プロセスを適用すること
に依り、グランド・プレーン形成用凹所を埋めたグラン
ド・プレーン層１２上及び支持基板１１の平坦面に在る
グランド・プレーン層１２上にも僅かに掛かる程度にレ
ジスト膜を形成する。(3) By applying the resist process, also on the ground plane layer 12 that fills the recess for forming the ground plane and on the ground plane layer 12 on the flat surface of the support substrate 11. The resist film is formed so that it is slightly covered.
【００３１】レジスト膜のパターンを上記のようにする
ことで、次の工程でグランド・プレーン層１２をウエッ
ト・エッチングする際、サイドからのエッチングに依る
グランド・プレーン部分への侵食を防止することができ
る。By setting the pattern of the resist film as described above, when the ground plane layer 12 is wet-etched in the next step, it is possible to prevent the ground plane portion from being eroded by the etching from the side. it can.
【００３２】（４）１／１０００に希釈したＨＣｌをエ
ッチャントとするウエット・エッチング法を適用するこ
とに依り、前記レジスト膜をマスクとしてグランド・プ
レーン層１２のエッチングを行う。(4) The ground plane layer 12 is etched using the resist film as a mask by applying a wet etching method using HCl diluted to 1/1000 as an etchant.
【００３３】この工程に依り、支持基板１１の平坦面上
に在るグランド・プレーン層１２は殆ど除去されるので
あるが、グランド・プレーン形成用凹所の縁辺近傍には
前記したレジスト膜パターンの関係で一部が突起状に残
留する。By this step, the ground plane layer 12 on the flat surface of the support substrate 11 is almost removed, but the resist film pattern described above is formed near the edge of the recess for forming the ground plane. Due to the relationship, a part remains as a protrusion.
【００３４】（５）径が０．０３〔μｍ〕以下のアルミ
ナを用いて表面を研磨することで平坦化する。尚、この
研磨に依って前記グランド・プレーン層１２の突起が除
去されてしまうことは云うまでもない。(5) The surface is polished by using alumina having a diameter of 0.03 [μm] or less to flatten the surface. Needless to say, the protrusion of the ground plane layer 12 is removed by this polishing.
【００３５】（６）レーザ・アブレーション法を適用す
ることに依り、厚さ２００〔ｎｍ〕のＬＳＡＴからなる
層間絶縁層１３を形成し、引き続き、厚さ２００〔ｎ
ｍ〕のＹＢＣＯからなる下部超伝導電極１４を形成し、
更に、厚さ４００〔ｎｍ〕のＬＳＡＴからなる層間絶縁
膜１５を形成する。(6) By applying the laser ablation method, the interlayer insulating layer 13 made of LSAT having a thickness of 200 nm is formed, and then the thickness of 200 nm is applied.
m], the lower superconducting electrode 14 made of YBCO is formed,
Further, the interlayer insulating film 15 made of LSAT and having a thickness of 400 nm is formed.
【００３６】図６（Ａ）参照
（７）リソグラフィ技術に於けるレジスト・プロセスを
適用することに依り、層間絶縁膜１５を塁状に加工する
為のレジスト膜１６を形成する。尚、レジストにはＯＭ
Ｒ−８３（商品名 東京応化製）を使用した。Referring to FIG. 6 (A) (7), by applying a resist process in the lithography technique, a resist film 16 for forming the base insulating film 15 into a base is formed. The resist is OM
R-83 (trade name, manufactured by Tokyo Ohka) was used.
【００３７】（８）３０度斜め方向からのＡｒイオンを
用いるイオン・ミリング法を適用することに依り、回転
ミリングを行って層間絶縁膜１５を截頭角錐型の塁状に
加工する。(8) By applying an ion milling method using Ar ions from a 30 ° oblique direction, rotational milling is performed to process the interlayer insulating film 15 into a truncated pyramid-shaped base.
【００３８】図６（Ｂ）参照
（９）レジスト膜１６を除去してから、再び、３０度斜
め方向からのＡｒ及び酸素混合ガスからなるイオンを用
いるイオン・ミリング法を適用することに依り、塁状の
層間絶縁膜１５をマスクに回転ミリングを行って下部超
伝導電極１４を塁状に加工する。Referring to FIG. 6B, (9) by removing the resist film 16 and then again applying an ion milling method using ions of Ar and oxygen mixed gas from an oblique direction of 30 degrees, The lower superconducting electrode 14 is processed into a base shape by performing rotary milling using the base-shaped interlayer insulating film 15 as a mask.
【００３９】この工程を経ることで、下部超伝導電極１
４はランプ構造となって、その表面には、薄い改質バリ
ヤ層が生成される。Through this process, the lower superconducting electrode 1
4 has a lamp structure, and a thin modified barrier layer is formed on the surface thereof.
【００４０】図７（Ａ）参照
（１０）レーザ・アブレーション法を適用することに依
り、厚さ２００〔ｎｍ〕のＹＢＣＯからなる上部超伝導
電極１７を形成する。Referring to FIG. 7A (10), by applying the laser ablation method, the upper superconducting electrode 17 made of YBCO having a thickness of 200 nm is formed.
【００４１】ここで、下部超伝導電極１４並びに上部超
伝導電極１７は、下部超伝導電極１４に於けるランプ構
造表面に於いて、薄い改質バリヤ層を介して接触し、超
伝導接合１８を生成する。Here, the lower superconducting electrode 14 and the upper superconducting electrode 17 are in contact with each other on the surface of the lamp structure of the lower superconducting electrode 14 through the thin modified barrier layer, and the superconducting junction 18 is formed. To generate.
【００４２】図７（Ｂ）参照
（１１）リソグラフィ技術に於けるレジスト・プロセ
ス、及び、Ａｒイオンを用いるイオン・ミリング法を適
用することに依り、ＹＢＣＯからなる上部超伝導電極１
７を幅２〔μｍ〕のライン状にパターニングする。See FIG. 7B. (11) By applying the resist process in the lithography technique and the ion milling method using Ar ions, the upper superconducting electrode 1 made of YBCO is formed.
7 is patterned into a line shape having a width of 2 [μm].
【００４３】図８（Ａ）及び（Ｂ）参照
（１２）研磨法を適用することに依り、塁状の層間絶縁
膜１５上に在るライン状の上部超伝導電極１７のみを除
去し、超伝導接合１８の分離を行う。8 (A) and 8 (B) (12) By applying the polishing method, only the line-shaped upper superconducting electrode 17 on the base-shaped interlayer insulating film 15 is removed, and The conductive junction 18 is separated.
【００４４】このようにして作製した超伝導回路に於い
て、塁状の層間絶縁膜１５頂面の上部超伝導電極１７延
在方向の幅は２〔μｍ〕程度である。In the superconducting circuit thus manufactured, the width of the top surface of the base-shaped interlayer insulating film 15 in the extending direction of the upper superconducting electrode 17 is about 2 [μm].
【００４５】ところで、前記実施例１の工程（１２）に
於いて、ライン状の上部超伝導電極１７を研磨し、超伝
導接合１８の分離を行っているのであるが、その際、超
伝導接合１８がダメージを受け易いことが知られてい
る。By the way, in the step (12) of the first embodiment, the line-shaped upper superconducting electrode 17 is polished and the superconducting junction 18 is separated. It is known that 18 is susceptible to damage.
【００４６】図９は本発明に於ける具体的な実施例２を
説明する為の工程要所に於ける超伝導回路を表す要部切
断側面図であり、以下、図を参照しつつ説明する。尚、
図５乃至図８に於いて用いた記号と同記号は同部分を表
すか或いは同じ意味を持つものとする。FIG. 9 is a cutaway side view of a main part showing a superconducting circuit in a process step for explaining a specific second embodiment of the present invention, which will be described below with reference to the drawings. . still,
The same symbols as those used in FIGS. 5 to 8 represent the same parts or have the same meanings.
【００４７】図９（Ａ）参照
（１）超伝導回路は、実施例１の工程（１）乃至工程
（１１）と全く同じ工程を経て、支持基板１上に塁状の
下部超伝導電極１４及び層間絶縁膜１５、ライン状の上
部超伝導電極１７が形成された状態にある。Referring to FIG. 9A, the superconducting circuit (1) is the same as the steps (1) to (11) of the first embodiment, and the base-shaped lower superconducting electrode 14 is formed on the supporting substrate 1. And the interlayer insulating film 15 and the line-shaped upper superconducting electrode 17 are formed.
【００４８】スピン・コート法を適用することに依り、
レジスト（例えばＯＭＲ−８３：商品名 東京応化製）
を塗布して保護膜１９を形成する。By applying the spin coat method,
Resist (for example, OMR-83: trade name manufactured by Tokyo Ohka)
Is applied to form a protective film 19.
【００４９】図９（Ｂ）参照
（２）実施例１の工程（１２）と同様にして、塁状の層
間絶縁膜１５上に在るライン状の上部超伝導電極１７及
び保護膜１９のみを除去し、超伝導接合１８の分離を行
う。Referring to FIG. 9B, (2) In the same manner as in step (12) of Example 1, only the line-shaped upper superconducting electrode 17 and the protective film 19 on the base-shaped interlayer insulating film 15 are removed. Then, the superconducting junction 18 is separated.
【００５０】（３）この後、レジスト剥離液中に浸漬
し、残っている保護膜１９を除去すれば、実施例１に依
って完成された超伝導回路と同じ構造のものが得られ、
また、その超伝導回路では、超伝導接合１８は研磨に依
るダメージがなく、良好な状態を維持している。(3) After that, by immersing in the resist stripping solution and removing the remaining protective film 19, a structure having the same structure as the superconducting circuit completed according to Example 1 is obtained.
Further, in the superconducting circuit, the superconducting junction 18 is maintained in a good state without being damaged by polishing.
【００５１】前記実施例１及び２では、超伝導電極材料
や層間絶縁膜材料をレーザ・アブレーション法を適用し
て成膜しているが、これは他の成膜法、例えばスパッタ
リング法などに代替することができる。In the first and second embodiments, the superconducting electrode material and the interlayer insulating film material are formed by applying the laser ablation method, but this is replaced by another film forming method such as sputtering method. can do.
【００５２】超伝導電極材料として、ＹＢＣＯの他、例
えばＮｄＢａＣｕＯを用いることができ、また、層間絶
縁膜材料として、ＬＳＡＴの他、例えばＭｇＯやセリア
などを用いることができ、更にまた、実施例２に於ける
保護膜としてレジストの他、保護膜として作用すると共
にＹＢＣＯにダメージを与えることなく除去できるもの
であれば適宜に選択することができる。In addition to YBCO, for example, NdBaCuO can be used as the superconducting electrode material, and as the interlayer insulating film material, for example, MgO or ceria can be used in addition to LSAT. In addition to the resist as the protective film in the above, it can be appropriately selected as long as it acts as a protective film and can be removed without damaging the YBCO.
【００５３】[0053]
【発明の効果】本発明に依る高集積超伝導回路の作製方
法に於いては、支持基板上に酸化物超伝導体からなる下
部超伝導電極を形成し、下部超伝導電極上に層間絶縁膜
を形成し、層間絶縁膜及び下部超伝導電極をランプ・エ
ッジ構造の塁状に加工し、酸化物超伝導体からなる上部
超伝導電極を形成して下部超伝導電極との接触部分に超
伝導接合を生成させ、上部超伝導電極を塁状の下部超伝
導電極及び層間絶縁膜を跨いで延在するライン状に加工
し、塁状層間絶縁膜の頂面に在るライン状の上部超伝導
電極を研磨除去して超伝導接合を分離する。According to the method of manufacturing a highly integrated superconducting circuit according to the present invention, a lower superconducting electrode made of an oxide superconductor is formed on a supporting substrate, and an interlayer insulating film is formed on the lower superconducting electrode. Process, the interlayer insulating film and the lower superconducting electrode are processed into a ramp-shaped base structure, and the upper superconducting electrode made of an oxide superconductor is formed. A junction is formed, and the upper superconducting electrode is processed into a line shape extending over the base-shaped lower superconducting electrode and the interlayer insulating film, and the line-shaped upper superconducting layer on the top surface of the base-shaped interlayer insulating film is processed. The electrodes are polished off to separate the superconducting junction.
【００５４】前記構成を採ることに依り、上部超伝導電
極をパターニングする際のマスク合わせマージンは不要
であり、しかも、均一なインダクタンス配分で超伝導接
合の分離を行うことができるので、下部超伝導電極の塁
状構造を縮小化することが可能となって回路全体の集積
度は向上し、又、インダクタンスの低減が可能となるの
で高速動作性及び実用性に優れた高集積超伝導回路を実
現することができる。By adopting the above-mentioned structure, no mask alignment margin is required when patterning the upper superconducting electrode, and the superconducting junction can be separated with a uniform inductance distribution. It is possible to downsize the base structure of the electrodes and improve the degree of integration of the entire circuit. Also, because it is possible to reduce the inductance, a highly integrated superconducting circuit with excellent high-speed operability and practicality is realized. can do.
【図１】本発明の原理的な実施の形態を説明する為の工
程要所に於ける超伝導回路を表す要部切断側面図であ
る。FIG. 1 is a cutaway side view of a main part showing a superconducting circuit in a process key point for explaining a principle embodiment of the present invention.
【図２】本発明の原理的な実施の形態を説明する為の工
程要所に於ける超伝導回路を表す要部切断側面図であ
る。FIG. 2 is a side sectional view showing an essential part of a superconducting circuit in a process key part for explaining a principle embodiment of the present invention.
【図３】本発明の原理的な実施の形態を説明する為の工
程要所に於ける超伝導回路を表す要部切断説明図であ
る。FIG. 3 is a fragmentary explanatory view showing a superconducting circuit in a process key point for explaining a principle embodiment of the present invention.
【図４】本発明の原理的な実施の形態を説明する為の工
程要所に於ける超伝導回路を表す要部切断説明図であ
る。FIG. 4 is a fragmentary explanatory view showing a superconducting circuit in a process key point for explaining a principle embodiment of the present invention.
【図５】本発明に於ける具体的な実施例１を説明する為
の工程要所に於ける超伝導回路を表す要部切断側面図で
ある。FIG. 5 is a cutaway side view of a main part showing a superconducting circuit in a process key point for explaining a specific example 1 of the present invention.
【図６】本発明に於ける具体的な実施例１を説明する為
の工程要所に於ける超伝導回路を表す要部切断側面図で
ある。FIG. 6 is a side sectional view showing an essential part of a superconducting circuit in a process step for explaining a specific example 1 of the present invention.
【図７】本発明に於ける具体的な実施例１を説明する為
の工程要所に於ける超伝導回路を表す要部切断説明図で
ある。FIG. 7 is a fragmentary explanatory view showing a superconducting circuit in a process key point for explaining a specific example 1 of the present invention.
【図８】本発明に於ける具体的な実施例１を説明する為
の工程要所に於ける超伝導回路を表す要部切断説明図で
ある。FIG. 8 is a fragmentary explanatory view showing a superconducting circuit in a process key point for explaining a specific example 1 of the present invention.
【図９】本発明に於ける具体的な実施例２を説明する為
の工程要所に於ける超伝導回路を表す要部切断側面図で
ある。FIG. 9 is a side sectional view showing a main part of a superconducting circuit in a process main part for explaining a second specific example of the present invention.
【図１０】従来の酸化物超伝導回路を製造する工程を説
明する為の工程要所に於ける酸化物超伝導回路の要部切
断側面図である。FIG. 10 is a side sectional view of a main part of an oxide superconducting circuit at a process step for explaining a conventional process for manufacturing an oxide superconducting circuit.
【図１１】従来の酸化物超伝導回路を製造する工程を説
明する為の工程要所に於ける酸化物超伝導回路の要部切
断側面図である。FIG. 11 is a side sectional view of a main part of an oxide superconducting circuit at a process step for explaining a process of manufacturing a conventional oxide superconducting circuit.
【図１２】従来の酸化物超伝導回路を製造する工程を説
明する為の工程要所に於ける酸化物超伝導回路の要部切
断平面図である。FIG. 12 is a plan view of a main part of an oxide superconducting circuit at a process step for explaining a process of manufacturing a conventional oxide superconducting circuit.
１ 支持基板 ２ 下部超伝導電極 ３ 層間絶縁膜 ４ レジスト膜 ５ 上部超伝導電極 ６ 超伝導接合 1 Support substrate 2 Lower superconducting electrode 3 Interlayer insulation film 4 Resist film 5 Upper superconducting electrode 6 Superconducting junction
───────────────────────────────────────────────────── フロントページの続き (72)発明者 波頭 経裕 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 吉田 晃 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 Ｆターム(参考） 4M113 AA06 AA16 AA25 AA37 AD36 AD42 AD67 AD68 BA01 BA04 BB07 BC04 BC05 BC08 BC22 CA34 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Nobuhiro Hazu 4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 within Fujitsu Limited (72) Inventor Akira Yoshida 4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 within Fujitsu Limited F term (reference) 4M113 AA06 AA16 AA25 AA37 AD36 AD42 AD67 AD68 BA01 BA04 BB07 BC04 BC05 BC08 BC22 CA34
Claims (2)
超伝導電極を形成する工程と、 次いで、該下部超伝導電極上に層間絶縁膜を形成する工
程と、 次いで、該層間絶縁膜及び下地の下部超伝導電極をラン
プ・エッジ構造の塁状に加工する工程と、 次いで、酸化物超伝導体からなる上部超伝導電極を形成
して該下部超伝導電極との接触部分に超伝導接合を生成
させる工程と、 次いで、該上部超伝導電極を該塁状の下部超伝導電極及
び層間絶縁膜を跨いで延在するライン状に加工する工程
と、 次いで、該塁状層間絶縁膜の頂面に在る該ライン状の上
部超伝導電極を研磨除去して該超伝導接合を分離する工
程とが含まれてなることを特徴とする高集積超伝導回路
の製造方法。1. A step of forming a lower superconducting electrode made of an oxide superconductor on a supporting substrate, a step of forming an interlayer insulating film on the lower superconducting electrode, and a step of forming the interlayer insulating film. And a step of processing the underlying lower superconducting electrode into a ramp-shaped base structure, and then forming an upper superconducting electrode made of an oxide superconductor and superconducting at a contact portion with the lower superconducting electrode. A step of forming a bond, a step of processing the upper superconducting electrode into a line shape extending across the base-shaped lower superconducting electrode and the interlayer insulating film, and then a step of forming the base-shaped interlayer insulating film. And a step of polishing and removing the line-shaped upper superconducting electrode present on the top surface to separate the superconducting junction.
後、全面に保護膜を形成してから塁状層間絶縁膜の頂面
に在る該ライン状の上部超伝導電極を研磨除去して該超
伝導接合を分離する工程とが含まれてなることを特徴と
する請求項１記載の高集積超伝導回路の製造方法。2. After the upper superconducting electrode is processed into a line shape, a protective film is formed on the entire surface, and then the line-shaped upper superconducting electrode on the top surface of the base-shaped interlayer insulating film is removed by polishing. 2. The method for manufacturing a highly integrated superconducting circuit according to claim 1, further comprising a step of separating the superconducting junction.
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|---|---|---|---|
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001286597A JP2003101090A (en) | 2001-09-20 | 2001-09-20 | Manufacturing method for high integrated superconducting circuit |
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|---|---|---|---|---|
| JPS6060783A (en) * | 1983-09-14 | 1985-04-08 | Nec Corp | Manufacture of superconducting circuit device |
| JPS6486575A (en) * | 1987-06-17 | 1989-03-31 | Hitachi Ltd | Superconducting device |
| JPH10150229A (en) * | 1996-11-20 | 1998-06-02 | Nec Corp | Superconductive circuit |
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