JP2003086851A - Low-inductance superconducting junction and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a low-inductance superconducting junction to operate at a high speed of >=20 [GHz] by reducing the inductance of the junction by adopting an extremely simple means, and to provide a method of manufacturing the junction. SOLUTION: In the lamp-edge type superconducting junction using an oxide superconductor, an upper superconducting electrode 24 is extended along a slope composed of a lower superconducting electrode 22 and an interlayer insulating film 23 and, at the same time, is terminated at an appropriate location between the junction 25 with the lower superconducting electrode 22 and the top of the slope of the insulating film 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-inductance superconducting junction suitable for constituting a superconducting circuit which is being used in the fields of communication, computers, measurement, etc., and a manufacturing method thereof.

[0002]

2. Description of the Related Art Currently, communication routers, servers, AD
Development of superconducting circuits used for converters, magnetometers (SQUIDs), samplers, etc. is urgent.

Oxide superconducting junctions are often used to form this superconducting circuit, and ramp edge junction is known as one of the types of the superconducting junctions.

FIG. 7 is a side sectional view showing an oxide superconducting junction having a ramp edge junction structure.
1 is a supporting substrate, 2 is a lower superconducting electrode, 3 is an interlayer insulating film,
Reference numerals 4 denote upper superconducting electrodes, respectively.

In this oxide superconducting junction, the interlayer insulating film 3 covering the portion indicated by the symbol L, that is, the lower superconducting electrode 2.
A part of the upper superconducting electrode 4 extends beyond the slope of No. 3, and due to this, a large inductance of 1.5 [pH] appears, which hinders high-speed operation.

Although this portion L is required in the process of manufacturing the junction, it is a portion that becomes a play in the superconducting circuit, and moreover, there is variation in the portion L due to the alignment accuracy in the lithography technique. It often happens.

Of course, if there is such a variation, the inductance in each superconducting junction will be different, so that the inductance will vary in the superconducting circuit. However, it is impossible to unambiguously implement it, and it is difficult to construct a high-speed superconducting circuit.

[0008]

SUMMARY OF THE INVENTION In the present invention, the inductance of a superconducting junction is reduced by adopting an extremely simple means, and a high speed operation of 20 [GHz] or higher is made possible.

[0009]

In the low-inductance superconducting junction and the method for manufacturing the same according to the present invention, a portion in which the upper superconducting electrode extends beyond the slope of the interlayer insulating film covering the lower superconducting electrode. Is basically eliminated to reduce the inductance, thereby achieving high-speed operation.

FIG. 1 is a cutaway side view of essential parts showing a superconducting junction for explaining the principle of the present invention. In the figure, 21 is a supporting substrate, 22 is a lower superconducting electrode, and Reference numeral 23 is an interlayer insulating film, 24 is an upper superconducting electrode, and 25 is a superconducting junction.

As is apparent from the figure, the upper superconducting electrode 24 in the present invention is originally a part of the interlayer insulating film 23 that extends beyond the slant surface to the flat surface, and is therefore cut off. The inductance is significantly reduced.

By the way, since the purpose of the superconducting junction is different from that of the superconducting junction according to the present invention, the conventional technique of the present invention cannot be realized. No. 10-150228), it is thought that it is meaningful to mention it in order to recognize the effectiveness of the superconducting junction of the present invention.

FIG. 8 is a cutaway side view of a main part of a conventional superconducting circuit. In the figure, 10 is a substrate, 11 is a lower electrode, 12 is a first insulating film, 13 is a tunnel barrier, and 14 is a tunnel barrier.
Is an upper electrode, 16 is a second insulating film, and 17 is a ground plane.

As shown in FIG. 8, this superconducting circuit is characterized in that the portion other than the inclined portion of the lower electrode 11 where the lower electrode 11 and the upper electrode 14 overlap with each other through the tunnel barrier 13 is removed and the surface is flat. It has a converted edge joint.

There are two methods for surface flattening, one is a method of flattening the first insulating film 12 as shown in FIG. 8A, and the other is flattening. Is
As shown in FIG. 8B, this is a method of planarizing without leaving the first insulating film 12.

As described above, the reason why the flattened edge junction is generated on the surface is that the ground plane 17 is formed via the second insulating film 16 as shown in FIG. 8C. It depends on what you have to do.

There are several problems in implementing the superconducting circuit seen in FIG. 1. When the first insulating film 12 is left flat on the lower electrode 11 and planarized, in this case, because of the structure, the thickness of the upper electrode 14 is equal to the total thickness of the lower electrode 11 and the first insulating film 12. This is necessary, and therefore the line thickness will change in the superconducting circuit, so the inductance and the superconducting current density will be different, and the circuit design will be difficult to achieve.

2. The first insulating film 12 is formed on the lower electrode 11.
In the case of flattening without leaving, the superconducting joint portion is polished and the joint is damaged, so that the characteristics are deteriorated.

3. It seems that if the ground plane 17 is formed on the upper portion, good bonding characteristics can be realized, but even if the upper surface of the bonding is flattened, steps are formed on the side surfaces of the bonding. Therefore, a portion having a weak superconducting state is generated in the ground plane 17 above the step portion, and it is highly possible that the magnetic field is trapped. As a result, the junction characteristics change depending on the magnetic field, and It will cause malfunction.

4. By forming the ground plane 17 on the upper side, the superconducting circuit is directly affected by the permittivity of the substrate, and the inductance increases when the permittivity is high. By the way, YBCO (YBa ₂ Cu ₃ O
SrTi as a suitable substrate for growing _7-x )
O ₃ or LaSrAlTaO is used. Since these have a dielectric constant of 20 or more, it is necessary to dispose the ground plane in the lower part to block the influence of the dielectric constant of the substrate in order to reduce the inductance.

In the superconducting junction according to the present invention, it is premised that the ground plane is arranged in the lower layer, and the reduction of the inductance of the junction itself is realized while avoiding the deterioration of the junction characteristics.

Therefore, it is indispensable to remove only the unnecessary portion on the upper surface of the joint, leave the protruding portion irrespective of the flatness, and cover the joint so as not to expose it.

In the present invention, by adopting the above means,
Not only can the inductance of the strip line be reduced, but also the inductance of the junction itself can be reduced, so that a superconducting circuit excellent in high-speed operability and practicability can be realized.

[0024]

2 and 3 are side sectional views showing essential parts of a superconducting junction in the process steps for explaining the first embodiment of the present invention. Will be described with reference to. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

See FIG. 2A. (1) LSAT (LaSrAlTa) which is an oxide material.
A support base 31 made of O _x ) is prepared.

See FIG. 2B. (2) By applying the laser ablation method, YBCO having a thickness of 200 nm is formed on the supporting substrate 31.
(YBa ₂ Cu ₃ O _7-x ) oxide superconductor layer 3
Form 2.

(3) Similarly, by applying the laser ablation method, the interlayer insulating layer 33 made of LSAT and having a thickness of 200 nm is formed on the oxide superconductor layer 32.

See FIG. 2C. (4) By applying a resist process, a resist layer serving as a mask when forming a slope (not shown).
To form.

(5) By applying the ion milling method, the ion acceleration voltage is set to 200 [V] to 700.
By appropriately selecting in the range of [V], the interlayer insulating layer 33 and the superconductor layer 32 are milled so as to have a slope shape of an angle of 30 ° by bombarding ions with the resist layer as a mask in an oblique direction. A barrier layer made of a modified layer is formed on the slope of the lower superconducting electrode 32E as well as the lower superconducting electrode 32E.

Referring to FIG. 3A (6), by applying the laser ablation method, an oxide superconductor layer 34 of YBCO having a thickness of 200 nm is formed. In the figure, the lower superconducting electrode 3
2E and oxide superconductor layer 34 to serve as upper superconducting electrode
The joint portion with and is indicated by the symbol 40 and is exaggerated slightly.

Referring to FIG. 3B (7), by applying a resist process, a resist layer (not shown) serving as a mask for forming the upper superconducting electrode is formed.

(8) By applying the same conditions as in the ion milling method adopted in the step (5), the superconductor layer 34 reaches the interlayer insulating layer 33 from the surface using the resist layer as a mask. Milling up to the upper superconducting electrode 34E.

Here, a part of the upper superconducting electrode 34E existing on the interlayer insulating layer 33 remains in a state of facing the lower superconducting electrode 32E, which causes generation of parasitic inductance.

Referring to FIG. 3 (C) (9), the upper superconducting electrode 34E is polished by using alumina having a diameter of 0.03 [μm] or less, and the lower superconducting electrode 3
The portion facing 2E and extending beyond the slope of the interlayer insulating layer 33 is removed.

In the first embodiment, the upper superconducting electrode 3
The unnecessary portion of 4E can be efficiently removed by simple polishing because the area of the polished portion is small, and if necessary, a protective film is formed on the entire surface and then the upper portion is removed. Damage to the superconducting electrode 34E can be effectively suppressed.

Although the degree of polishing is important in the above description of the steps, the lower superconducting electrode 32E can be obtained by polishing so that the entire surface becomes flat as seen in the above-mentioned conventional technique. Since the edge of the joining portion with the upper superconducting electrode 34E is exposed and the characteristics are deteriorated, it is necessary to limit at least the edge of the joining portion to the polishing limit.

FIG. 4 is a cutaway side view of an essential part showing a superconducting junction in a process step for explaining the second embodiment of the present invention, which will be described below with reference to these figures. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings, and the upper superconducting electrode 34E
Since the steps up to the formation of the superconductor layer 34 for forming the same are the same as those in the first embodiment, the description thereof will be omitted and will be described from the next stage.

See FIG. 4A. (1) The portion of the superconductor layer 34 that faces the lower superconducting electrode 32E and extends beyond the slope of the interlayer insulating layer 33 by applying a resist process. A resist layer 35 having a pattern for removing is formed.

In this case, unlike the first embodiment, the patterning of the superconductor layer 34 and the removal of the portion producing the parasitic inductance are carried out at the same time.
Moreover, the removal of the part that creates the parasitic inductance is
Junction part 4 of lower superconducting electrode 32E and upper superconducting electrode
The patterning technique with high alignment accuracy is necessary because the process is performed at the limit where 0 edges are not exposed.

Here, the layer thickness of the superconductor layer 34 is about 200.
Since the length of the inclined surface of the interlayer insulating film 33 is 400 [nm] on the inclined surface of about [nm] and the angle of 30 °, the alignment accuracy is required to be 200 [nm] or less, To meet the demand, for example, an electron beam exposure method is useful.

See FIG. 4B. (2) By applying the same conditions as in the ion milling method adopted in the step (5), the resist layer 35 is used as a mask to form the superconductor layer 34 from the surface to the bottom. Until just before reaching the superconducting electrode 32E, the lower superconducting electrode 32
The upper superconducting electrode 34E is milled until just before the edge of the joint portion 40 between E and the upper superconducting electrode is exposed.

FIG. 5 and FIG. 6 are sectional side views of essential parts showing superconducting junctions in the process steps for explaining the third embodiment of the present invention. Hereinafter, with reference to these drawings, FIG. explain. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

See FIG. 5A. (1) By applying the resist process and the ion milling method, the depth is selected in the range of 300 [nm] to 500 [nm] for the support base 31 made of LSAT. The ground plane forming recess 31A is formed.

Refer to FIG. 5B (2) By applying the laser ablation method, the range of 300 [nm] to 500 [nm] is provided on the supporting substrate 31 including the recess 31 A for forming the ground plane. A ground plane layer 41 made of YBCO having a thickness selected in step 1 is formed.

Refer to FIG. 5C. (3) By applying the resist process, the ground plane forming recess 31A is filled with the ground layer.
A resist film is formed on the plane layer 41 and the ground plane layer 41 on the flat surface of the support substrate 31 so as to cover the ground plane layer 41.

By performing the above, the following wet
When etching is performed, it is possible to prevent erosion of the ground plane portion due to etching from the side.

(4) The ground plane layer 41 is etched using the resist film as a mask by applying a wet etching method using HCl diluted to 1/1000 as an etchant.

By this step, the ground plane layer 41 on the flat surface of the supporting substrate 31 is almost removed, but the resist film described above is formed near the edge of the recess 31 for forming the ground plane. Due to the pattern, a part remains as a protrusion.

See FIG. 6A (5) The surface is flattened by polishing the surface with alumina having a diameter of 0.03 [μm] or less. Needless to say, the protrusions are removed by this polishing.

See FIG. 6B. (6) By applying the laser ablation method, the entire surface including the ground plane layer 41 has a thickness of 20.
LS selected in the range of 0 [nm] to 300 [nm]
An interlayer insulating layer 42 made of AT is formed.

After this, the same steps as in the first embodiment, namely,
The same steps as those described with reference to FIGS. 2B to 3C are performed to form the lower superconducting electrode 3 on the interlayer insulating layer 42.
2E, the interlayer insulating film 33, the upper superconducting electrode 34E, the bonding portion 40 and the like are formed, and the upper superconducting electrode 34E is polished to complete the process. Therefore, the completed superconducting junction has a structure in which the superconducting junction shown in FIG. 3C is mounted on the interlayer insulating layer 42.

In each of the above-mentioned embodiments, LSAT was used as the support base made of an oxide material.
Alternatively, a supporting substrate formed by forming a buffer layer of Y ₂ O ₃ or CeO _{2 on} MgO can be used, or SrTiO ₃ or the like can be used.

In each of the above embodiments, YBCO was used as the oxide superconductor, but in addition to this, NdBa ₂ Cu ₃ O was used.
Other oxide superconductor materials such as _x can be used.

In each of the above-mentioned embodiments, the laser ablation method is applied to deposit the thin film, but in addition to this, a magnetron sputtering method, an off-axis sputtering method or the like may be appropriately selected.

[0055]

According to the present invention, there is provided a low-inductance superconducting junction and a method of manufacturing the same. In a lamp-edge type superconducting junction using an oxide superconductor, the upper superconducting electrode is a lower superconducting electrode. And an interlayer insulating film, and extends at a proper position beyond the junction with the lower superconducting electrode and beyond the slope of the interlayer insulating film.

By adopting the above configuration, the strip
Not only can the line inductance be reduced, but the inductance of the junction itself can also be reduced, so that a superconducting circuit with excellent high-speed operability and practicality can be realized.

[Brief description of drawings]

FIG. 1 is a cutaway side view of essential parts showing a superconducting junction for explaining the principle of the present invention.

FIG. 2 is a cutaway side view of an essential part showing a superconducting junction in a process key point for explaining the first embodiment of the present invention.

FIG. 3 is a cutaway side view of an essential part showing a superconducting junction in a process key point for explaining the first embodiment of the present invention.

FIG. 4 is a cutaway side view of an essential part showing a superconducting junction in a process essential part for explaining a second embodiment of the present invention.

FIG. 5 is a cutaway side view of an essential part showing a superconducting junction in a process essential part for explaining a third embodiment of the present invention.

FIG. 6 is a cutaway side view of essential parts showing a superconducting junction in a process key part for explaining a third embodiment of the present invention.

FIG. 7 is a cutaway side view of essential parts showing an oxide superconducting junction having a ramp edge junction structure.

FIG. 8 is a cutaway side view of a main part of a conventional superconducting circuit.

[Explanation of symbols]

21 support substrate 22 Lower superconducting electrode 23 Interlayer insulation film 24 Upper superconducting electrode 25 Superconducting junction

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Nobuhiro Hazu             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F-term (reference) 4M113 AA06 AA16 AA25 AA37 AD35                       AD36 AD37 AD42 AD67 AD68                       BA01 BA04 BA08 BB07 BC04                       BC08 BC22 CA34

Claims (5)

[Claims] 1. In a ramp-edge type superconducting junction using an oxide superconductor, an upper superconducting electrode extends along a slope formed by a lower superconducting electrode and an interlayer insulating film, and a lower superconducting electrode. A low-inductance superconducting junction having a structure in which it is terminated at an appropriate position beyond the junction with the electrode and beyond the slope of the interlayer insulating film. 2. A superconducting ground layer below the lower superconducting electrode.
The low inductance superconducting junction according to claim 1, wherein a plane is provided. 3. A step of forming an upper superconducting electrode extending along a slope formed on a side surface of the laminated lower superconducting electrode and the interlayer insulating film, and a step of forming a tip of the upper superconducting electrode at the lower superconducting electrode. A method of manufacturing a low-inductance superconducting junction, which comprises a step of removing it at a proper position beyond the junction with the electrode and beyond the slope of the interlayer insulating film. 4. The method of manufacturing a low inductance superconducting junction according to claim 3, wherein the removal of the tip of the upper superconducting electrode is performed by polishing. 5. The method for producing a low-inductance superconducting junction according to claim 3, wherein the removal of the tip of the upper superconducting electrode is performed by patterning.