JP4843772B2 - Method for manufacturing superconducting circuit device - Google Patents

Description

The present invention relates to a method of manufacturing a superconducting circuit device , and more particularly to manufacturing a superconducting circuit device characterized by a ground plane processing procedure for reducing variations in critical current density of Josephson junctions and reducing parasitic inductance. It is about the method.

  In recent years, high-temperature oxide superconductors typified by yttrium-based superconductors exhibit a superconducting state at a temperature higher than the liquid nitrogen temperature, so the cooling mechanism has been simplified compared to conventional metal-based superconductors that require cooling with liquid He. Various applications to sensors, logic circuits, and the like are expected (see, for example, Patent Document 1).

Here, an example of the manufacturing process of the conventional high-temperature superconducting circuit device will be described with reference to FIGS.
See FIG.
First, a La—YBCO (La doped YBa ₂ Cu ₃ O _7-x ) layer 42 to be a ground plane and a first insulating layer 43 made of SrSnO _x are sequentially formed on the MgO substrate 41 by sputtering. .
Next, the exposed portion of the first insulating layer 43 and the La-YBCO layer 42 is removed using an ion milling method using a resist pattern (not shown) as a mask to form a ground plane 44.

Next, the second insulating layer 45 made of SrSnO _x is formed on the entire surface by sputtering again.
In this film forming process, O ₂ escapes from the ground plane 44 and the conductivity is lowered.
Next, contact holes 46 and moats 47 that reach the MgO substrate 41 are formed by ion milling using a resist pattern (not shown) as a mask.

See FIG.
Next, a La—YBCO layer 48 to be a base electrode and an SrSnO _x layer 49 to be a base insulating layer are sequentially deposited again by using a sputtering method.
Next, the exposed portions of the SrSnO _x layer 49 and the La—YBCO layer 48 are removed by ion milling using a resist pattern (not shown) as a mask, thereby forming the base electrode 50 and the base insulating layer 51.
At this time, the La-YBCO layer 48 is left also in the contact hole 46 to form the plug 52.

Patterning by ion milling at this time is performed from an angle of 30 ° to form a ramp edge junction, and an inclined surface of about 30 ° is formed.
After removing the resist, a Josephson junction barrier is formed as a damage layer on the slope of the La-YBCO layer 48, which corresponds to the interface with the so-called YBCO layer, by surface modification by ion milling. .
This is known as surface-modified bonding, and the damage layer is formed by, for example, Ar ions accelerated at 500 V from the direction perpendicular to the substrate.

  Next, after a YBCO layer 53 serving as a counter electrode is formed on the entire surface using a laser ablation method, an Au protective layer 54 is sequentially deposited using a sputtering method.

Next, the exposed portions of the Au protective layer 54 and the YBCO layer 53 are removed using an ion milling method using a resist pattern (not shown) as a mask to form a counter electrode 55.
At this time, the YBCO layer 53 and the Au protective layer 54 are also left in the periphery of the plug 52 and the periphery of the moat 47.

Next, by performing an annealing process in an O ₂ atmosphere, O ₂ is supplied to the ground plane 44 via the moat 47 to restore the conductivity of the ground plane that has been lowered in the film forming process after the patterning process described above.
Next, an Au layer 56 serving as a wiring layer is formed on the entire surface by sputtering.

See FIG.
Next, the Au layer 56 is patterned using an ion milling method using a resist pattern (not shown) as a mask to form an Au wiring 57 and a resistance forming portion 58 is formed.

Next, a VTi layer 59 to be a resistance is deposited on the entire surface using a sputtering method, and finally, the VTi layer 59 is patterned using an ion milling method using a resist pattern (not shown) as a mask to form a resistor 60. As a result, the basic configuration of the high-temperature superconducting circuit device is completed.
JP 2000-353831 A

However, in the high temperature superconductor circuit device manufactured as described above, there is a problem that the circuit operation variation greatly stabilized critical current I _c of the Josephson junction constituting the high-temperature superconductor circuit is difficult, 15 and This situation will be described with reference to FIG.

See FIG.
Conventionally, the Josephson junction is formed after patterning the ground plane 44, but due to the low thermal conductivity of the MgO substrate 41, there is a difference in temperature between where the ground plane 44 is located and where it is not. Crystal growth is simultaneously performed on the base, and the crystallinity of the second insulating layer serving as the base for forming the Josephson junction becomes nonuniform.

That is, as shown in FIG. 15, when the ratio occupied by the area without the ground plane 44 is large, the surface roughness Ra of the second insulating layer and the La-YBCO layer that becomes the base electrode is increased. There is a tendency, and the surface roughness of the La-YBCO layer serving as the base electrode is closely related to variations in the critical current I _c of the Josephson junction, and therefore the critical current I _{c of the} Josephson junction varies. .

As described above, when the surface roughness of the La-YBCO layer is increased, in the ion milling process for patterning the La-YBCO layer to the base electrode, the end surface shape of the base electrode on which the unevenness of the surface of the La-YBCO layer is patterned is changed. In order to make it uneven, the critical current I _{c of the} Josephson junction varies.

See FIG.
Figure 16 is shows the average surface roughness Ra dependence of La-YBCO layer of variation of the critical current I _c of the Josephson junction, almost proportional.

In the conventional manufacturing method, the average surface roughness Ra (according to JIS standard) of the La-YBCO layer reaches an average of 4.9 nm, and as it is apparent from FIG. 16, the variation in the critical current I _c of the Josephson junction is not It will exceed 50%.

In order to operate the circuit stably, since it is desired to variations in the critical current I _c of the Josephson junction to 10% or less, the variation does not operate the circuit exceeds 50%.

In order to improve such a problem, although the average surface roughness Ra can be improved to about 1.8 nm by a flattening technique by polishing, the polished surface suffers physical damage accompanying polishing. The variation of the critical current I _c of this is improved only to about 30%, and stable operation is still difficult.

  Accordingly, an object of the present invention is to reduce the average surface roughness to such an extent that stable circuit operation is possible by devising the process, and to enable high-speed operation.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
To solve the above-described problem, the present invention provides a method for manufacturing a superconducting circuit device , wherein a Josephson made of a high-temperature superconductor via a first insulating layer 3 is formed on a ground plane 2 made of a high-temperature superconductor. It is characterized by having a step of patterning the ground plane 2 after forming the element 4 .

Thus, before the patterning process of the ground plane 2, that is, in a state where most of the surface of the substrate 1 is covered with the ground plane 2, the base electrode 5 constituting the first insulating layer 3 and the Josephson element 4 and By forming the base insulating layer 6, the average surface roughness Ra of the base electrode 5 can be reduced to 1 nm or less, whereby the variation in critical current of the Josephson element 4 can be reduced to 10% or less. .

In this case, the ground plane contact hole 8 and the magnetic flux trap moat 9 may be formed simultaneously before the patterning process of the ground plane 2, or the magnetic flux trap moat 9 may be formed simultaneously with the patterning process of the ground plane 2. The latter may have a higher ratio of the base electrode 5 covered with the ground plane 2 in the film formation process of the base electrode 5, so that the average surface roughness Ra of the base electrode 5 can be further reduced.
The oxygen supply via hole may be formed simultaneously with the ground plane contact hole 8.

  When the above-described process is employed, the second insulating layer 10 is provided on at least the side end face of the ground plane 2 and the counter electrode 7 of the Josephson element 4 after the patterning process of the ground plane 2.

  According to the present invention, when the high-temperature superconductor serving as the base electrode constituting the Josephson junction is formed, most of the surface of the substrate is covered with the ground plane, so that the temperature becomes uniform and the average of the base electrode The surface roughness Ra can be reduced to 1 nm or less, whereby the variation in critical current of the Josephson element can be reduced to 10% or less.

  In the present invention, a high-temperature superconductor serving as a ground plane and an insulating layer on the ground plane are formed on a substrate, then at least a ground plane contact hole is formed, and then a high-temperature superconductor serving as a base electrode and the base insulating layer are deposited. After patterning, a base electrode is formed, then a counter electrode is formed, and then a ground plane is patterned. Next, an interlayer made of an oxide dielectric or photosensitive polyimide that can be formed at a low temperature of 300 ° C. or lower. The surface is covered with an insulating film.

  The moat for trapping the magnetic flux and the via hole for supplying oxygen may be formed at the same time as the ground plane contact hole, or may be formed at the same time as the patterning process of the ground plane. When it also serves as, it is not necessary to provide an oxygen supply via hole.

Here, with reference to FIG. 2 thru | or FIG. 6, the manufacturing process of the superconducting circuit device of Example 1 of this invention is demonstrated.
See Figure 2
First, a La-YBCO layer 12 having a thickness of, for example, 200 nm is formed on the MgO substrate 11 by sputtering, for example, at 680 ° C., and then, for example, a thickness of SrSnO _{x at} 660 ° C. For example, the first insulating layer 13 having a thickness of 300 nm is formed.

  Next, the exposed portions of the first insulating layer 13 and the La-YBCO layer 12 are removed using an ion milling method using a resist pattern (not shown) as a mask to form contact holes 14 and moats 15.

Next, using a sputtering method again, for example, after forming a La-YBCO layer 16 having a thickness of 300 nm, for example, at 680 ° C., the thickness to be a base insulating layer at 660 ° C. is, for example, A 200 SrSnO _x layer 17 is formed.

In this case, since the surface of the MgO substrate 11 is covered with the La-YBCO layer 12 except for the region of the contact hole 14 and the moat 15 in the film forming process of the La-YBCO layer 16, the temperature uniformity is improved. The average surface roughness Ra of the La—YBCO layer 16 is 1 nm or less.
Further, in this film forming process, O ₂ escapes from the La—YBCO layer 12 serving as a ground plane and the conductivity is lowered, so that oxygen annealing described later is required.

Next, the exposed portions of the SrSnO _x layer 17 and the La—YBCO layer 16 are removed by ion milling using a resist pattern (not shown) as a mask to form the base electrode 18 and the base insulating layer 19.
At this time, after this process is performed from an oblique direction to form a slope, the resist is removed, and then a barrier by a surface-modified damage layer is formed on the surface of the superconductor slope. Do.
At this time, the La-YBCO layer 16 remains in the contact hole 14 to form the plug 20.

See Figure 3
Next, after forming a YBCO layer 21 having a thickness of, for example, 300 nm as a counter electrode on the entire surface by using a laser ablation method, for example, at 660 ° C., a Au film having a thickness of, for example, 200 nm is formed by using a sputtering method. A protective layer 22 is sequentially deposited.

Next, the exposed portions of the Au protective layer 22 and the YBCO layer 21 are removed using an ion milling method using a resist pattern (not shown) as a mask to form a counter electrode 23.
At this time, the YBCO layer 21 and the Au protective layer 22 are also left in the periphery of the plug 20 and the periphery of the moat 15.

Next, the exposed portions of the SrSnO _x layer 13 and the La—YBCO layer 12 are removed using an ion milling method using a resist pattern (not shown) as a mask to form a ground plane 24.

See Figure 4
Next, annealing is performed in an O ₂ atmosphere to supply O ₂ to the ground plane 24 via the moat 15 and the exposed end surface, thereby restoring the conductivity of the ground plane 24 that has been lowered in the above-described film forming process.

Next, an interlayer insulating layer 25 made of SrSnO _x having a thickness of, for example, 200 nm is deposited on the entire surface by sputtering, for example, at 200 ° C.
In this case, the film forming temperature is set to 300 ° C. or lower, specifically 200 ° C., so that O ₂ does not escape from the exposed portion of the ground plane 24 and the Josephson junction is not damaged.

Next, the exposed portions of the interlayer insulating layer 25 are removed by ion milling using a resist pattern (not shown) as a mask to form contact holes 26, 27, and 28.
At this time, the etching rate of the interlayer insulating layer 25 made of SrSnO _x grown at a low temperature is about 1.4 times the etching rate of the Au protective layer 22 exposed in the contact holes 26, 27, 28. It disappears and the counter electrode 23 is not damaged.

See Figure 5
Next, an Au layer 29 having a thickness of, for example, 500 nm is formed on the entire surface by sputtering.

  Next, the Au layer 29 is patterned using an ion milling method using a resist pattern (not shown) as a mask to form an Au wiring 30, and a resistance forming portion 31 is formed.

See FIG.
Next, after a VTi layer 32 having a thickness of, for example, 50 nm is deposited on the entire surface using a sputtering method, finally, a VTi layer is formed using an ion milling method using a resist pattern (not shown) as a mask. By patterning layer 32 to form resistor 33, the basic configuration of the high temperature superconducting circuit device is completed.

See FIG.
FIG. 7 is a diagram in which the average surface roughness Ra of the La—YBCO layer 16 serving as the base electrode is compared with the case of the conventional manufacturing method. In Example 1 of the present invention, the average surface roughness is 1 nm or less. It can be seen that Ra is realized.

Therefore, as apparent from FIG. 16 described above, in the first embodiment of the present invention, the variation in the critical current I _c of the Josephson junction can be reduced to 10% or less, thereby allowing the superconducting circuit to operate stably. Is possible.

  In Example 1, since the upper portion of the Josephson junction is covered with the interlayer insulating layer 25 in the film forming process of the Au layer 28 and the VTi layer 31, the Josephson junction is not damaged.

  In addition, since only a single 300-nm first insulating layer 13 is interposed between the ground plane 24 and the base electrode 18, the parasitic inductance is reduced compared to the prior art and high-speed operation is possible.

Here, with reference to FIG. 8 thru | or FIG. 10, the manufacturing process of the superconducting circuit device of Example 2 of this invention is demonstrated.
See FIG.
First, similarly to Example 1, after forming the La-YBCO layer 12 having a thickness of, for example, 200 nm as a ground plane at 680 ° C. using the sputtering method on the MgO substrate 11, for example, 660 The first insulating layer 13 having a thickness of, for example, 300 nm made of SrSnO _{x at a} temperature of 0 ° C. is formed.

  Next, the exposed portions of the first insulating layer 13 and the La—YBCO layer 12 are removed using an ion milling method using a resist pattern (not shown) as a mask to form a contact hole.

Next, using a sputtering method again, for example, after forming a La-YBCO layer 16 having a thickness of 300 nm, for example, at 680 ° C., the thickness to be a base insulating layer at 660 ° C. is, for example, A 200 SrSnO _x layer 17 is formed.

See FIG.
Next, the exposed portions of the SrSnO _x layer 17 and the La—YBCO layer 16 are removed by ion milling using a resist pattern (not shown) as a mask to form the base electrode 18 and the base insulating layer 19.
At this time, after this process is performed from an oblique direction to form a slope, the resist is removed, and then a barrier by a surface-modified damage layer is formed on the surface of the superconductor slope. Do.
At this time, the La-YBCO layer 16 remains in the contact hole 14 to form the plug 20.

  Next, after forming a YBCO layer 21 having a thickness of, for example, 300 nm as a counter electrode on the entire surface by using a laser ablation method, for example, at 660 ° C., a Au film having a thickness of, for example, 200 nm is formed by using a sputtering method. A protective layer 22 is sequentially deposited.

Next, the exposed portions of the Au protective layer 22 and the YBCO layer 21 are removed using an ion milling method using a resist pattern (not shown) as a mask to form a counter electrode 23.
At this time, the YBCO layer 21 and the Au protective layer 22 are also left around the plug 20.

See FIG.
Next, an exposed portion of the first insulating layer 13 and the La-YBCO layer 12 is removed by ion milling using a resist pattern (not shown) as a mask to form a ground plane 24 and a moat 15 is simultaneously formed. To do.

Thereafter, in the same manner as in the first embodiment, annealing is performed in an O ₂ atmosphere, so that O ₂ is supplied to the ground plane 24 via the moat 15 and the exposed end face, and is reduced in the above-described film forming process. The conductivity of the ground plane 24 is restored.

Next, an insulating layer made of SrSnO _x having a thickness of, for example, 200 nm is deposited on the entire surface by sputtering, for example, at 200 ° C., and then the insulating layer is formed by ion milling using a resist pattern as a mask. The exposed portion is removed to form a contact hole.

  Next, an Au layer having a thickness of, for example, 500 nm is formed on the entire surface by sputtering, and then the Au layer is patterned by ion milling using a resist pattern as a mask. And a resistance forming portion is formed.

  Next, after depositing a VTi layer having a resistance thickness of, for example, 50 nm on the entire surface by sputtering, the VTi layer is patterned by ion milling using a resist pattern (not shown) as a mask. By forming the resistor 33, the basic configuration of the high-temperature superconducting circuit device is completed.

  The operational effects of the second embodiment are basically the same as those of the first embodiment. However, in the second embodiment, the MgO substrate 11 has a larger area in the film-forming process of the La-YBCO layer 16 serving as the base electrode. Since it is covered with the La-YBCO layer 12, the average surface roughness Ra of the La-YBCO layer 16 can be further reduced.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the conditions and configurations described in each embodiment, and various modifications are possible. For example, the substrate described in each embodiment The material of the high-temperature superconductor, the insulator, the conductor, the film thickness, and the like can be arbitrarily changed.

For example, in each of the above embodiments, an MgO substrate is used as the substrate. However, the substrate is not limited to an MgO substrate, and is not limited to an LSAT, that is, [LaAlO ₃ ] _0.3 [Sr (Al, Ta) O ₃ ] _0.7 or SrTiO ₃ or the like may be used.

In each of the above embodiments, the base electrode is made of La-YBCO having a relatively high film formation temperature, and the counter electrode is made of YBCO having a relatively low film formation temperature. It may be composed of YBCO, or both may be composed of La-YBCO.
The ground plane is not limited to La-YBCO, and YBCO may be used.

Further, the ground plane, the base electrode, and the counter electrode are not limited to YBCO or La-YBCO, and YbBa ₂ Cu ₃ O _7-X or REBa ₂ Cu ₃ O _7-X may be used. .
Note that RE in REBa ₂ Cu ₃ O _7-X is a lanthanoid element other than Pr and Ce, and these are included in a ratio of RE: Ba: Cu = 1: 2: 3 alone or in combination.

In each of the above embodiments, SrSnO _x is used as the first insulating layer, the base insulating layer, and the interlayer insulating film. However, the present invention is not limited to SrSnO _x , and other oxides such as CeO ₂ or MgO are used. A dielectric material may be used.

  The interlayer insulating film is not limited to the oxide dielectric, and photosensitive polyimide may be used. When this photosensitive polyimide is used, the patterning process of the interlayer insulating film is performed by ion milling. Instead, only the exposure and development process can be performed, and the process can be simplified because there is no over-etching.

  In each of the above embodiments, only YBCO to be the counter electrode is formed by the laser ablation method and the others are formed by the sputtering method. However, the opposite film forming methods may be adopted. Alternatively, all of the high-temperature superconductor and the dielectric may be formed by either laser ablation or sputtering.

  In each of the above embodiments, the mote is also used as the oxygen supply via. However, the oxygen supply via may be provided separately. For example, in the case of the first embodiment, contact holes and It may be formed at the same time as the moat forming process, and in the case of Example 2, it may be formed simultaneously with either the contact hole or moat forming process, or may be formed in a completely separate process. It is.

  In the description of each of the above embodiments, for simplicity of illustration, the La-YBCO layer 16 or the interlayer insulating film 25 is illustrated so as to completely fill the contact hole or moat. Although it depends on the thickness of the film to be deposited, it is deposited in a shape that conforms to the shape of the contact hole or moat, and does not completely fill the contact hole or moat.

Here, the detailed features of the present invention will be described again with reference to FIG.
Again see Figure 1
(Additional remark 1 ) After forming the Josephson element 4 which consists of a high temperature superconductor via the 1st insulating layer 3 on the ground plane 2 which consists of a high temperature superconductor, it has the process of patterning the said ground plane 2 A method for manufacturing a superconducting circuit device.
(Supplementary note 2 ) The method of manufacturing a superconducting circuit device according to supplementary note 1, wherein the ground plane contact hole 8 and the magnetic flux trap moat 9 are formed simultaneously before the patterning step of the ground plane 2.
(Supplementary note 3 ) The method for manufacturing a superconducting circuit device according to supplementary note 2, wherein an oxygen supply via hole is formed simultaneously with the ground plane contact hole 8.
(Supplementary note 4 ) The method for manufacturing a superconducting circuit device according to supplementary note 1, wherein a magnetic flux trap moat 9 is formed simultaneously with the patterning step of the ground plane 2.
(Supplementary Note 5) after the ground plane 2 of the patterning step, Appendix 1, characterized in that a second insulating layer 10 at least on the counter electrode 7 of the ground plane 2 of the side end surface and the Josephson element 4 Or a method of manufacturing a superconducting circuit device according to any one of appendix 4 .

  As an application example of the present invention, the use in the field of measurement and communication using a high-temperature superconducting high-speed circuit is typical, but it is also applied to various information processing fields using logical operations. .

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the superconducting circuit device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 2 of the superconducting circuit device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 3 of the superconducting circuit device of Example 1 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 4 of the superconducting circuit device of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 5 of the superconducting circuit device of Example 1 of this invention. It is a comparison figure of average surface roughness Ra. It is explanatory drawing of the manufacturing process to the middle of the superconducting circuit device of Example 2 of this invention. It is explanatory drawing of the manufacturing process to the middle after FIG. 8 of the superconducting circuit device of Example 2 of this invention. It is explanatory drawing of the manufacturing process after FIG. 9 of the superconducting circuit device of Example 2 of this invention. It is explanatory drawing of the manufacturing process to the middle of the conventional superconducting circuit device. It is explanatory drawing of the manufacturing process until the middle of FIG. 11 after the conventional superconducting circuit device. It is explanatory drawing of the manufacturing process until the middle of FIG. 12 after the conventional superconducting circuit device. It is explanatory drawing of the manufacturing process after FIG. 13 of the conventional superconducting circuit device. It is a top view before the film-forming process of the base electrode layer in the manufacturing process of the conventional superconducting circuit device. An average surface roughness Ra dependence of illustration of La-YBCO layer of variation of the critical current I _c of the Josephson junction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Ground plane 3 First insulating layer 4 Josephson element 5 Base electrode 6 Base insulating layer 7 Counter electrode 8 Ground plane contact hole 9 Magnetic flux trap moat 10 Second insulating layer 11 MgO substrate 12 La-YBCO layer 13 First insulating layer 14 Contact hole 15 Mote 16 La-YBCO layer 17 SrSnO _x layer 18 Base electrode 19 Base insulating layer 20 Plug 21 YBCO layer 22 Au protective layer 23 Counter electrode 24 Ground plane 25 Interlayer insulating layer 26 Contact hole 27 Contact hole 28 Contact hole 29 Au layer 30 Au wiring 31 Resistance forming part 32 VTi layer 33 Resistance 41 MgO substrate 42 La-YBCO layer 43 First insulating layer 44 Ground plane 45 Second insulating layer 46 Contact hole 47 Moat 48 L a-YBCO layer 49 SrSnO _x layer 50 Base electrode 51 Base insulating layer 52 Plug 53 YBCO layer 54 Au protective layer 55 Counter electrode 56 Au layer 57 Au wiring 58 Resistance forming portion 59 VTi layer 60 Resistance

Claims (3)

  Manufacturing a superconducting circuit device comprising a step of forming a Josephson element made of a high-temperature superconductor on a ground plane made of a high-temperature superconductor via a first insulating layer and then patterning the ground plane. Method. 2. The method of manufacturing a superconducting circuit device according to claim 1, wherein a ground plane contact hole and a magnetic flux trapping mote are simultaneously formed before the patterning process of the ground plane. 2. The method of manufacturing a superconducting circuit device according to claim 1, wherein a magnetic flux trap moat is formed simultaneously with the patterning step of the ground plane.

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