JP2003100631A - Semiconductor manufacturing method and semiconductor device - Google Patents

Semiconductor manufacturing method and semiconductor device

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Publication number
JP2003100631A
JP2003100631A JP2001288879A JP2001288879A JP2003100631A JP 2003100631 A JP2003100631 A JP 2003100631A JP 2001288879 A JP2001288879 A JP 2001288879A JP 2001288879 A JP2001288879 A JP 2001288879A JP 2003100631 A JP2003100631 A JP 2003100631A
Authority
JP
Japan
Prior art keywords
region
silicon film
catalyst substance
film
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001288879A
Other languages
Japanese (ja)
Inventor
Yasuyuki Umenaka
靖之 梅中
Yoshinobu Nakamura
好伸 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2001288879A priority Critical patent/JP2003100631A/en
Publication of JP2003100631A publication Critical patent/JP2003100631A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method for manufacturing a crystalline silicon film, excellent in performance, reliability and stability, from an amorphous silicon film, and to provide a semiconductor device. SOLUTION: An islanded amorphous silicon film 5 laminated on a substrate 4 is provided with a catalyst substance adding area 9 for adding a catalyst substance, and a crystal growth area 10 is arranged in which a single crystal grain is grown, while the film 5 is configured so that a route 12 having crystal grain boundary guiding areas 11 for growing unnecessary crystal grains between the catalyst substance adding area 9 and the crystal growing area 10 at both sides of the same. The catalyst substance is added to the catalyst substance adding area 9, and the same area is heated whereby crystal growth is effected from the catalyst substance adding area 9 toward the crystal growth area 10. In this case, the unnecessary crystal grains are grown in the crystal grain boundary guiding areas 11 arranged at both sides of the route 12, and the same crystal grains are driven into the crystal grain boundary guiding areas 11 whereby only the single crystal grain can be grown in the crystal growth area 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、基板上に形成され
る半導体の作製方法および半導体装置に関し、さらに詳
細には、基板上に非晶質珪素膜を形成し、この非晶質珪
素膜に珪素の結晶化を助長する触媒物質を添加して作製
される結晶性珪素膜の作製方法およびそれを用いた半導
体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor formed on a substrate and a semiconductor device. More specifically, an amorphous silicon film is formed on the substrate and the amorphous silicon film is formed. The present invention relates to a method for producing a crystalline silicon film produced by adding a catalyst substance that promotes crystallization of silicon, and a semiconductor device using the same.

【0002】[0002]

【従来の技術】近年、薄膜トランジスタ(TFT:Thin
film Transistor)に代表される薄膜半導体素子が注目
されている。薄膜半導体素子は、絶縁表面を有する基板
上にCVD(Chemical Vapor Deposition)法などで形
成された数十nm〜数百nmの半導体薄膜を活性層とし
て用いる。前記半導体薄膜を活性層として用いることに
よって、絶縁ゲート型電界効果半導体装置やダイオード
などを構成することができる。半導体薄膜を用いた応用
技術の1つとして、アクティブマトリクス型の液晶表示
装置が知られている。アクティブマトリクス型の液晶表
示装置では、マトリクス状に配置された数十万個以上の
画素電極のそれぞれに、1つ以上のTFTを配置するこ
とによって、画素電極に供給する電荷をTFTによって
制御している。
2. Description of the Related Art In recent years, thin film transistors (TFTs)
Attention is focused on thin film semiconductor devices represented by film transistors. A thin film semiconductor element uses a semiconductor thin film of several tens nm to several hundreds nm formed as an active layer on a substrate having an insulating surface by a CVD (Chemical Vapor Deposition) method or the like. By using the semiconductor thin film as an active layer, an insulated gate field effect semiconductor device, a diode or the like can be formed. An active matrix liquid crystal display device is known as one of application techniques using a semiconductor thin film. In an active matrix type liquid crystal display device, one or more TFTs are arranged in each of several hundreds of thousands or more pixel electrodes arranged in a matrix to control electric charges supplied to the pixel electrodes by the TFTs. There is.

【0003】TFTの活性層に用いられる半導体薄膜と
しては、成膜が容易な非晶質珪素膜が挙げられる。しか
しながら、非晶質珪素膜は電気的特性が低いという問題
がある。TFTの電気的特性を向上させるためには、活
性層に結晶性を有する珪素薄膜を利用すればよい。結晶
性を有する珪素膜は、多結晶珪素および微結晶珪素など
と称されている。結晶性を有する珪素膜は、まず非晶質
珪素膜を形成し、その非晶質珪素膜に結晶化を助長する
触媒物質を添加し、しかる後に加熱を行なうことで作製
することができる。
An example of a semiconductor thin film used for the active layer of a TFT is an amorphous silicon film which can be easily formed. However, there is a problem that the amorphous silicon film has low electrical characteristics. In order to improve the electrical characteristics of the TFT, a silicon thin film having crystallinity may be used for the active layer. The crystalline silicon film is called polycrystalline silicon, microcrystalline silicon, or the like. The crystalline silicon film can be manufactured by first forming an amorphous silicon film, adding a catalyst substance that promotes crystallization to the amorphous silicon film, and then performing heating.

【0004】非晶質珪素膜から結晶性珪素膜を作製する
従来技術は、特開平7−130652号公報に開示され
ている。上記特開平7−130652号公報に開示され
る従来の技術では、まず、基板上に形成した非晶質珪素
膜の表面に触媒物質導入マスクを形成し、前記マスクの
表面に珪素の結晶化を助長する触媒物質を含む溶液を塗
布し、マスク貫通孔から触媒物質を添加する。その後、
アニールすることによって、非晶質珪素を結晶化させて
結晶性珪素膜を得ている。
A conventional technique for producing a crystalline silicon film from an amorphous silicon film is disclosed in Japanese Patent Application Laid-Open No. 7-130652. In the conventional technique disclosed in Japanese Patent Application Laid-Open No. 7-130652, first, a catalyst substance introduction mask is formed on the surface of an amorphous silicon film formed on a substrate, and silicon is crystallized on the surface of the mask. A solution containing a promoting catalytic material is applied, and the catalytic material is added through the mask through hole. afterwards,
By annealing, the amorphous silicon is crystallized to obtain a crystalline silicon film.

【0005】[0005]

【発明が解決しようとする課題】図5は、非晶質珪素膜
に触媒物質を添加することによって結晶化を行なう従来
技術で作製された結晶性珪素膜について、隣接点間の結
晶方位のずれの大きさによって分類された粒界の分布を
示す図である。図5に示す黒太線が結晶方位のずれの大
きい大傾角粒界1であり、大傾角粒界1に囲まれた部分
が1つのドメインになっている。また、ドメイン内に見
られる黒細線が結晶方位のずれの小さい小傾角粒界2を
示している。また、図5の小さなドメインが無数に集ま
った帯状の領域が触媒を添加した触媒物質添加領域3で
ある。図5から判るように、珪素は触媒物質添加領域3
から周辺部へと結晶成長している。
FIG. 5 shows a deviation of crystal orientation between adjacent points in a crystalline silicon film manufactured by a conventional technique in which a catalyst substance is added to an amorphous silicon film for crystallization. It is a figure which shows the distribution of the grain boundary classified according to the size of. The thick black line shown in FIG. 5 is the large-angle grain boundary 1 with a large deviation of the crystal orientation, and the part surrounded by the large-angle grain boundary 1 is one domain. Further, the black thin lines seen in the domain indicate the small-angle grain boundaries 2 with a small deviation of the crystal orientation. In addition, a belt-shaped region in which a number of small domains are gathered in FIG. As can be seen from FIG. 5, silicon is used as the catalyst material addition region 3
The crystal has grown from the surrounding area.

【0006】このように、従来技術によって作製された
結晶性珪素膜では大傾角粒界1が多数存在し、また、大
傾角粒界1の位置を制御することができない。したがっ
て、このような結晶性珪素膜を用いてTFTを作製した
場合、チャネル領域に大傾角粒界1が入り込む可能性が
大きい。チャネル領域に大傾角粒界1が入り込むと、T
FTの電気的特性が悪化し、また特性にばらつきが生じ
る原因となる。
As described above, the crystalline silicon film produced by the conventional technique has a large number of large-angle boundaries 1 and the position of the large-angle boundaries 1 cannot be controlled. Therefore, when a TFT is manufactured using such a crystalline silicon film, there is a high possibility that the high-angle grain boundary 1 will enter the channel region. When the large tilt grain boundary 1 enters the channel region, T
This may deteriorate the electrical characteristics of the FT and cause variations in the characteristics.

【0007】薄膜半導体素子の高密度化および電気特性
の安定化のためには結晶性のよい半導体薄膜を得ること
が不可欠である。中でも、単一ドメインを形成している
結晶は非常に結晶性がよいので、高い特性が要求される
薄膜半導体素子にも利用することができる。
It is indispensable to obtain a semiconductor thin film having good crystallinity in order to increase the density of the thin film semiconductor device and stabilize the electric characteristics. Among them, the crystal forming a single domain has very good crystallinity, and therefore, it can be used for a thin film semiconductor element that requires high characteristics.

【0008】ここで、単一ドメインとは、結晶中で結晶
方位のずれが5度以上である大傾角粒界が存在しない領
域のことをいう。ただし、単一ドメイン内には、結晶方
位のずれが数度以下である小傾界粒界は存在している。
よって、TFTなどの薄膜半導体素子の電気的特性を向
上させるためには、活性層に用いる珪素膜の結晶性が単
一ドメインになるように結晶成長を行なえばよい。
Here, the single domain refers to a region in the crystal in which a large tilt angle grain boundary having a crystal orientation deviation of 5 degrees or more does not exist. However, within a single domain, there exists a small-boundary grain boundary with a crystal orientation shift of several degrees or less.
Therefore, in order to improve the electrical characteristics of a thin film semiconductor element such as a TFT, crystal growth may be performed so that the crystallinity of the silicon film used for the active layer becomes a single domain.

【0009】しかしながら、特開平7−130652号
公報に開示される従来技術では、触媒物質の添加領域に
おいて無数の結晶核が発生し、そのまま成長領域に成長
するため、単一ドメインを成長させることができない。
However, according to the conventional technique disclosed in Japanese Patent Laid-Open No. 7-130652, a large number of crystal nuclei are generated in the catalyst substance addition region and grow in the growth region as they are, so that a single domain can be grown. Can not.

【0010】本発明の目的は、非晶質珪素膜から性能、
信頼性および安定性に優れた結晶性珪素膜を作製する半
導体作製方法および半導体装置を提供することである。
The object of the present invention is to improve the performance from an amorphous silicon film,
It is an object of the present invention to provide a semiconductor manufacturing method and a semiconductor device for manufacturing a crystalline silicon film having excellent reliability and stability.

【0011】[0011]

【課題を解決するための手段】本発明は、基板上に積層
した島状の非晶質珪素膜の表面の一部に珪素の結晶化を
助長する触媒物質を添加し、エネルギーを印加すること
によって、前記触媒物質が添加された触媒物質添加領域
から触媒物質を添加していない結晶成長領域へ結晶成長
を行なうことで結晶性珪素膜を作製する半導体作製方法
であって、前記島状の非晶質珪素膜は、前記触媒物質添
加領域と結晶成長領域との間に、不要な結晶粒を成長さ
せる結晶粒界誘導領域を両側に有する経路が配置される
形状を有し、結晶成長領域に単一の結晶粒のみを成長さ
せることを特徴とする半導体作製方法である。
According to the present invention, a catalyst substance which promotes crystallization of silicon is added to a part of the surface of an island-shaped amorphous silicon film laminated on a substrate, and energy is applied. A semiconductor manufacturing method for forming a crystalline silicon film by performing crystal growth from a catalyst substance-added region to which the catalyst substance has been added to a crystal growth region to which the catalyst substance has not been added. The crystalline silicon film has a shape in which a path having crystal grain boundary induction regions for growing unnecessary crystal grains on both sides is arranged between the catalyst substance addition region and the crystal growth region, and It is a semiconductor manufacturing method characterized by growing only a single crystal grain.

【0012】本発明に従えば、基板上に積層される島状
の非晶質珪素膜は、触媒物質が添加される触媒物質添加
領域と、単一の結晶粒が成長する結晶成長領域とを有
し、前記触媒物質添加領域および結晶成長領域との間に
不要な結晶粒を成長させる結晶粒界誘導領域を両側に有
する経路が配置される形状とする。前記触媒物質添加領
域に触媒物質を添加し、エネルギーを印加、たとえば加
熱することによって島状の非晶質珪素膜は結晶化する。
非晶質珪素膜は、触媒物質添加領域から結晶化し始め、
触媒物質添加領域から結晶成長領域に向かって結晶成長
が行なわれる。このとき、経路の両側に配置される結晶
粒界誘導領域に不要な結晶粒を成長させて結晶粒界誘導
領域に不要な結晶粒を追い込むことで、1つのドメイン
からなる結晶粒のみが結晶成長領域に成長する。したが
って、結晶成長領域に単一の結晶粒のみを成長させるこ
とができる。前記結晶成長領域を、たとえば半導体装置
の活性領域に用いることによって、電気的特性に優れた
半導体装置を作製することが可能となる。
According to the present invention, the island-shaped amorphous silicon film laminated on the substrate has a catalyst substance addition region to which a catalyst substance is added and a crystal growth region in which a single crystal grain grows. A path having a crystal grain boundary induction region for growing unnecessary crystal grains on both sides is provided between the catalyst substance addition region and the crystal growth region. The island-shaped amorphous silicon film is crystallized by adding a catalyst substance to the catalyst substance adding region and applying energy, for example, heating.
The amorphous silicon film begins to crystallize from the catalyst substance added region,
Crystal growth is performed from the catalyst substance addition region toward the crystal growth region. At this time, by growing unnecessary crystal grains in the crystal grain boundary induction regions arranged on both sides of the path and driving the unnecessary crystal grains into the crystal grain boundary induction regions, only the crystal grains having one domain grow. Grow in the area. Therefore, only a single crystal grain can be grown in the crystal growth region. By using the crystal growth region as, for example, an active region of a semiconductor device, a semiconductor device having excellent electric characteristics can be manufactured.

【0013】また本発明は、前記触媒物質添加領域と結
晶粒界誘導領域との間の距離が1μm以上、20μm以
下であることを特徴とする。
Further, the present invention is characterized in that the distance between the catalyst substance addition region and the crystal grain boundary induction region is 1 μm or more and 20 μm or less.

【0014】触媒物質添加領域と結晶粒界誘導領域との
間の距離が1μmよりも小さいと、経路の両側に配置さ
れる結晶粒界誘導領域への入り口を過ぎてもなお複数の
ドメインが結晶成長領域に向かって成長し、結晶成長領
域に単一ドメインが成長しない。また、触媒物質添加領
域と結晶粒界誘導領域との間の距離が20μmよりも大
きいと、経路の両端に配置される結晶粒界誘導領域への
入り口に到達する頃には複数のドメインがある程度大き
く成長しているので、結晶粒界誘導領域に不要な結晶粒
を完全に追い込むことができなくなり、結晶成長領域に
単一ドメインが成長しない。本発明に従えば、前記触媒
物質添加領域と結晶粒界誘導領域との間の距離が1μm
以上、20μm以下であるので、結晶成長領域に単一の
結晶粒のみを成長させることができる。
When the distance between the catalyst substance addition region and the crystal grain boundary induction region is smaller than 1 μm, a plurality of domains are crystallized even after passing through the entrances to the crystal grain boundary induction regions arranged on both sides of the path. It grows toward the growth region and no single domain grows in the crystal growth region. Further, if the distance between the catalyst substance addition region and the crystal grain boundary induction region is larger than 20 μm, a plurality of domains will be formed to some extent by the time when reaching the entrances to the crystal grain boundary induction regions arranged at both ends of the path. Since the growth is large, it becomes impossible to completely drive unnecessary crystal grains into the crystal grain boundary induction region, and a single domain does not grow in the crystal growth region. According to the present invention, the distance between the catalyst substance addition region and the grain boundary induction region is 1 μm.
As described above, since it is 20 μm or less, only a single crystal grain can be grown in the crystal growth region.

【0015】また本発明は、結晶粒界誘導領域の面積が
それぞれ10μm2以上、1000μm2以下であること
を特徴とする。
Further, the present invention is characterized in that the areas of the crystal grain boundary inducing regions are 10 μm 2 or more and 1000 μm 2 or less, respectively.

【0016】結晶粒界誘導領域の面積が10μm2より
も小さいと、結晶粒界誘導領域に追い込まれたドメイン
は結晶粒界誘導領域に完全に入り込まずに、そのまま結
晶成長領域に成長するので、結晶成長領域に単一ドメイ
ンが成長しない。また、結晶粒界誘導領域の面積が10
00μm2よりも大きいと、結晶を成長させる領域が大
きくなりすぎて、結晶成長領域に到達する前に結晶成長
が止まってしまう。本発明に従えば、経路の両側に配置
される結晶粒界誘導領域の面積がそれぞれ10μm2
上、1000μm2以下であるので、結晶成長領域に単
一の結晶粒のみを成長させることができる。
When the area of the crystal grain boundary induction region is smaller than 10 μm 2, the domain driven into the crystal grain boundary induction region does not completely enter the crystal grain boundary induction region but grows as it is in the crystal growth region. No single domain grows in the crystal growth region. Further, the area of the crystal grain boundary induction region is 10
If it is larger than 00 μm 2, the region for growing the crystal becomes too large and the crystal growth stops before reaching the crystal growth region. According to the present invention, since the areas of the crystal grain boundary inducing regions arranged on both sides of the path are 10 μm 2 or more and 1000 μm 2 or less, respectively, it is possible to grow only a single crystal grain in the crystal growth region.

【0017】また本発明は、前記結晶性珪素膜の膜厚が
10nm以上、200nm以下であることを特徴とす
る。
Further, the present invention is characterized in that the film thickness of the crystalline silicon film is 10 nm or more and 200 nm or less.

【0018】結晶性珪素膜の膜厚が10nmよりも薄い
と、成膜不良などの問題が起こりやすくなる。また、結
晶性珪素膜の膜厚が200nmよりも厚いと、結晶成長
領域に単一ドメインが形成されにくくなる。本発明に従
えば、結晶性珪素膜の膜厚が10nm以上、200nm
以下であるので、成膜不良などの問題が発生せず、結晶
成長領域に単一の結晶粒のみを成長させることができ
る。
If the thickness of the crystalline silicon film is less than 10 nm, problems such as defective film formation easily occur. Further, if the thickness of the crystalline silicon film is thicker than 200 nm, it becomes difficult to form a single domain in the crystal growth region. According to the invention, the thickness of the crystalline silicon film is 10 nm or more and 200 nm or more.
Because of the following, it is possible to grow only a single crystal grain in the crystal growth region without causing a problem such as defective film formation.

【0019】また本発明は、前記触媒物質としてFe,
Co,Ni,Ge,Ru,Rh,Pd,Os,Ir,P
t,Cu,Auから選ばれた少なくとも1種の元素を用
いることを特徴とする。
In the present invention, the catalytic substance is Fe,
Co, Ni, Ge, Ru, Rh, Pd, Os, Ir, P
At least one element selected from t, Cu, and Au is used.

【0020】本発明に従えば、珪素膜の結晶化を助長す
る触媒物質としてFe,Co,Ni,Ge,Ru,R
h,Pd,Os,Ir,Pt,Cu,Auから選ばれた
少なくとも1種の元素を用いることができる。
According to the present invention, Fe, Co, Ni, Ge, Ru and R are used as the catalyst substance for promoting the crystallization of the silicon film.
At least one element selected from h, Pd, Os, Ir, Pt, Cu, and Au can be used.

【0021】また本発明は、結晶性珪素膜には、Fe,
Co,Ni,Ge,Ru,Rh,Pd,Os,Ir,P
t,Cu,Auから選ばれた少なくとも1種の元素が1
×1016/cm3以上、5×1019/cm3以下の濃度で
含まれることを特徴とする。
According to the present invention, the crystalline silicon film contains Fe,
Co, Ni, Ge, Ru, Rh, Pd, Os, Ir, P
At least one element selected from t, Cu, and Au is 1
It is characterized in that it is contained in a concentration of not less than × 10 16 / cm 3 and not more than 5 × 10 19 / cm 3 .

【0022】結晶成長領域中に存在する触媒物質である
元素が1×1016/cm3よりも少ない場合、非晶質珪
素膜の結晶化が起こりにくくなる。また、結晶成長領域
中に存在する触媒物質である元素が5×1019/cm3
よりも多い場合、結晶性珪素膜に残留する触媒物質が過
大となって、結晶化後に半導体装置の電気的特性の悪化
を防止するために行なわれる触媒を除去する触媒除去工
程が困難になる。本発明に従えば、結晶性珪素膜中には
触媒物質である元素が1×1016/cm3以上、5×1
19/cm3以下の濃度で含まれるので、結晶化が起こ
りやすく、また結晶化後に行なわれる触媒の除去を容易
に行なうことができる。
When the amount of the catalytic substance element present in the crystal growth region is less than 1 × 10 16 / cm 3 , the amorphous silicon film is less likely to be crystallized. In addition, when the element that is the catalyst substance existing in the crystal growth region is 5 × 10 19 / cm 3
If the amount is larger than that, the amount of the catalytic substance remaining on the crystalline silicon film becomes excessive, which makes it difficult to perform the catalyst removal step of removing the catalyst for preventing deterioration of the electrical characteristics of the semiconductor device after crystallization. According to the present invention, an element which is a catalytic substance is 1 × 10 16 / cm 3 or more and 5 × 1 or more in the crystalline silicon film.
Since it is contained at a concentration of 0 19 / cm 3 or less, crystallization is likely to occur, and the catalyst removed after crystallization can be easily removed.

【0023】また本発明は、触媒物質添加領域には、F
e,Co,Ni,Ge,Ru,Rh,Pd,Os,I
r,Pt,Cu,Auから選ばれた少なくとも1種の元
素が0.1nm以上、10nm以下の膜厚で成膜される
ことを特徴とする。
In the present invention, the catalyst substance addition area is provided with F
e, Co, Ni, Ge, Ru, Rh, Pd, Os, I
It is characterized in that at least one element selected from r, Pt, Cu, and Au is formed in a film thickness of 0.1 nm or more and 10 nm or less.

【0024】触媒物質添加領域に成膜される触媒物質で
ある元素が0.1nmよりも薄い場合、非晶質珪素に拡
散する触媒物質の量が不足し、結晶成長領域に単一ドメ
インが形成されない。また、触媒物質添加領域に成膜さ
れる触媒物質である元素が10nmよりも厚い場合、触
媒物質の量が過大となり、結晶性窒素膜に触媒物質が残
留してしまう。本発明に従えば、触媒物質添加領域には
触媒物質である元素が0.1nm以上、10nm以下の
膜厚で成膜されるので、結晶成長領域に単一の結晶粒を
成長させることができ、また結晶性窒素膜への触媒物質
の残留を防止することができる。
When the element which is the catalyst substance formed in the catalyst substance addition region is thinner than 0.1 nm, the amount of the catalyst substance diffused into the amorphous silicon is insufficient and a single domain is formed in the crystal growth region. Not done. Further, when the element which is the catalyst substance formed in the catalyst substance addition region is thicker than 10 nm, the amount of the catalyst substance becomes excessive and the catalyst substance remains on the crystalline nitrogen film. According to the invention, since the element which is the catalyst substance is formed in the catalyst substance addition region in a film thickness of 0.1 nm or more and 10 nm or less, a single crystal grain can be grown in the crystal growth region. Moreover, it is possible to prevent the catalytic substance from remaining on the crystalline nitrogen film.

【0025】また本発明は、550℃以上、650℃以
下の温度で加熱処理を行なうことによって、エネルギー
の印加を行なう特徴とする。
The present invention is also characterized in that energy is applied by performing heat treatment at a temperature of 550 ° C. or higher and 650 ° C. or lower.

【0026】本発明に従えば、加熱処理の温度が550
℃よりも低いと、非晶質珪素膜の結晶化が急激に進行し
難くなり、結晶化に時間がかかる。また、加熱処理の温
度が650℃よりも高いと、触媒物質を添加していない
領域においても非晶質珪素膜の結晶化が始まって結晶性
珪素膜の結晶粒が微小になってしまい、結晶成長領域に
単一の結晶粒を成長させることができない。550℃以
上、650℃以下の温度で加熱処理を行なうことによっ
て、エネルギーの印加を行なうので、適度な時間で結晶
を成長させることができるとともに、結晶成長領域に単
一の結晶粒を成長させることができる。
According to the present invention, the temperature of the heat treatment is 550.
If the temperature is lower than ° C, it becomes difficult for the amorphous silicon film to crystallize rapidly, and it takes time to crystallize. Further, if the temperature of the heat treatment is higher than 650 ° C., the crystallization of the amorphous silicon film starts even in the region to which the catalyst substance is not added, and the crystal grains of the crystalline silicon film become minute, resulting in crystallization. It is not possible to grow a single crystal grain in the growth region. Since energy is applied by performing heat treatment at a temperature of 550 ° C. or higher and 650 ° C. or lower, it is possible to grow a crystal in an appropriate time and to grow a single crystal grain in a crystal growth region. You can

【0027】また本発明は、触媒物質の添加を行なう前
に、触媒物質添加領域を除く非晶質珪素膜の表面を膜厚
が50nm以上の窒化珪素膜、酸化珪素膜、炭化珪素膜
のうち少なくとも1種類で覆うことを特徴とする。
In addition, according to the present invention, before the addition of the catalyst substance, the surface of the amorphous silicon film excluding the region where the catalyst substance is added is selected from among silicon nitride film, silicon oxide film and silicon carbide film having a film thickness of 50 nm or more. It is characterized by covering with at least one kind.

【0028】本発明に従えば、触媒物質の添加を行なう
前に、触媒物質添加領域を除く非晶質珪素膜の表面を膜
厚が50nm以上の窒化珪素膜、酸化珪素膜、炭化珪素
膜のうち少なくとも1種類で覆うので、触媒物質添加領
域にのみ触媒物質を添加することができる。
According to the present invention, before the addition of the catalyst substance, the surface of the amorphous silicon film excluding the catalyst substance addition region is formed into a silicon nitride film, a silicon oxide film or a silicon carbide film having a thickness of 50 nm or more. Since at least one of them is covered, the catalyst substance can be added only to the catalyst substance addition region.

【0029】また本発明は、基板上に形成される結晶性
珪素膜を活性領域として構成される半導体装置であっ
て、島状に非晶質珪素膜が積層された基板にエネルギー
を印加し、前記島状の非晶質珪素膜の表面の一部に結晶
化を助長する触媒物質を添加した触媒物質添加領域か
ら、不要な結晶粒を成長させるための結晶粒界誘導領域
を経て、単一の結晶粒のみを成長させる結晶成長領域へ
結晶化させた前記結晶成長領域を活性領域として用いる
ことを特徴とする半導体装置である。
Further, the present invention is a semiconductor device in which a crystalline silicon film formed on a substrate is used as an active region, and energy is applied to a substrate in which an amorphous silicon film is laminated in an island shape, From the catalyst substance-added region where a catalyst substance that promotes crystallization is added to a part of the surface of the island-shaped amorphous silicon film, through a grain boundary induction region for growing unnecessary crystal grains, In the semiconductor device, the crystal growth region crystallized into a crystal growth region for growing only the crystal grains is used as an active region.

【0030】本発明に従えば、触媒を添加する触媒物質
添加領域、不要な結晶粒を成長させる結晶粒界誘導領域
および単一の結晶粒のみが成長する結晶成長領域からな
る島状の非晶質珪素膜が形成された基板にエネルギーを
印加し、該島状の非晶質珪素膜の結晶化を助長する触媒
物質を添加した触媒物質添加領域から、不要な結晶粒を
成長させるための結晶粒界誘導領域を経て、単一の結晶
粒のみを形成させる結晶成長領域へ結晶化させた前記結
晶成長領域を活性領域として半導体装置を構成するの
で、電気的特性の優れた半導体装置を作製することが可
能となる。
According to the present invention, an island-shaped amorphous structure composed of a catalyst substance addition region to which a catalyst is added, a crystal grain boundary induction region for growing unnecessary crystal grains, and a crystal growth region for growing only a single crystal grain. A crystal for growing unnecessary crystal grains from a catalyst substance-added region to which energy is applied to the substrate on which the crystalline silicon film is formed and a catalyst substance that promotes crystallization of the island-shaped amorphous silicon film is added. Since the semiconductor device is configured with the crystal growth region crystallized into a crystal growth region for forming only a single crystal grain through the grain boundary induction region as an active region, a semiconductor device having excellent electrical characteristics is manufactured. It becomes possible.

【0031】また本発明は、前記触媒物質添加領域と結
晶粒界誘導領域との間の距離が1μm以上、20μm以
下であることを特徴とする。
Further, the present invention is characterized in that the distance between the catalyst substance addition region and the crystal grain boundary induction region is 1 μm or more and 20 μm or less.

【0032】本発明に従えば、触媒物質添加領域と結晶
粒界誘導領域との間の距離が1μm以上、20μm以下
とするので、不要な結晶粒を結晶粒界誘導領域に成長さ
せることができ、結晶成長領域に単一の結晶粒を成長さ
せることができる。
According to the present invention, since the distance between the catalyst substance added region and the crystal grain boundary induction region is 1 μm or more and 20 μm or less, unnecessary crystal grains can be grown in the crystal grain boundary induction region. , A single crystal grain can be grown in the crystal growth region.

【0033】また本発明は、前記結晶粒界誘導領域の1
つの面積が10μm2以上、1000μm2以下であるこ
とを特徴とする。
The present invention also relates to one of the above-mentioned grain boundary induction regions.
One area is 10 μm 2 or more and 1000 μm 2 or less.

【0034】本発明に従えば、結晶粒界誘導領域の1つ
の面積が10μm2以上、1000μm2以下であるの
で、結晶成長領域に単一の結晶粒のみを成長させること
ができる。
According to the present invention, since one area of the crystal grain boundary inducing region is 10 μm 2 or more and 1000 μm 2 or less, only a single crystal grain can be grown in the crystal growth region.

【0035】また本発明は、前記結晶性珪素膜の膜厚が
10nm以上、200nm以下であることを特徴とす
る。
Further, the present invention is characterized in that the thickness of the crystalline silicon film is 10 nm or more and 200 nm or less.

【0036】本発明に従えば、結晶性珪素膜の膜厚が1
0nm以上、200nm以下とするので、成膜不良がな
く、結晶成長領域に単一の結晶粒が形成しやすい。
According to the present invention, the thickness of the crystalline silicon film is 1
Since the thickness is 0 nm or more and 200 nm or less, there is no film formation defect and a single crystal grain is easily formed in the crystal growth region.

【0037】また本発明は、結晶性珪素膜中には、F
e,Co,Ni,Ge,Ru,Rh,Pd,Os,I
r,Pt,Cu,Auから選ばれた少なくとも1種の元
素が1×1016/cm3以上、5×1019/cm3以下の
濃度で含まれることを特徴とする。
Further, according to the present invention, in the crystalline silicon film, F
e, Co, Ni, Ge, Ru, Rh, Pd, Os, I
At least one element selected from r, Pt, Cu, and Au is contained at a concentration of 1 × 10 16 / cm 3 or more and 5 × 10 19 / cm 3 or less.

【0038】本発明に従えば、結晶性珪素膜中には触媒
物質である元素が1×1016/cm 3以上、5×1019
/cm3以下の濃度で含まれるので、結晶化が容易であ
り、触媒物質の除去を容易に行なうことができる。
According to the invention, a catalyst is present in the crystalline silicon film.
The element that is a substance is 1 × 1016/ Cm 3Above, 5 × 1019
/ Cm3Since it is contained in the following concentrations, it is easy to crystallize.
Therefore, the catalyst substance can be easily removed.

【0039】[0039]

【発明の実施の形態】図1は、本発明の実施の一形態の
半導体作製方法の手順を示す図である。図1(a)〜図
1(e)は半導体作製方法の各工程における断面図を示
し、図1(a)から図1(e)へと順に工程が進む。
FIG. 1 is a diagram showing a procedure of a semiconductor manufacturing method according to an embodiment of the present invention. 1A to 1E are cross-sectional views in each step of the semiconductor manufacturing method, and the steps sequentially proceed from FIG. 1A to FIG.

【0040】まず、図1(a)に示すように、基板4の
一方側表面上にCVD法などによって非晶質珪素膜5を
成膜する。前記基板4には、石英基板またはガラス基板
などの絶縁性の表面を有する基板、あるいは表面に、絶
縁膜であるSiO2膜またはSiN膜を形成したシリコ
ンウェハが用いられる。
First, as shown in FIG. 1A, an amorphous silicon film 5 is formed on one surface of the substrate 4 by the CVD method or the like. As the substrate 4, a substrate having an insulative surface such as a quartz substrate or a glass substrate, or a silicon wafer having an SiO 2 film or SiN film as an insulating film formed on the surface is used.

【0041】次に図1(b)に示すように、非晶質珪素
膜5を覆うようにCVD法などによってSiO2膜6を
成膜する。そして、SiO2膜6の上にレジストを塗布
し、露光および現像を行なってフォトリソグラフィ工程
を行なった後、ドライエッチングを行なうことによっ
て、図1(c)に示すように、島状の非晶質珪素膜5と
この上に積層されるSiO2膜6を形成する。次に図1
(d)に示すように、非晶質珪素膜5上のSiO2膜6
を全面除去する。図2は、図1(d)を基板4の一方側
から見た平面図である。非晶質珪素膜5は、図2に示す
ように十字型となるように形成される。非晶質珪素膜5
は、触媒物質が添加される触媒物質添加領域9、単一の
結晶粒が成長する結晶成長領域10、不要な結晶粒が成
長する結晶粒界誘導領域11および経路12を有する。
触媒物質添加領域9、経路12および結晶成長領域10
が直線状に配列し、一対の結晶粒界誘導領域11が経路
12の両側から測方に突出して設けられている。
Next, as shown in FIG. 1B, a SiO 2 film 6 is formed by a CVD method or the like so as to cover the amorphous silicon film 5. Then, a resist is applied on the SiO 2 film 6, exposed and developed, a photolithography process is performed, and then dry etching is performed, so that an island-shaped amorphous film is formed as shown in FIG. 1C. A silicon film 5 and a SiO 2 film 6 laminated thereon are formed. Next in FIG.
As shown in (d), the SiO 2 film 6 on the amorphous silicon film 5 is formed.
Are completely removed. FIG. 2 is a plan view of FIG. 1D viewed from one side of the substrate 4. The amorphous silicon film 5 is formed in a cross shape as shown in FIG. Amorphous silicon film 5
Has a catalyst substance addition region 9 to which a catalyst substance is added, a crystal growth region 10 in which a single crystal grain grows, a grain boundary induction region 11 in which unnecessary crystal grains grow, and a path 12.
Catalyst substance addition region 9, path 12 and crystal growth region 10
Are arranged in a straight line, and a pair of crystal grain boundary induction regions 11 are provided so as to project in a square direction from both sides of the path 12.

【0042】次に、図1(e)に示すように、非晶質珪
素膜5上および基板4の全体にCVD法などを用いてマ
スク層13を形成する。マスク層13としては、膜厚が
50nm以上の窒化珪素膜、酸化珪素膜、炭化珪素膜の
うち少なくとも1種類を用いる。次に、非晶質珪素膜5
の一部である触媒物質添加領域9が外部に露出するよう
に、フォトリソグラフィ工程およびドライエッチングを
行なう。これによって、図3に示すように非晶質珪素膜
5の触媒物質添加領域9上のマスク層13に窓14を形
成する。このマスク層13に形成された窓14から、非
晶質珪素膜5の触媒物質添加領域9が外部に露出する。
Next, as shown in FIG. 1E, a mask layer 13 is formed on the amorphous silicon film 5 and the entire substrate 4 by the CVD method or the like. As the mask layer 13, at least one of a silicon nitride film, a silicon oxide film, and a silicon carbide film having a film thickness of 50 nm or more is used. Next, the amorphous silicon film 5
A photolithography process and dry etching are performed so that the catalyst substance-added region 9, which is a part of, is exposed to the outside. As a result, a window 14 is formed in the mask layer 13 on the catalyst substance added region 9 of the amorphous silicon film 5 as shown in FIG. The catalyst substance-added region 9 of the amorphous silicon film 5 is exposed to the outside through the window 14 formed in the mask layer 13.

【0043】次に、マスク層13の上および非晶質珪素
膜5の露出部である触媒物質添加領域9上に触媒物質で
あるFe,Co,Ni,Ge,Ru,Rh,Pd,O
s,Ir,Pt,Cu,Auから選ばれた少なくとも1
種の元素を添加する。触媒物質は触媒物質添加領域9に
スパッタ法を用いて触媒物質膜を成膜する、蒸着法を用
いて触媒物質を成膜する、あるいは触媒物質溶液を塗布
することによって添加することができる。触媒物質添加
領域9に触媒を添加した後に加熱を行なう。これによっ
て、触媒物質を添加した触媒物質添加領域9で核発生が
起こり、触媒物質が非晶質珪素膜5内の触媒物質が添加
されていない領域に拡散して結晶化が行なわれ、結晶性
珪素膜が作製される。
Next, Fe, Co, Ni, Ge, Ru, Rh, Pd, O, which are catalytic substances, are formed on the mask layer 13 and on the catalytic substance added region 9 which is the exposed portion of the amorphous silicon film 5.
at least 1 selected from s, Ir, Pt, Cu, Au
Add seed elements. The catalyst substance can be added to the catalyst substance addition region 9 by forming a catalyst substance film by a sputtering method, forming a catalyst substance film by an evaporation method, or applying a catalyst substance solution. Heating is performed after the catalyst is added to the catalyst substance addition region 9. As a result, nucleation occurs in the catalyst substance-added region 9 to which the catalyst substance has been added, and the catalyst substance diffuses into the region of the amorphous silicon film 5 to which the catalyst substance has not been added to cause crystallization, resulting in crystallinity. A silicon film is produced.

【0044】図4は、非晶質珪素膜5が結晶化した結晶
性珪素膜15の結晶粒の様子を示す平面図である。非晶
質珪素膜5では、触媒物質が添加された触媒物質添加領
域9に結晶核16が発生し、結晶成長領域10に向かっ
て結晶が成長する。結晶成長領域10と触媒物質添加領
域9との間に配置された経路12の両側に結晶粒界誘導
領域11を設けることによって、触媒物質添加領域9か
ら触媒を添加していない領域へと成長する結晶粒のうち
経路12の両側に近い部分に成長してきた結晶粒17
は、結晶成長領域10へ成長しないで、経路12に設け
た結晶粒界誘導領域11に向かって成長し、結晶粒界誘
導領域11の端に追いやられて成長が止まる。一方、経
路12のほぼ中央に成長する結晶粒は、結晶成長領域1
0へと成長していく。本出願人らの研究によって、結晶
成長領域10へ結晶粒が到達するときには、最終的に結
晶粒が1つに選択されており、大傾角粒界のない単一な
結晶粒(単一ドメイン)18が結晶成長領域10に形成
されることが見出された。結晶性珪素膜中には、触媒物
質である元素が1×1016/cm3以上、5×1019
cm3以下の濃度で含まれる。結晶成長領域10中に存
在する触媒である元素が1×1016/cm3よりも少な
い場合、非晶質珪素膜5の結晶化が起こりにくくなる。
また、非晶質珪素膜5に存在する触媒である元素が5×
1019/cm3よりも多い場合、結晶性珪素膜に残留す
る触媒物質が過大となって、結晶化後に半導体装置の電
気的特性の悪化を防止するために触媒の除去を行なう場
合の工程が困難になる。
FIG. 4 is a plan view showing a state of crystal grains of the crystalline silicon film 15 obtained by crystallizing the amorphous silicon film 5. In the amorphous silicon film 5, crystal nuclei 16 are generated in the catalyst substance addition region 9 to which the catalyst substance is added, and crystals grow toward the crystal growth region 10. By providing the crystal grain boundary inducing regions 11 on both sides of the path 12 arranged between the crystal growth region 10 and the catalyst substance addition region 9, the catalyst substance addition region 9 grows to a region to which no catalyst is added. Crystal grains 17 grown on portions of the crystal grains near both sides of the path 12
Does not grow into the crystal growth region 10 but grows toward the crystal grain boundary induction region 11 provided in the path 12 and is driven to the edge of the crystal grain boundary induction region 11 and stops growing. On the other hand, the crystal grains growing in the approximate center of the path 12 are the crystal growth region 1
It grows to zero. According to the study by the applicants, when the crystal grains reach the crystal growth region 10, one crystal grain is finally selected, and a single crystal grain (single domain) having no large tilt grain boundary It has been found that 18 is formed in the crystal growth region 10. In the crystalline silicon film, the catalytic substance element is 1 × 10 16 / cm 3 or more and 5 × 10 19 / cm 3 or more.
It is contained at a concentration of not more than cm 3 . When the amount of the catalyst element existing in the crystal growth region 10 is less than 1 × 10 16 / cm 3 , the amorphous silicon film 5 is less likely to be crystallized.
Further, if the element which is the catalyst present in the amorphous silicon film 5 is 5 ×
If the amount is more than 10 19 / cm 3 , the amount of the catalytic substance remaining in the crystalline silicon film becomes excessive, and the step of removing the catalyst in order to prevent the deterioration of the electrical characteristics of the semiconductor device after crystallization is required. It will be difficult.

【0045】上述の半導体作製方法によって作製された
結晶性珪素膜は、半導体装置の活性領域として用いる。
結晶性珪素膜を活性領域として半導体装置を作製する場
合には、単一の結晶粒が形成された結晶成長領域10の
みを用いる。つまり、触媒物質添加領域9、結晶粒界誘
導領域11および経路12は、エッチングなどによって
取り除かれる。絶縁膜を形成した基板上に作製した場合
などでは、取り除いた触媒物質添加領域9、結晶粒界誘
導領域11および経路12の痕跡が絶縁膜に縁取られて
残る。また、結晶成長領域10以外の領域を取り除かな
いで、作製した十字型の結晶性珪素膜をそのまま用いて
半導体装置を作製してもよい。
The crystalline silicon film manufactured by the above-described semiconductor manufacturing method is used as an active region of a semiconductor device.
When manufacturing a semiconductor device using a crystalline silicon film as an active region, only the crystal growth region 10 in which a single crystal grain is formed is used. That is, the catalyst substance addition region 9, the crystal grain boundary induction region 11 and the path 12 are removed by etching or the like. In the case where the insulating film is formed on the substrate on which the insulating film is formed, the traces of the removed catalyst substance-added region 9, the crystal grain boundary inducing region 11 and the path 12 are left on the insulating film. Further, the semiconductor device may be manufactured by using the manufactured cross-shaped crystalline silicon film as it is without removing the region other than the crystal growth region 10.

【0046】上述の結晶性珪素膜を用いて作製される半
導体装置としては、たとえばTFTが挙げられる。上述
した半導体作製方法で基板上に島状に多数形成された結
晶性珪素膜が活性領域であるチャネルとなるように、結
晶性珪素膜の上にゲート電極、ソース電極およびドレイ
ン電極を形成することで、プレーナ構造のTFTを作製
することができる。また、基板上にゲート電極および絶
縁膜を形成した後、絶縁膜上に上述した半導体作製方法
によって島状の結晶性珪素膜を形成し、ソース電極およ
びドレイン電極を結晶性珪素膜の上に形成することで、
スタガ構造のTFTの作製が可能である。
As a semiconductor device manufactured using the above crystalline silicon film, for example, a TFT can be cited. Forming a gate electrode, a source electrode, and a drain electrode on the crystalline silicon film so that the crystalline silicon film formed in large numbers in an island shape on the substrate by the above-described semiconductor manufacturing method becomes a channel which is an active region. Thus, a TFT having a planar structure can be manufactured. Further, after forming the gate electrode and the insulating film on the substrate, the island-shaped crystalline silicon film is formed on the insulating film by the above-described semiconductor manufacturing method, and the source electrode and the drain electrode are formed on the crystalline silicon film. by doing,
It is possible to manufacture a TFT having a staggered structure.

【0047】本実施形態では、非晶質珪素膜5の形状を
十字型としているが、非晶質珪素膜5内に触媒物質添加
領域9から結晶成長領域10までの間に設けられ経路1
2の両側に結晶粒界誘導領域11を設けた形状であれ
ば、特に十字型でなくてもよい。
In this embodiment, the shape of the amorphous silicon film 5 is cruciform, but the path 1 provided in the amorphous silicon film 5 from the catalyst substance addition region 9 to the crystal growth region 10 is provided.
The shape is not limited to the cross shape as long as the crystal grain boundary induction regions 11 are provided on both sides of 2.

【0048】以下に本発明の具体的な実施例を説明す
る。 (実施例1)石英基板上に減圧CVD法によってSi2
6ガスを用いて、膜厚が100nmの非晶質珪素膜を
形成する。次に常圧CVD法によってSiH4ガスとO2
ガスとを用いて、膜厚が100nmのSiO2膜を形成
する。次にレジストの塗布を行い、露光、現像のフォト
リソグラフィ工程を行い、さらにドライエッチングを行
なうことによって十字型の非晶質珪素膜を生成する。本
実施例では、非晶質珪素膜の触媒物質添加領域と結晶粒
界誘導領域との間の距離を5μmとする。また、経路の
両側に形成される結晶粒界誘導領域の面積は、それぞれ
100μm2とする。
Specific examples of the present invention will be described below. (Example 1) Si 2 was formed on a quartz substrate by a low pressure CVD method.
An amorphous silicon film having a film thickness of 100 nm is formed using H 6 gas. Next, SiH 4 gas and O 2 are formed by the atmospheric pressure CVD method.
Using a gas, a SiO 2 film having a film thickness of 100 nm is formed. Next, a resist is applied, a photolithography process of exposure and development is performed, and further dry etching is performed to form a cross-shaped amorphous silicon film. In this embodiment, the distance between the catalyst substance added region of the amorphous silicon film and the crystal grain boundary induction region is set to 5 μm. The area of the crystal grain boundary inducing regions formed on both sides of the path is 100 μm 2 .

【0049】この後、SiO2膜を全面除去し、新たに
常圧CVD法によってSiH4ガスとO2ガスとを用い
て、膜厚が200nmのSiO2膜を形成する。このS
iO2膜がマスク層となる。そして、フォトリソグラフ
ィ工程を行なって、SiO2膜の一部を10:1BHF
(バッファードフッ酸)でエッチングを行い、SiO2
膜の一部を開口して窓を形成し、非晶質珪素膜の触媒物
質添加領域を露出させる。
[0049] After this, an SiO 2 film is removed entirely newly by using the SiH 4 gas and O 2 gas by atmospheric pressure CVD method, the film thickness to form a SiO 2 film of 200 nm. This S
The iO 2 film serves as a mask layer. Then, a photolithography process is performed to remove a part of the SiO 2 film by 10: 1 BHF.
Etching with (buffered hydrofluoric acid), SiO 2
A part of the film is opened to form a window to expose the catalyst substance added region of the amorphous silicon film.

【0050】このSiO2膜のマスク層および露出部に
スパッタリング法によって膜厚1nmのニッケル(N
i)薄膜を形成した後、600℃に加熱する。これによ
って、上述した結晶成長領域に単一の結晶粒が形成され
た結晶性珪素膜を作製することができる。
The thickness 1nm nickel by sputtering on the mask layer and the exposed portion of the SiO 2 film (N
i) After forming a thin film, it is heated to 600 ° C. As a result, a crystalline silicon film in which a single crystal grain is formed in the above crystal growth region can be manufactured.

【0051】上記方法によって、単一の結晶粒が形成さ
れた結晶成長領域を活性領域に用いてTFTを作製する
と、電界効果移動度は250cm2/Vs程度、閾値電
圧が1.5V程度であり非常に電気的特性に優れたTF
Tを作製することができた。また、TFT動作時のリー
ク電流の異常な増大が全くみられず、単位W当たり1p
A以下と非常に低い値を示し安定したTFTを作製する
ことができた。
When a TFT is manufactured by using the crystal growth region in which a single crystal grain is formed in the active region by the above method, the field effect mobility is about 250 cm 2 / Vs and the threshold voltage is about 1.5V. TF with excellent electrical characteristics
It was possible to make T. Also, no abnormal increase in leakage current was observed during TFT operation, and 1p per unit W
A stable TFT having a value as low as A or less was able to be manufactured.

【0052】本実施例では、非晶質珪素膜の結晶物質添
加領域にスパッタリング法でニッケル薄膜を成膜した
が、スピンコータで1ppm以上、100ppm以下の
濃度、たとえば20ppmの濃度の酢酸ニッケル溶液を
塗布してもよい。
In this example, a nickel thin film was formed in the crystalline substance-added region of the amorphous silicon film by the sputtering method. You may.

【0053】また本実施例では、触媒物質添加領域と結
晶粒界誘導領域との間の距離を5μmとしたが、この距
離は、1μm以上、20μm以下となる長さであれば、
他の長さでもよい。触媒物質添加領域と結晶粒界誘導領
域との間の距離が1μmよりも小さいと、経路の両側に
配置される結晶粒界誘導領域への入り口を過ぎてもなお
複数のドメインが結晶成長領域に向かって成長し、結晶
成長領域に単一ドメインが成長しない。また、触媒物質
添加領域と結晶粒界誘導領域との間の距離が20μmよ
りも大きいと、結晶粒界誘導領域の入り口に到達する頃
には複数のドメインがある程度大きく成長しているの
で、結晶粒界誘導領域に完全に追い込むことができなく
なり、結晶成長領域に単一ドメインが成長しない。
In the present embodiment, the distance between the catalyst substance added region and the crystal grain boundary inducing region is set to 5 μm, but this distance is 1 μm or more and 20 μm or less,
Other lengths are possible. When the distance between the catalyst substance addition region and the crystal grain boundary induction region is less than 1 μm, a plurality of domains still form the crystal growth region even after passing through the entrances to the crystal grain boundary induction regions arranged on both sides of the path. The single domain does not grow in the crystal growth region. Further, if the distance between the catalyst substance addition region and the crystal grain boundary induction region is larger than 20 μm, a plurality of domains have grown to some extent by the time when reaching the entrance of the crystal grain boundary induction region. It is impossible to completely drive into the grain boundary induction region, and a single domain does not grow in the crystal growth region.

【0054】また本実施例では、結晶粒界誘導領域の面
積をそれぞれ100μm2としたが、この面積は10μ
2以上、1000μm2以下であれば他の面積となるよ
うに形成してもよい。結晶粒界誘導領域の面積が10μ
2よりも小さいと、結晶粒界誘導領域に追いやられた
ドメインは結晶粒界誘導領域に完全に入り込まずにその
まま、結晶成長領域に成長するので、結晶成長領域に単
一ドメインが成長しない。また、結晶粒界誘導領域の面
積が1000μm2よりも大きいと、成長領域が大きく
なりすぎて、結晶成長領域に到達する前に成長が止まっ
てしまう。
In this embodiment, the area of the crystal grain boundary inducing region is set to 100 μm 2 , but this area is 10 μm.
It may be formed to have another area as long as it is m 2 or more and 1000 μm 2 or less. The area of the grain boundary induction region is 10μ
When it is smaller than m 2, the domain driven to the crystal grain boundary induction region does not completely enter the crystal grain boundary induction region and grows as it is to the crystal growth region, so that no single domain grows in the crystal growth region. Further, if the area of the crystal grain boundary inducing region is larger than 1000 μm 2 , the growth region becomes too large and the growth stops before reaching the crystal growth region.

【0055】また本実施例では、非晶質珪素膜が100
nmの厚さに形成したが、この非晶質珪素膜が結晶化し
て得られる結晶性珪素膜の厚みが10nm以上、200
nm以下となる厚さであれば、他の厚さでもよい。結晶
性珪素膜の膜厚が10nmよりも薄いと、成膜不良など
の問題が起こりやすくなる。また、結晶性珪素膜の膜厚
が200nmよりも厚いと、単一ドメインが形成されに
くくなる。
In this embodiment, the amorphous silicon film is 100
The thickness of the crystalline silicon film obtained by crystallization of the amorphous silicon film is 10 nm or more, 200 nm.
Other thicknesses may be used as long as the thickness is less than or equal to nm. When the film thickness of the crystalline silicon film is thinner than 10 nm, problems such as defective film formation easily occur. Further, if the thickness of the crystalline silicon film is thicker than 200 nm, it becomes difficult to form a single domain.

【0056】また本実施例では、触媒物質をニッケルと
し、ニッケルの薄膜を1nmの厚さに成膜したが、触媒
物質はFe,Co,Ni,Ge,Ru,Rh,Pd,O
s,Ir,Pt,Cu,Auから選ばれた少なくとも1
種の元素を用いることができ、また、触媒物質層の厚さ
は、0.1nm以上、10nm以下のどの厚さに形成し
てもよい。
In this embodiment, nickel is used as the catalyst substance and a nickel thin film is formed to a thickness of 1 nm. However, the catalyst substance is Fe, Co, Ni, Ge, Ru, Rh, Pd, O.
at least 1 selected from s, Ir, Pt, Cu, Au
A seed element may be used, and the catalyst substance layer may be formed to any thickness of 0.1 nm or more and 10 nm or less.

【0057】触媒物質添加領域を覆う触媒物質層が0.
1nmよりも薄い場合、触媒物質層から非晶質珪素に拡
散する触媒物質の量が不足し、単一ドメインが形成でき
ない。また、触媒物質添加領域を覆う触媒物質層が10
nmよりも厚い場合、触媒物質の量が過大となり、結晶
性窒素膜に触媒物質が残留してしまう。
The catalyst substance layer covering the catalyst substance addition region has a thickness of 0.
When the thickness is less than 1 nm, the amount of the catalyst substance diffused from the catalyst substance layer to the amorphous silicon is insufficient, and a single domain cannot be formed. Further, the catalyst substance layer covering the catalyst substance addition region is 10
If the thickness is thicker than nm, the amount of the catalytic substance becomes excessive and the catalytic substance remains on the crystalline nitrogen film.

【0058】また本実施例では、600℃の温度で加熱
処理を行なったが、550℃以上、650℃以下のいず
れの温度で加熱処理を行なってもよい。加熱処理の温度
が550℃よりも低いと、非晶質珪素膜の結晶化が急激
に進行しがたくなり、結晶化に時間がかかる。また、加
熱処理の温度が650℃よりも高いと、触媒物質を添加
していない領域においても非晶質珪素膜の結晶化が起こ
り、結晶性珪素膜の結晶が微小になってしまい、結晶成
長領域に単一ドメインを成長させることができない。
Further, in this embodiment, the heat treatment is carried out at a temperature of 600 ° C., but the heat treatment may be carried out at any temperature of 550 ° C. or higher and 650 ° C. or lower. When the temperature of the heat treatment is lower than 550 ° C., the crystallization of the amorphous silicon film is hard to proceed rapidly, and it takes time to crystallize. Further, when the temperature of the heat treatment is higher than 650 ° C., the amorphous silicon film is crystallized even in the region where the catalyst substance is not added, and the crystal of the crystalline silicon film becomes minute, resulting in crystal growth. No single domain can be grown in the region.

【0059】[0059]

【発明の効果】以上のように本発明によれば、基板上に
積層される島状の非晶質珪素膜は、触媒物質が添加され
る触媒物質添加領域と、単一の結晶粒が成長する結晶成
長領域とを有し、前記触媒物質添加領域および結晶成長
領域との間に不要な結晶粒を成長させる結晶粒界誘導領
域を両側に有する経路が配置される形状とする。前記触
媒物質添加領域に触媒物質を添加し、加熱することによ
って、結晶性珪素膜を形成することができる。結晶粒界
誘導領域を経路の両側に設けることによって、この結晶
粒界誘導領域に不要な結晶粒を成長させ、結晶成長領域
に単一の結晶粒のみを成長させることができる。したが
って、非晶質珪素膜から性能、信頼性および安定性に優
れ、結晶性のよい結晶性珪素膜を容易に作製することが
できる。前記結晶成長領域を、たとえば半導体装置の活
性領域に用いることによって、電気的特性に優れた半導
体装置を作製することが可能となる。
As described above, according to the present invention, in the island-shaped amorphous silicon film laminated on the substrate, the catalyst substance added region to which the catalyst substance is added and the single crystal grain grows. And a crystal grain growth region, and a path having crystal grain boundary inducing regions on both sides between the catalyst substance addition region and the crystal growth region for growing unnecessary crystal grains is arranged. A crystalline silicon film can be formed by adding a catalyst substance to the catalyst substance addition region and heating. By providing the crystal grain boundary induction regions on both sides of the path, it is possible to grow unnecessary crystal grains in the crystal grain boundary induction region and to grow only a single crystal grain in the crystal growth region. Therefore, a crystalline silicon film having excellent performance, reliability and stability and good crystallinity can be easily formed from the amorphous silicon film. By using the crystal growth region as, for example, an active region of a semiconductor device, a semiconductor device having excellent electric characteristics can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1(a)〜図1(d)は、本発明の実施の一
形態の半導体作製方法の手順を示す図である。
1A to 1D are diagrams showing a procedure of a semiconductor manufacturing method according to an embodiment of the present invention.

【図2】図1(d)を基板4の一方側から見た平面図で
ある。
FIG. 2 is a plan view of FIG. 1D viewed from one side of a substrate 4.

【図3】マスク層13に窓14を形成した基板4の平面
図である。
FIG. 3 is a plan view of a substrate 4 having a window 14 formed in a mask layer 13.

【図4】非晶質珪素膜5が結晶化し、結晶性珪素膜15
が作製されたときの結晶粒の様子を示す平面図である。
FIG. 4 shows that the amorphous silicon film 5 is crystallized and the crystalline silicon film 15 is formed.
FIG. 6 is a plan view showing the state of crystal grains when the is manufactured.

【図5】非晶質珪素膜に触媒物質を添加することによっ
て結晶化を行なう従来技術で作製された結晶性珪素膜に
ついて、隣接点間の結晶方位のずれの大きさによって分
類された粒界の分布を示す図である。
FIG. 5 is a grain boundary of a crystalline silicon film produced by a conventional technique in which a catalyst substance is added to an amorphous silicon film to crystallize the amorphous silicon film. It is a figure which shows the distribution of.

【符号の説明】[Explanation of symbols]

4 基板 5 非晶質珪素膜 6 SiO2膜 9 触媒物質添加領域 10 結晶成長領域 11 結晶粒界誘導領域 12 経路 13 マスク層 14 窓 16 結晶核 17 結晶粒 18 単一ドメイン4 substrate 5 amorphous silicon film 6 SiO 2 film 9 catalyst substance added region 10 crystal growth region 11 crystal grain boundary induction region 12 path 13 mask layer 14 window 16 crystal nucleus 17 crystal grain 18 single domain

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F052 AA11 AA17 DA02 DB02 EA01 FA02 FA06 GB01 JA01 5F110 AA01 AA06 BB01 CC01 CC07 DD02 DD03 DD05 DD13 DD14 GG02 GG13 GG16 GG25 GG47 PP01 PP23 PP34 PP36    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F052 AA11 AA17 DA02 DB02 EA01                       FA02 FA06 GB01 JA01                 5F110 AA01 AA06 BB01 CC01 CC07                       DD02 DD03 DD05 DD13 DD14                       GG02 GG13 GG16 GG25 GG47                       PP01 PP23 PP34 PP36

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 基板上に積層した島状の非晶質珪素膜の
表面の一部に珪素の結晶化を助長する触媒物質を添加
し、エネルギーを印加することによって、前記触媒物質
が添加された触媒物質添加領域から触媒物質を添加して
いない結晶成長領域へ結晶成長を行なうことで結晶性珪
素膜を作製する半導体作製方法であって、 前記島状の非晶質珪素膜は、前記触媒物質添加領域と結
晶成長領域との間に、不要な結晶粒を成長させる結晶粒
界誘導領域を両側に有する経路が配置される形状を有
し、結晶成長領域に単一の結晶粒のみを成長させること
を特徴とする半導体作製方法。
1. A catalyst substance for promoting crystallization of silicon is added to a part of the surface of an island-shaped amorphous silicon film laminated on a substrate, and the catalyst substance is added by applying energy. A semiconductor manufacturing method for forming a crystalline silicon film by performing crystal growth from a catalyst substance addition region to a crystal growth region to which a catalyst substance is not added, wherein the island-shaped amorphous silicon film is A single crystal grain is grown in the crystal growth region with a shape in which a path having crystal grain boundary induction regions for growing unnecessary crystal grains on both sides is arranged between the material addition region and the crystal growth region. A method for manufacturing a semiconductor, comprising:
【請求項2】 前記触媒物質添加領域と結晶粒界誘導領
域との間の距離が1μm以上、20μm以下であること
を特徴とする請求項1記載の半導体作製方法。
2. The method for producing a semiconductor according to claim 1, wherein the distance between the catalyst substance addition region and the crystal grain boundary induction region is 1 μm or more and 20 μm or less.
【請求項3】 結晶粒界誘導領域の面積がそれぞれ10
μm2以上、1000μm2以下であることを特徴とする
請求項1記載の半導体作製方法。
3. The area of each of the grain boundary induction regions is 10
2. The method for producing a semiconductor according to claim 1, wherein the thickness is at least μm 2 and at most 1000 μm 2 .
【請求項4】 前記結晶性珪素膜の膜厚が10nm以
上、200nm以下であることを特徴とする請求項1記
載の半導体作製方法。
4. The method for producing a semiconductor according to claim 1, wherein the crystalline silicon film has a film thickness of 10 nm or more and 200 nm or less.
【請求項5】 前記触媒物質としてFe,Co,Ni,
Ge,Ru,Rh,Pd,Os,Ir,Pt,Cu,A
uから選ばれた少なくとも1種の元素を用いることを特
徴とする請求項1記載の半導体作製方法。
5. The catalyst material of Fe, Co, Ni,
Ge, Ru, Rh, Pd, Os, Ir, Pt, Cu, A
The semiconductor manufacturing method according to claim 1, wherein at least one element selected from u is used.
【請求項6】 結晶性珪素膜には、Fe,Co,Ni,
Ge,Ru,Rh,Pd,Os,Ir,Pt,Cu,A
uから選ばれた少なくとも1種の元素が1×1016/c
3以上、5×1019/cm3以下の濃度で含まれること
を特徴とする請求項1記載の半導体作製方法。
6. The crystalline silicon film comprises Fe, Co, Ni,
Ge, Ru, Rh, Pd, Os, Ir, Pt, Cu, A
at least one element selected from u is 1 × 10 16 / c
The method for manufacturing a semiconductor according to claim 1, wherein the semiconductor is contained at a concentration of m 3 or more and 5 × 10 19 / cm 3 or less.
【請求項7】 触媒物質添加領域には、Fe,Co,N
i,Ge,Ru,Rh,Pd,Os,Ir,Pt,C
u,Auから選ばれた少なくとも1種の元素が0.1n
m以上、10nm以下の膜厚で成膜されることを特徴と
する請求項1記載の半導体作製方法。
7. The Fe, Co, N in the catalyst substance addition region
i, Ge, Ru, Rh, Pd, Os, Ir, Pt, C
at least one element selected from u and Au is 0.1n
The semiconductor manufacturing method according to claim 1, wherein the film is formed with a film thickness of m or more and 10 nm or less.
【請求項8】 550℃以上、650℃以下の温度で加
熱処理を行なうことによって、エネルギーの印加を行な
う特徴とする請求項1記載の半導体作製方法。
8. The method of manufacturing a semiconductor according to claim 1, wherein energy is applied by performing heat treatment at a temperature of 550 ° C. or higher and 650 ° C. or lower.
【請求項9】 触媒物質の添加を行なう前に、触媒物質
添加領域を除く非晶質珪素膜の表面を膜厚が50nm以
上の窒化珪素膜、酸化珪素膜、炭化珪素膜のうち少なく
とも1種類で覆うことを特徴とする請求項1記載の半導
体作製方法。
9. Before the addition of the catalyst substance, at least one of a silicon nitride film, a silicon oxide film, and a silicon carbide film having a film thickness of 50 nm or more is formed on the surface of the amorphous silicon film excluding the catalyst substance addition region. The method for manufacturing a semiconductor according to claim 1, further comprising:
【請求項10】 基板上に形成される結晶性珪素膜を活
性領域として構成される半導体装置であって、 島状に非晶質珪素膜が積層された基板にエネルギーを印
加し、前記島状の非晶質珪素膜の表面の一部に結晶化を
助長する触媒物質を添加した触媒物質添加領域から、不
要な結晶粒を成長させるための結晶粒界誘導領域を経
て、単一の結晶粒のみを成長させる結晶成長領域へ結晶
化させた前記結晶成長領域を活性領域として用いること
を特徴とする半導体装置。
10. A semiconductor device comprising a crystalline silicon film formed on a substrate as an active region, wherein energy is applied to a substrate having an amorphous silicon film laminated in an island shape, Of the amorphous silicon film, a single crystal grain is passed through a grain boundary induction region for growing unnecessary crystal grains from a catalyst substance addition region in which a catalyst substance for promoting crystallization is added. A semiconductor device characterized in that the crystal growth region crystallized into a crystal growth region for growing only is used as an active region.
【請求項11】 前記触媒物質添加領域と結晶粒界誘導
領域との間の距離が1μm以上、20μm以下であるこ
とを特徴とする請求項10記載の半導体装置。
11. The semiconductor device according to claim 10, wherein the distance between the catalyst substance addition region and the crystal grain boundary induction region is 1 μm or more and 20 μm or less.
【請求項12】 前記結晶粒界誘導領域の1つの面積が
10μm2以上、1000μm2以下であることを特徴と
する請求項10記載の半導体装置。
12. The semiconductor device according to claim 10, wherein one area of the crystal grain boundary inducing region is 10 μm 2 or more and 1000 μm 2 or less.
【請求項13】 前記結晶性珪素膜の膜厚が10nm以
上、200nm以下であることを特徴とする請求項10
記載の半導体装置。
13. The crystalline silicon film having a thickness of 10 nm or more and 200 nm or less.
The semiconductor device described.
【請求項14】 結晶性珪素膜中には、Fe,Co,N
i,Ge,Ru,Rh,Pd,Os,Ir,Pt,C
u,Auから選ばれた少なくとも1種の元素が1×10
16/cm3以上、5×1019/cm3以下の濃度で含まれ
ることを特徴とする請求項10記載の半導体装置。
14. Fe, Co, N in the crystalline silicon film.
i, Ge, Ru, Rh, Pd, Os, Ir, Pt, C
At least one element selected from u and Au is 1 × 10
11. The semiconductor device according to claim 10, wherein the semiconductor device is contained at a concentration of 16 / cm 3 or more and 5 × 10 19 / cm 3 or less.
JP2001288879A 2001-09-21 2001-09-21 Semiconductor manufacturing method and semiconductor device Pending JP2003100631A (en)

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Publications (1)

Publication Number Publication Date
JP2003100631A true JP2003100631A (en) 2003-04-04

Family

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Country Link
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