JP2002124466A - Method for fabricating semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor device having uniform characteristics by controlling the position where a nucleus is generated, and to provide a semiconductor device. SOLUTION: The method for fabricating a semiconductor device comprises a step for forming a protrusion 12 on the surface of a substrate 11, a step for depositing an a-Si film 13 on the entire surface of the substrate 11, a step for generating micro nuclei 13b at steps 13a and 13a' by heat treating the substrate 11 entirely for about 2 hours, and a step for adding a catalytic metal to the entire surface of the substrate 11 and performing heat treatment for forming a CGS film 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a thin film transistor used for driving liquid crystal in an active matrix type liquid crystal display device, and a semiconductor device.

[0002]

2. Description of the Related Art In a liquid crystal display device having characteristics of low power consumption and being formed thin, when a thin film transistor (hereinafter abbreviated as TFT) is used as a driving element for driving liquid crystal, a high contrast and a high response speed are obtained. Further characteristics such as high speed are added. Therefore, a liquid crystal display device having a TFT is used for a display portion of a personal computer, a portable TV, and the like, and in recent years, the market scale thereof has greatly increased.

[0003] Among TFTs used in such applications, the semiconductor in the channel portion is a continuo.
s Grain Silicon (hereinafter abbreviated as CGS)
One using a membrane is known.

[0004] As described in Japanese Patent Application Laid-Open No. 6-244103, a CGS film is formed on a surface of an a-Si film by Ni.
Is a Si film having excellent crystallinity obtained by depositing a trace amount of a metal element such as, and then heating.

The TFT using the CGS film includes a conventional amorphous Si film (amorphous silicon: hereinafter abbreviated as an a-Si film) and a polycrystalline silicon film (hereinafter abbreviated as a p-Si film).
The power consumption is low and the response is fast as compared with a TFT using a TFT. TFT using such high mobility CGS film
Is expected to be used in sheet computers in the future, and is promising as a TFT to be mounted on a next-generation liquid crystal display device.

A method of forming a CGS film is called vertical growth.
There is a method called "deviation" and a method called "lateral growth". Vertical growth
Means that a metal element is directly added to the entire surface of the a-Si film.
This is a method for growing crystals by heating. What is lateral growth?
For example, SiO _TwoAfter forming a film,
The a-Si film is partially exposed by performing the ion implantation.
And add a metal element to the exposed part and heat it.
Is a method of growing a crystal.

The state of the vertical growth in the formation of the CGS film will be described with reference to FIG.

First, at the time of adding the catalytic metal element,
As shown in FIG. 13A, the a-Si film 51 is formed over the entire surface of the quartz substrate.

When the quartz substrate in such a state is subjected to solid phase growth at a temperature of about 600 ° C. for about 1 hour,
As shown in FIG. 13B, a Si crystal nucleus 52 serving as a nucleus is formed at an arbitrary position on the substrate. The generation density of the formed Si crystal nuclei 52 is affected by the film quality of the a-Si film 51, the concentration of the added metal element, and the like.

When the solid phase growth is further continued, FIG.
As shown in FIG. 5, a CGS crystal 53 grows radially around each Si crystal nucleus 52. The region of the CGS crystal grown around this single crystal nucleus is also called a domain. Although the orientation is not continuous between the CGS crystals 53 and is in a polycrystalline state, in the CGS crystal 53, the orientation between the crystals is continuous (Continuous).
Grain), that is, a quasi-single crystal state.

Further, if the solid phase growth is continued for a long time, finally, as shown in FIG.
The S crystals 53 collide with each other to form a domain boundary 54 where the CGS films 53 collide, and the entire surface of the substrate becomes the CGS film 53, and the crystal growth ends. The size of each of these SGS crystals 53 is C
Although it depends on the manufacturing conditions for forming the GS film, a large one may exceed 200 μm in diameter.

Finally, after the CGS film 53 is formed,
The metal element introduced into the film is described in JP-A-10-22353.
As described in Japanese Patent Application Publication No. 3 (1994), after a part of the formed CGS film is doped with phosphorus as a group V element at a high concentration, the metal element is gettered in a region doped with phosphorus by heat treatment. The ring is removed from a region to be a channel portion of the TFT.

[0013]

When the CGS crystal film 54 is formed by the above-described vertical growth, crystal nuclei are formed at arbitrary positions on the substrate surface, and the CGS crystal grows as each crystal nucleus grows. Therefore, it is inevitable that the domain boundary 54 is formed on the substrate surface. Therefore, the TFT is formed by the CGS film formed by the vertical growth.
When the TFT is formed, the TFT is formed only in the region where the internal crystal is continuous without including the domain boundary in the channel region.
And a TFT including a domain region at a channel boundary and a discontinuous region formed in an internal crystal.

In the domains adjacent to each other at the domain boundary 54, the orientations of the crystals grown to each other are not continuous, and the portion is considered to be the same as a polycrystalline state, so that the domain boundary is included in the channel region. Not T
FT and TFT with domain boundary in channel region
Is different in characteristics.

[0015] Such a difference in the characteristics of the TFTs becomes a problem not in the driver part but in the display part of the liquid crystal panel.

That is, each pixel T in the display section of the liquid crystal panel
FT is a TFT provided for each pixel.
, Each of which is in charge of display, a difference in characteristics of each TFT results in a difference in potential applied to each pixel electrode, and this difference in potential is directly reflected in a difference in transmittance of liquid crystal. As a result, CGS formed by vertical growth
In a TFT panel using a film, a difference in transmittance occurs for each pixel depending on whether each TFT has a domain boundary in a channel region, and the difference may appear as display unevenness.

The present invention has been made in view of the above problems, and in forming a CGS film by vertical growth, by controlling the position where crystal nuclei are generated, TFT characteristics can be made uniform. An object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device manufactured by the method.

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a linearly extending projection on a flat substrate surface;
Forming an amorphous silicon film over the entire surface of the substrate, and subjecting the amorphous silicon film to a heat treatment to form an amorphous silicon film at a step portion on the substrate formed along the protrusions; Forming a crystal nucleus in the porous silicon film, and adding a catalytic metal element for promoting crystallization of silicon onto the surface of the substrate and heating the crystal nucleus to grow the crystal nucleus. And crystallizing the entire structure into a crystalline silicon film.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the convex portion is formed after a film for forming the convex portion is formed on the substrate surface. It is formed by patterning a film for formation into a predetermined shape.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the film for forming the convex portion is a metal film or a film containing a metal element in a component. Things.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the convex portion is formed by directly patterning the substrate surface into a predetermined shape. is there.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the heat treatment of the amorphous silicon film is performed within a temperature range of 500 ° C. to 700 ° C. It is.

According to a sixth aspect of the present invention, there is provided a semiconductor device having a plurality of channel portions in a silicon film, wherein a portion of the silicon film corresponding to each channel portion does not include a domain boundary and has an internal crystal orientation. Is a crystalline silicon film formed only in a continuous region.

According to a seventh aspect of the present invention, there is provided a semiconductor device having a plurality of channel portions in a silicon film, wherein a portion of the silicon film corresponding to each channel portion includes a domain boundary at a predetermined position. It is a feature.

[0025]

Embodiment 1 Hereinafter, a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view for explaining a method of manufacturing a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view along the line BB 'in FIG.

In the method of manufacturing a semiconductor device according to the present invention, as shown in FIGS.
A strip-shaped step forming layer (projection) 62 extending linearly is formed such that a step 64 is formed on the surface of a flat substrate 61 which is a base layer of the film. This step forming layer 62 is formed on the substrate 61.
Is formed by performing etching directly on the substrate 61, or Poly-Si, Ta, WSi, Ti
It is formed by forming a film formed from such elements as described above and then performing etching. The step forming layer 62 includes
A plurality is formed in parallel at equal intervals over the entire surface of the substrate 61.

After forming the step forming layer 62 on the substrate 61, the substrate 61 on which the step is formed by the step forming layer 62 is formed.
A-Si film 63 is formed over the entire surface of the substrate. Thus, the step forming layer 62 is also covered with the a-Si film 63, and step portions 63a are formed on both sides of the step forming layer 62 of the a-Si film 63.

In such a state, the entire substrate 61 and the step forming layer 62 are heat-treated for about 2 hours under the temperature condition of 600 ° C.

When the substrate 61 and the step forming layer 62 are heated under these heating conditions, a step 63 a of the a-Si film 63 is formed.
, A fine crystal nucleus 65 of about 1 μm is generated. The generation density of such crystal nuclei 65 changes depending on the temperature, the film quality of the a-Si film 63, and the like. However, the generation of the crystal nuclei 65 is caused by the stress caused by the distortion of the step 63a of the a-Si film 63. Since this is caused by a phenomenon that Si crystal is easily generated, the step portion 63a of the a-Si film 63 is formed.
In a flat part which is not, such a distortion is small and S
No i crystal is generated.

As a result, as shown in FIGS. 1B and 2B, the crystal nucleus 65 is formed in the stepped portion 6 of the a-Si film 63.
Solid-phase growth is performed at 3a, and a strip-shaped Si film is formed along the direction in which the step 64 extends.

Next, when a catalytic metal is added to the entire surface of the substrate and a heat treatment for forming a CGS film is performed, FIG.
As shown in FIG. 2C and FIG. 2C, the domain grows from the step 64 using the minute Si crystal 65 formed in the step 63a of the a-Si film 63 as a nucleus for domain growth. In this case, the direction in which the step 64 extends (FIG. 1B)
, The solid phase growth has already been completed, so that no crystal grows in this direction. On the other hand, since no other crystal nucleus exists in a direction perpendicular to the step 64 (indicated by an arrow Y in FIG. 1C),
A sufficient growth region remains, and the domain grows in a direction orthogonal to the step 64. Therefore, the domain grows in both directions perpendicular to the step 64 with the Si crystal formed along the step 64 as the center.

As the growth of the domain progresses, as shown in FIGS. 1D and 2D, on the step forming film 62,
The domains grown from the step 64 on each side surface of the step forming layer 62 collide with each other, and the step forming layer 6
A domain boundary 66 is formed on 2 and domain growth stops.

Since the domain grows at the same speed from the step portions 63a on both sides of the a-Si film 63, the domain boundary 6
The step 6 occurs at a substantially middle point of each step 64 formed on both sides of the step forming layer 62, that is, substantially at the center of the step forming layer 62 in the width direction and substantially at the center between the adjacent step forming layers 62. Therefore, the location where the domain boundary 66 occurs is specified at this location.

As described above, the step forming layer 62 is formed on the substrate 61.
Are provided, steps 64 are respectively formed on both sides of the step forming layer 62, and an a-Si film 63 is formed on the entire substrate 61.
By performing the heat treatment, crystal nuclei 65 are formed along each step 63a of the a-Si film 63, and crystals are grown from each step 63a.
The generation location of the domain boundary 66 can be specified in advance between the steps 64. Therefore, in the TFT channel portion formed thereafter, the domain boundary 66
Can be easily controlled.

As a result, a plurality of TFT elements having uniform characteristics can be formed on the substrate 61, and variations in the characteristics of the TFT elements can be suppressed. Therefore, in a liquid crystal panel using a substrate on which a TFT element is formed, display unevenness can be prevented.

Next, a semiconductor device actually manufactured by the above manufacturing method will be described with reference to the drawings.

FIGS. 3 to 6 are side sectional views showing the manufacturing process of the TFT as the semiconductor device of the first embodiment with time, and the manufacturing process progresses sequentially from FIG. 3 to FIG. FIG. 7 is a plan view of the TFT 1 manufactured by the manufacturing steps of FIGS. 3 to 6, and FIG.
It is an I 'sectional view.

The TFT 1 is manufactured by the following steps.

(1) First, as shown in FIG. 3A, the quartz substrate 11 is directly etched by using general photolithography and dry etching on the quartz substrate 11, and A strip-shaped convex portion 12 extending linearly is formed. Each protrusion 12 has a thickness of 50 nm to 30 nm.
The thickness may be about 0 nm.

(2) Next, as shown in FIG.
An LPCV (Low) is formed on the quartz substrate 11 on which the portion 12 is formed.
 Pressure Chemical Vapor
The a-Si film 13 is formed by the Deposition method.
Deposit to a thickness of 0 nm. This a-Si film 13 is formed.
The condition for this is that disilane gas (Si _Two
H₆) At a temperature of 450 ° C. under a pressure of 50 Pa
Was.

A-Si film 1 formed on quartz substrate 11
In 3, steps 13 a and 13 a ′ are formed on both sides of the protrusion 12 because the protrusion 12 is formed on the quartz substrate 11.

(3) Next, heat treatment is performed on the quartz substrate 11 to form crystal nuclei 13b along the steps 13a and 13a 'of the a-Si film 13 as shown in FIG. 3C. . The heating in this case is performed in a nitrogen atmosphere at 500 ° C.
It is performed within a temperature range of 700 ° C. Each step 13a, 13a '
Each of the crystal nuclei 13b formed at the center becomes the center of the domain growth of the CGS film. At this time, steps 13 and 13
Since no stress due to strain is applied to portions other than a ′, no crystal nuclei are generated.

(4) Next, the entire surface of the a-Si film 13 is N
By spin-coating an aqueous solution of i (CH ₃ COOH) ₂ (nickel acetate) at a concentration of 10 ppm, as shown in FIG. 3D, Ni, which is a catalytic metal element that promotes crystallization of Si, The entire surface of the a-Si film 13 is applied so that the Ni concentration is about 1 × 10 ¹³ atm / cm ² .

As a method for adding Ni to the surface of the a-Si film 13, other methods such as a sputtering method, a CVD method, a plasma processing method, and an evaporation method may be used.

(5) Next, the quartz substrate 11 is heated in a nitrogen atmosphere at a temperature of 600 ° C. for a reaction time of 12 hours to crystallize the a-Si film 13, as shown in FIG. Thus, the CGS film 14 is formed. The CGS film 14 starts to grow from the step portions 13a and 13a 'as starting points,
The growth is continued perpendicular to the steps 13a and 13a ',
Steps 13a and 13a at an intermediate point between
When the domaines growing from both sides of a ′ collide with each other, a domain boundary 14 a is formed at a substantially middle point in the width direction of the protrusion 12.

(6) Next, as shown in FIG.
on the CGS film 14 containing i, due atmospheric pressure CVD stacking a first SiO ₂ film 15 to a film thickness of 200 nm, further using a common photolithography and dry etching, the first SiO ₂ film Pattern 15 and CGS
A part of the film 14 is exposed.

(7) Next, as shown in FIG. 4C, phosphorus ions having a concentration of about 2 × 10 ¹⁵ atm / cm ² are implanted into the entire surface of the substrate. At this time, the first SiO ₂ film 15
Phosphorus ions are implanted into the portion of the CGS film 14 that is not covered with the first SiO ₂ film 15 and serves as an implantation mask, thereby forming a CGS film 14b containing a high concentration of phosphorus.

(8) Next, as shown in FIG. 4D, the quartz substrate 11 is heated under the conditions of a temperature of 600 ° C. and a reaction time of 24 hours to remove the Ni element in the CGS film 14. Gettering is performed in the CGS film 14b containing a high concentration of phosphorus.

(9) Next, as shown in FIG. 5A, CGS containing a high concentration of phosphorus by dry etching.
The film 14b is entirely removed, and then the first SiO ₂ film 15 is completely removed using buffered hydrofluoric acid. C left
The GS film 14 contains almost no Ni element due to the gettering effect of the CGS film 14b containing a high concentration of phosphorus.

(10) Next, as shown in FIG.
The second oxide film 16 is formed on the surface by oxidizing the CGS film 14 to a thickness of 30 nm at a temperature of 950 ° C. in an oxygen atmosphere. This step is called second gettering and is performed to further remove the metal element (Ni) reduced by the above-described gettering. This second gettering includes HCl, HF, HBr, Cl ₂ , F ₂ ,
Heat treatment in an oxidizing atmosphere containing at least one kind of halogen element such as Br ₂ enhances the gettering effect. The temperature range is desirably in the range of 700 to 1150 ° C., but as the temperature is higher, diffusion of the metal element in the oxide film is promoted, and the gettering effect is increased.

(11) Next, after removing the second oxide film 16 using buffered hydrofluoric acid, patterning is performed using general photolithography and dry etching as shown in FIG. 5C. Then, the CGS film 17 is formed.

(12) On the CGS film 17 patterned as described above, as shown in FIG. 5D, a third oxide film 18 as a gate insulating film is formed to a thickness of 80 nm by the CVD method. After that, a p-Si film is further deposited to a thickness of 300 nm by a CVD method, and the p-Si film is patterned by using general photolithography and dry etching. The gate electrode 19 is formed along. CGS film 1 under this gate electrode 19
The portion 7 becomes the TFT active region 17a.

Here, as described above, the domain boundary 14a
Is formed at a substantially middle position in the width direction of the convex portion 12, so that by selecting a region for forming the gate electrode 19, the domain boundary 14a may be included in the active region 17a of the TFT. , May not be included. Here, patterning is performed so that the gate electrode 19 is located on one side of the convex portion 12 adjacent to the domain boundary 14a so that the domain boundary 14a is not included in the TFT active region 17a.

(13) Next, as shown in FIG.
Using the gate electrode 19 as a mask, phosphorus ions having a concentration of about 2 × 10 ¹⁵ atm / cm ² are implanted into the CGS film 17 to form a side CGS film 17 not including the domain boundary 14 a with respect to the gate electrode 19. Gate electrode 1 including source region 20a and including domain boundary 14a
A drain region 20 b is formed in the CGS film 17 on the other side of the TFT 9, and a TFT active region 17 a into which phosphorus ions are not implanted is formed below the gate electrode 19.

(14) Next, as shown in FIG. 6B, the C oxide film is formed on the entire surface of the third oxide film 18 and the gate electrode 19.
A fourth oxide film 21 as an interlayer insulating film is formed to a thickness of 600 nm using a VD method, and activated in a nitrogen atmosphere to activate phosphorus ions implanted into the source region 20a and the drain region 20b. At a temperature of 950 ° C, 30
After performing a heat treatment for a reaction time of 10 minutes, the source contact hole 26 and the drain region 20b reaching the source region 20a are formed in the third and fourth oxide films 18 and 21 by using general photolithography and dry etching. A drain contact hole 27 that reaches is formed.

(15) Finally, a 400 nm thick Al
By depositing Si and repeating photolithography and dry etching, a source wiring 22 and a drain electrode 23 shown in FIG. 6C are formed. afterwards,
A protective film 24 having a pixel contact hole 28 is formed by depositing a nitride film having a thickness of 400 nm and sequentially performing photolithography and dry etching. Then, a transparent conductive film (ITO) having a thickness of 80 nm is deposited, and photolithography and dry etching are sequentially performed to form the pixel electrode 25 on the protective film 24. The pixel electrode 25 is connected to the drain electrode 23 via the pixel contact hole 28. Thereby, TF
T1 is formed.

FIG. 7 is a plan view of the TFT 1. In FIG. 7, some films are omitted for easy understanding. In the TFT 1, the source wiring 22 is provided in a state orthogonal to the gate electrode 19, and the source region 20 a provided on the side of the gate electrode 19 is connected to the source electrode 22 a and the source wiring 22 through the source contact hole 20. It is connected. Further, the drain region 20 b provided on the side of the gate electrode 19 with the domain boundary 14 a interposed therebetween is connected to the drain electrode 2 via the drain contact hole 27.
3 and the drain electrode 23 is connected to the pixel electrode 25 via the pixel contact hole 28.

As is apparent from the above description, in the semiconductor device manufactured by the manufacturing method according to the first embodiment, the convex portion 12 extending linearly is formed on the quartz substrate 11.
An a-Si film 13 is formed on the quartz substrate 11 in this state,
After the steps 13a and 13a 'are formed on the a-Si film 13, the steps 13a and 13a
After the formation of the crystal nucleus 13b in the portion a ', the solid phase growth is performed by adding a catalytic metal element.
The CGS film 14 in which the position of 4a is controlled can be formed. For this reason, it is possible to include or not include the domain boundary 14 in the active region 17a of the TFT 1, and the variation in TFT characteristics is reduced, so that a liquid crystal panel with a uniform display can be manufactured.

As a result, it becomes possible to realize a high-performance active matrix type liquid crystal display device, mountable image, three-dimensional IC, and the like. (Embodiment 2) A method of manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described below with reference to the drawings.

FIGS. 8 to 11 are sectional views showing the manufacturing steps of the TFT 2 which is the semiconductor device of the second embodiment with time, and the manufacturing steps sequentially progress from FIG. 8 to FIG.
FIG. 12 is a top view of the TFT 2 manufactured by the manufacturing method shown in FIGS. 8 to 11, and FIG. 11C is a cross-sectional view taken along the line HH ′ of FIG.

The TFT 2 is manufactured by the following steps.

(1) First, as shown in FIG. 8A, a formation film 31a made of an element such as Poly-Si, Ta, WSi, Ti, etc. is formed on a quartz substrate 31 and then a general film is formed. By performing etching using appropriate photolithography and dry etching, a band-shaped step film 49 extending linearly is formed. On both sides of the step film 49,
Steps 32 and 32 'are formed. Further, a base insulating film 50 is formed so as to cover the step film 49. Step film 4
The thickness of 9 may be about 50 nm to 300 nm. When the step film 49 is formed of a metal film such as Ta, Ti, or WSi, the step film 49 can also serve as a light-shielding film for preventing light from entering the TFT 2.

(2) Next, as shown in FIG. 8B, LPCVD (Low Pressur) is formed on the underlying insulating film 50.
e Chemical Vapor Depositi
On), the a-Si film 33 is deposited to a thickness of 70 nm. Conditions for forming the a-Si film 33 are as follows:
Disilane gas (Si ₂ H ₆ ) was used as a source gas, and 50
The temperature was 450 ° C. under a pressure of Pa.

A-Si film 33 formed on step film 49
Are formed on both sides of the step film 49 so that the steps 33a and 32 'are formed on both sides of the step film 49.
And 33a 'are formed.

(3) Next, a heat treatment is performed on the quartz substrate 31 to form a step 3 of the a-Si film 33 as shown in FIG.
A crystal nucleus 33b is formed at portions 3a and 33a '. The heating in this case is performed in a nitrogen atmosphere within a temperature range of 500 ° C to 700 ° C. The crystal nuclei 33b formed on each of the steps 33a and 33a 'become the center of the domain growth of the CGS film. At this time, since no stress is applied to portions other than the steps 33a and 33a ', no crystal nuclei are generated.

(4) Next, Ni (CH ₃ COOH) ₂ (nickel acetate) is applied over the entire surface of the a-Si film
By spin-coating an aqueous solution dissolved at a concentration of 0 ppm, as shown in FIG. 8D, Ni, which is a catalytic metal element that promotes crystallization of Si, is deposited on the entire surface of the a-Si film 33, Is applied so as to be about 1 × 10 ¹³ atm / cm ² .

As a method for adding Ni to the surface of the a-Si film 33, other methods such as a sputtering method, a CVD method, a plasma processing method, and an evaporation method may be used.

(5) Next, the quartz substrate 31 is subjected to a heat treatment under a condition of a temperature of 600 ° C. and a reaction time of 12 hours in a nitrogen atmosphere to crystallize the a-Si film 33. As shown in FIG. 7, a CGS film 34 is formed. This CGS film 34
Starts growing from the step portions 33a and 33a ', continues to grow vertically to the step portions 33a and 33a', and at an intermediate point between the step portions 33a and 33a ',
The domains growing from both sides of the step portions 33a and 33a 'collide with each other, so that a domain boundary 34a is formed at a substantially middle point in the width direction of the formation film 31a.

(6) Next, as shown in FIG.
On CGS film 34 containing i, the first SiO ₂ film 35 is deposited to a thickness of 200nm due atmospheric pressure CVD, further using a common photolithography and dry etching, a first SiO ₂ Patterning the film 35, CG
A part of the S film 34 is exposed.

(7) Next, as shown in FIG.
2 × 10 on the entire board^Fifteenatm / cm ^TwoModerate concentration of phosphorus
Implant ions. At this time, the first SiO_TwoThe membrane 35
Acts as an implantation mask and acts as a first SiO_TwoCovered by membrane 35
Phosphorus ions are implanted into the CGS film
As a result, a CGS film 34b containing a high concentration of phosphorus is formed.
You.

(8) Next, as shown in FIG. 9D, the quartz substrate 31 is heated under the conditions of a temperature of 600 ° C. and a reaction time of 24 hours, and the Ni element in the CGS film 34 is removed. Gettering is performed in the CGS film 34b containing a high concentration of phosphorus.

(9) Next, as shown in FIG.
CG containing high concentration of phosphorus using dry etching method
The S film 34b is entirely removed, and then the first SiO ₂ film 35 is entirely removed using buffered hydrofluoric acid. The remaining CGS film 34 is a CGS film 34b containing a high concentration of phosphorus.
Hardly contains the Ni element due to the gettering effect.

(10) Next, as shown in FIG. 10B, the CGS film 34 is oxidized to a thickness of 30 nm in an oxygen atmosphere at a temperature of 950 ° C. to form a second film on the surface. Oxide film 36 is formed. This step is called second gettering and is performed to further remove the metal element (Ni) reduced by the above-described gettering. This second gettering comprises HCl, HF, HBr, Cl
_By performing heat treatment in an oxidizing atmosphere containing at least one kind of halogen element such as ₂ , F ₂ and Br ₂ , the gettering effect is enhanced. The temperature range is from 700 ° C to 1
It is desirable to be in the range of 150 ° C., but the higher the temperature,
Diffusion of the metal element in the oxide film is promoted, and the gettering effect is enhanced.

(11) Next, after removing the second oxide film 36 using buffered hydrofluoric acid, as shown in FIG. 10C, patterning is performed using general photolithography and dry etching. Is performed to form the CGS film 37.

(12) Next, on the CGS film 37 patterned as described above, as shown in FIG.
The third oxide film 38 as a gate insulating film is
After being formed to a thickness of 0 nm, p
-Si film is deposited to a thickness of 300 nm, and the p-Si film is patterned using general photolithography and dry etching to form a formation film 31a on the formation film 31a.
The gate electrode 39 is formed along. This gate electrode 3
9 below the CGS film 37 is a TFT active region 37a.
Becomes

Here, as described above, the domain boundary 34a
Is formed at a substantially middle position in the width direction of the formation film 31a. Therefore, by selecting a region where the gate electrode 39 is formed, it is possible to include the domain boundary 34a in the active region 37a of the TFT. , May not be included. Here, patterning is performed so that the gate electrode 39 is located on one side of the formation film 31a adjacent to the domain boundary 34a so that the domain boundary 34a is not included in the TFT active region 37a.

(13) Next, as shown in FIG. 11A, the CGS film 3 is formed using the gate electrode 39 as a mask.
7 is implanted with phosphorus ions at a concentration of about 2 × 10 ¹⁵ atm / cm ² , and a domain boundary 3
The source region 40a is formed in the lateral CGS film 37 not including the source region 40a.
Is formed, a drain region 40b is formed, and a TFT active region 37a into which phosphorus ions are not implanted is formed below the gate electrode 39.

(14) Next, over the entire surface of the third oxide film 38 and the gate electrode 39, as shown in FIG.
Fourth oxide film 41 as interlayer insulating film using CVD method
Is formed to a thickness of 600 nm, and the source region 40a,
In order to activate phosphorus ions implanted into the drain region 40b, at a temperature of 950 ° C. in a nitrogen atmosphere, 3
After performing a heat treatment for a reaction time of 0 minutes, the third heat treatment is performed using general photolithography and dry etching.
And a source contact hole 46 and a drain region 40 reaching the source region 40a in the fourth oxide films 38 and 41.
A drain contact hole 47 reaching B is formed.

(15) Finally, a 400 nm thick Al
By depositing Si and repeating photolithography and dry etching, a source wiring 42 and a drain electrode 43 shown in FIG. 11C are formed. afterwards,
A protective film 44 having a pixel contact hole 48 is formed by depositing a nitride film having a thickness of 400 nm and sequentially performing photolithography and dry etching. Then, a transparent conductive film (ITO) having a thickness of 80 nm is deposited, and photolithography and dry etching are sequentially performed to form the pixel electrode 45 on the protective film 44. The pixel electrode 45 is connected to the drain electrode 43 via the pixel contact hole 48. Thereby, TF
T2 is formed.

FIG. 12 is a plan view of the TFT 2.
In FIG. 12, some films are omitted for easy understanding. In the TFT 2, the source wiring 42 has the gate electrode 3.
9 is provided in an orthogonal state, and the source region 40 a provided on the side of the gate electrode 39 is connected to the source electrode 42 a and the source wiring 42 via the source contact hole 40.

When viewed from above, the TFT 2 is almost in the same state as the TFT 1 shown in FIG. 7 shown in the first embodiment.

As is apparent from the above description, in the semiconductor device manufactured by the manufacturing method according to the second embodiment, a formation film 31a extending linearly on a quartz substrate 31 is formed by a general photolithography. By performing the etching using dry etching, a strip-shaped step film 49 extending linearly is formed, and the quartz substrate 31 in this state is formed.
An a-Si film 33 is formed thereon, steps 33a and 33a 'are formed on the a-Si film 33, and a heat treatment is performed thereon, so that crystal nuclei 33 are formed on the steps 33a and 33a'.
After the formation of b, solid phase growth is performed by adding a catalytic metal element, so that the position of the domain boundary 34a is controlled.
The GS film 34 can be formed. For this reason, TFT
The second active region 37a may or may not include the domain boundary 34, so that variations in TFT characteristics are reduced and a liquid crystal panel with a uniform display can be manufactured.

As a result, it becomes possible to realize a high-performance active matrix type liquid crystal display device, mountable image, three-dimensional IC, and the like.

The TFT manufactured by the manufacturing method shown in Embodiment Modes 1 and 2 is an example of a semiconductor manufactured by the present invention, and the material, film thickness, forming method and the like are not limited to the above. .

[0086]

As is apparent from the above description, the method of manufacturing a semiconductor device according to the present invention comprises forming an a-Si film on a substrate having a projection formed thereon, and subjecting the a-Si film to a heat treatment. After forming a crystal nucleus at a step formed by having a convex portion, a solid phase growth is performed by adding a catalytic metal element to use the crystal nucleus formed at the step as a central part of domain growth. Since the CGS film in which the position of the domain boundary is controlled is formed, variation in TFT characteristics is reduced, and a liquid crystal panel having a uniform display can be manufactured.

As a result, it is possible to manufacture a semiconductor device which realizes a high-performance active matrix liquid crystal display device, a mountable image, a three-dimensional IC, and the like.

[Brief description of the drawings]

FIGS. 1A to 1D are plan views illustrating growth of a CGS film in a semiconductor manufacturing method according to the present invention.

FIGS. 2A to 2D respectively show BB ′ in FIG. 11;
It is sectional drawing which follows a line.

FIGS. 3A to 3D are cross-sectional views illustrating steps of manufacturing a TFT which is a semiconductor device according to the first embodiment of the present invention; FIGS.

FIGS. 4A to 4D are cross-sectional views each showing a manufacturing process following the manufacturing process of the TFT.

FIGS. 5A to 5D are cross-sectional views each showing a manufacturing process following the manufacturing process of the TFT.

FIGS. 6A to 6C are cross-sectional views each showing a manufacturing process following the manufacturing process of the TFT.

FIG. 7 is a diagram showing a TF which is a semiconductor device according to the first embodiment of the present invention;
It is a top view of T.

FIGS. 8A to 8D are cross-sectional views illustrating steps of manufacturing a TFT according to a second embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views each showing a manufacturing process following the manufacturing process of the TFT.

FIGS. 10A to 10D are cross-sectional views each showing a manufacturing process following the manufacturing process of the TFT.

FIGS. 11A to 11C are cross-sectional views each showing a manufacturing process following the manufacturing process of the TFT.

FIG. 12 shows a semiconductor device T according to the second embodiment of the present invention;
It is a top view of FT.

FIGS. 13A to 13D are plan views illustrating vertical growth of a CGS film.

[Explanation of symbols]

 Reference Signs List 12 convex part 13 a-Si film 13 a, 13 a ′ step 14 a domain boundary 18 third oxide film 19 gate electrode 20 a source region 20 b drain region 21 fourth oxide film 23 drain electrode 24 protective film 25 pixel electrode 28 pixel contact hole

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 GA59 JA25 JA29 JA35 JA38 JA39 JA42 JA44 JA46 JB13 JB23 JB27 JB32 JB33 JB38 JB41 JB57 JB63 JB69 KA04 KA07 MA05 MA07 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA30 MA35 NA37 NA41 5F052 AA17 CA07 DA02 DB02 FA06 FA13 HA03 JA01 5F110 AA30 BB02 BB10 BB11 CC02 DD03 DD21 EE09 EE45 FF02 FF29 GG02 GG13 GG16 GG22 GG25 GG47 HJ01 HJ04 HJ13 HJ23 HL05 HL06 NN03 PPN NN03 NN04 PPNN

Claims (7)

[Claims] A step of forming a linearly extending projection on a flat substrate surface; a step of forming an amorphous silicon film over the entire substrate surface; and a heat treatment for the amorphous silicon film. Forming a crystal nucleus on an amorphous silicon film formed on a step portion on the substrate formed along the convex portion; A crystal growth of the crystal nucleus by heating the amorphous silicon film to form a crystalline silicon film. 2. The projection according to claim 1, wherein the projection is formed by forming a projection-forming film on the surface of the substrate and then patterning the projection-forming film into a predetermined shape. A method for manufacturing a semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the film for forming the convex portion is a metal film or a film containing a metal element in a component. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said convex portion is formed by directly patterning said substrate surface into a predetermined shape. 5. The heat treatment of the amorphous silicon film includes the steps of:
The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed within a temperature range of 00 ° C. to 700 ° C. 6. A semiconductor device having a plurality of channel portions in a silicon film, wherein a portion of the silicon film corresponding to each channel portion does not include a domain boundary and is formed only in a region in which the orientation of the internal crystal is continuous. A semiconductor device characterized by being a formed crystalline silicon film. 7. A semiconductor device having a plurality of channel portions in a silicon film, wherein a portion of the silicon film corresponding to each channel portion includes a domain boundary at a position specified in advance.