JP2006324564A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method which can easily manufacture a high-performance semiconductor device. <P>SOLUTION: The semiconductor device manufacturing method includes a process S1 for forming a laminated layer which has a first amorphous silicon layer substantially composed of an amorphous silicon, and a catalyst layer containing a catalyst to promote the crystallization of the first amorphous silicon layer and having the catalyst layer laminated on the first amorphous silicon layer; a first crystallization process S2 which forms a first crystallized silicon layer by crystallizing the first amorphous silicon layer with the catalyst; a process S4 which forms a second amorphous silicon layer substantially composed of an amorphous silicon on the crystallized silicon layer; and a second crystallization process S5 which forms a second crystallized silicon layer by crystallizing the second amorphous silicon layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, high-performance semiconductors on insulating substrates and insulating films such as glass have been developed to realize large-sized, high-resolution liquid crystal display devices, high-speed, high-resolution contact image sensors, and three-dimensional integrated circuits (ICs). Attempts have been made to fabricate devices. As a semiconductor used for these semiconductor elements, a thin film silicon (silicon) semiconductor can be cited. Thin film silicon semiconductors are roughly classified into amorphous silicon semiconductors (a-Si) and crystalline silicon semiconductors (hereinafter abbreviated as “crystallized silicon semiconductors”).

  An amorphous silicon semiconductor has a low manufacturing temperature and can be manufactured relatively easily by a vapor phase method. It is also most commonly used because of its high mass productivity. However, the amorphous silicon semiconductor has lower conductivity than the crystallized silicon semiconductor. For this reason, there is a problem that it is difficult to manufacture a semiconductor element having excellent semiconductor characteristics with an amorphous silicon semiconductor. For this reason, establishment of a manufacturing method of a crystallized silicon semiconductor is strongly demanded from the viewpoint of realizing higher semiconductor characteristics.

  Conventionally, as a method of obtaining a crystallized silicon semiconductor, a method of directly forming a silicon semiconductor film having crystallinity at the time of film formation, and a method of forming an amorphous silicon semiconductor film and crystallizing it by annealing It has been known. As an annealing method, thermal annealing for directly heating the silicon semiconductor film and laser annealing for irradiating the silicon semiconductor film with laser are known.

  In the method of directly forming a silicon semiconductor film having crystallinity at the time of film formation, crystallization proceeds simultaneously with the film formation. For this reason, it is difficult to obtain a crystallized silicon semiconductor thin film having a uniform large grain size.

  In a method of forming a crystalline silicon semiconductor film by performing laser annealing on an amorphous silicon semiconductor film, a crystallization phenomenon in a melt-solidification process is used. Therefore, a high-quality crystallized silicon semiconductor film having a good grain boundary with a small particle diameter can be obtained relatively easily. However, since a laser device having sufficient stability has not yet been realized, it is difficult to uniformly form a crystallized silicon semiconductor film on a large-area substrate.

  A method of forming a crystalline silicon semiconductor film (crystallized silicon semiconductor film) by thermally annealing an amorphous semiconductor film is a method of directly forming a crystallized silicon semiconductor film at the time of film formation. A uniform crystallized silicon semiconductor film can be easily obtained as compared with a method of performing laser annealing on a semiconductor film. However, heat treatment for a long time at a high temperature is essential for crystallization by thermal annealing. For this reason, there are problems that the processing time is long and the throughput is low.

In order to obtain a crystallized silicon semiconductor film having high crystallinity using thermal annealing, a method of performing heat treatment in an oxygen atmosphere at a high temperature such as 1000 ° C. is also used. However, since this method requires a substrate that can withstand high temperatures, a semiconductor film cannot be formed on an inexpensive glass substrate or the like. Also, with this method, it is difficult to obtain high device characteristics. For example, in TFTs, only low device characteristics with a field effect mobility of about 100 cm ² / Vs can be obtained.

  For example, Patent Documents 1 to 3 disclose a method for manufacturing a crystallized silicon semiconductor film using a catalyst. Specifically, a method of forming a crystallized silicon semiconductor film by forming a layer made of a metal catalyst element such as nickel or palladium on the surface of an amorphous silicon semiconductor film and then performing heat treatment is disclosed. . By using a catalytic element that promotes crystallization of an amorphous silicon semiconductor film such as nickel or palladium, the heating temperature can be lowered, the processing time can be shortened, and the crystallinity can be improved.

In crystallization of an amorphous silicon semiconductor film using a catalyst, first, crystal nuclei having a catalyst element as a nucleus are generated. Crystal growth is promoted by the generated crystal nuclei, and crystallization of silicon proceeds rapidly. In addition, while one grain of the crystallized silicon film crystallized by the normal solid phase growth method has a twin crystal structure, the crystallized silicon film grain that has been crystallized by the crystallization promoted by the catalytic element The inside is composed of a number of columnar crystal networks, and each columnar crystal has an almost ideal single crystal state.
Japanese Patent Laid-Open No. 06-244103 Japanese Patent Laid-Open No. 06-296020 JP 2001-93835 A

  A conventional method for forming a crystallized silicon semiconductor film using a catalyst will be described in detail with reference to the drawings.

  12 to 15 are cross-sectional views for explaining a conventional process of forming the crystalline silicon layer 103.

  First, as shown in FIG. 12, the overcoat layer 102 is formed on the substrate 101. An amorphous (amorphous) silicon layer 103 is formed on the overcoat layer 102. An island-shaped catalyst layer 104 is formed on the amorphous silicon layer 103.

  The substrate thus formed is thermally annealed (FIG. 12). Then, the catalyst contained in the island-shaped catalyst layer 104 located at the end in FIG. 12 is silicided, and the silicided catalyst (hereinafter abbreviated as “catalyst silicide”) 105 is a silicon layer 103 as annealing proceeds. Move in. In the silicon layer 103, the portion 103a through which the catalyst silicide 105 has passed is partially crystallized. The moved catalyst silicide 105 remains in the center of FIG. 12 (FIG. 13). The portion 103b where the catalyst silicide 105 has not moved does not substantially accelerate crystallization and remains substantially amorphous silicon.

  In FIG. 13, the catalyst silicide 105 remaining in the center portion may be exposed on the surface of the silicon layer 103 or may not be exposed on the surface of the silicon layer 103 depending on the annealing conditions. In FIG. 13, for convenience of explanation, it is assumed that the right catalyst silicide 105 a is exposed on the surface of the silicon layer 103 and the left catalyst silicide 105 b is not exposed on the surface of the silicon layer 103.

  Next, laser annealing is performed on the silicon layer 103 by irradiating ultraviolet light (FIG. 13). As a result, the crystallization of the silicon layer 103 is further promoted with the crystals generated in the previously performed thermal annealing step as nuclei.

  After the laser annealing, etching is performed using an etching solution such as hydrogen fluoride water in order to remove the catalyst silicide 105a (FIG. 14). This is because when the catalyst silicide 105 remains, desired semiconductor characteristics are difficult to obtain, and the catalyst silicide 105 is prevented from diffusing into the silicon layer 103. In this etching step, the catalyst silicide 105b that is not exposed on the surface of the silicon layer 103 cannot be removed and remains after the etching.

  FIG. 15 shows the etched substrate. Since the etching needs to be performed so that the catalyst silicide 105 is completely removed, as shown in FIG. 15, there is a possibility that the overcoat layer 102 under the portion where the catalyst silicide 105a exists is over-etched.

  For this reason, the conventional method has a problem that a coverage (film property) defect of a film formed on the silicon layer 103 may occur in a later process. There is also a problem that a large defect occurs in the formed silicon layer 103. Therefore, there is a problem that it is difficult to manufacture a high-performance semiconductor device using the crystallized silicon layer formed by the above formation method.

  If all of the generated catalyst silicide 105 is not exposed on the surface of the silicon layer 103, the problem of poor coverage does not occur, but many large catalyst silicides 105 remain in the silicon layer 103. When a large number of large catalyst silicides 105 remain, there is a problem that high semiconductor characteristics of the silicon layer 103 cannot be obtained. Therefore, there is a problem that it is difficult to manufacture a high-performance semiconductor device.

  The present invention has been made in view of the above points, and an object of the present invention is to realize a manufacturing method capable of easily manufacturing a high-performance semiconductor device.

  The manufacturing method according to the present invention relates to a semiconductor device having a crystallized silicon layer. The manufacturing method according to the present invention includes a first amorphous silicon layer substantially made of amorphous silicon and a catalyst for promoting crystallization of the first amorphous silicon layer. A step of forming a stack having a catalyst layer stacked on a silicon layer, and a first crystallization step of forming a first crystallized silicon layer by crystallizing the first amorphous silicon layer using a catalyst; A step of forming a second amorphous silicon layer substantially made of amorphous silicon on the first crystallized silicon layer, and a second crystallization by crystallizing the second amorphous silicon layer. A second crystallization step of forming a silicon layer.

  Similar to the conventional method for manufacturing a semiconductor device described above, in the manufacturing method according to the present invention, silicide (compound of catalyst and silicon) is generated in the first crystallization step. However, in the manufacturing method according to the present invention, the crystallized silicon layer is not formed at a time, but is formed in two stages from the first amorphous silicon layer and the second amorphous silicon layer. For this reason, when forming a crystallized silicon layer having the same thickness, the first amorphous silicon layer in the manufacturing method according to the present invention is thinner than the amorphous silicon layer in the conventional manufacturing method. Here, the amount of catalyst required for crystallization correlates with the thickness of the amorphous silicon layer to be crystallized. Specifically, the amount of catalyst required for crystallization increases as the thickness of the amorphous silicon layer to be crystallized increases. For this reason, the amount of silicide generated in the manufacturing process according to the present invention is smaller than the amount of silicide generated in the conventional manufacturing process. Therefore, according to the manufacturing method of the present invention, a high-quality crystallized silicon layer with little silicide can be obtained, and thus a high-performance semiconductor device can be manufactured.

  In the present invention, the catalyst layer may be provided on the first silicon layer or may be provided below the first silicon layer.

  The manufacturing method according to the present invention includes a removal step of removing a part or all of the silicide generated by the reaction between the catalyst and silicon contained in the first amorphous silicon layer by etching in the first crystallization step. Further, it may be included.

  After the first crystallization step is completed, before the second amorphous silicon layer is formed, a removal step is performed, so that, for example, silicide exposed from the surface of the silicon layer can be removed. For this reason, since a high-quality crystallized silicon layer with less silicide is obtained, a higher-performance semiconductor device can be manufactured.

  As described above, in the removal step of removing the silicide, there is a possibility that overetching is performed up to the substrate and the overcoat layer existing under the silicon layer. When overetching, a coverage (coverability) defect of a film formed on the crystallized silicon layer may occur. However, according to this configuration, even when overetching is performed, the second amorphous silicon layer is formed on the second amorphous silicon layer, and the second crystallized silicon layer is formed by crystallization. Therefore, a crystallized silicon layer with few defects and a relatively smooth surface can be obtained. Therefore, it is possible to effectively suppress the occurrence of poor coverage and the like. In addition, since the surface of the crystallized silicon layer can be made relatively smooth, a crystallized silicon layer having excellent semiconductor characteristics can be obtained. Therefore, a higher performance semiconductor device can be manufactured.

  In the manufacturing method according to the present invention, the second amorphous silicon layer may be crystallized by irradiating with laser light.

  For example, when the second amorphous silicon layer is crystallized by thermal annealing, not only the second amorphous silicon layer but also the already crystallized first crystallized silicon layer is almost uniform. Is supplied with heat. For this reason, there exists a possibility that the crystal | crystallization of the silicon which exists in a 1st crystallized silicon layer may melt | dissolve. Since the second amorphous silicon layer is crystallized from the interface with the first crystallized silicon layer with the crystals present in the first crystallized silicon layer as nuclei, If the existing silicon crystal melts, crystallization of the second amorphous silicon layer is hindered. For this reason, there is a problem that a high-quality crystallized silicon layer cannot be obtained.

  On the other hand, when the second amorphous silicon layer is crystallized by irradiating laser light (by applying laser annealing), only the second amorphous silicon layer is locally heated, and the first crystallized silicon is heated. The layer is not heated too much. Therefore, melting of silicon crystals in the first crystallized silicon layer can be suppressed, and the second amorphous silicon layer can be preferably crystallized. Therefore, a high-quality crystallized silicon layer with high crystallinity can be formed.

  From the viewpoint of more suitably crystallization of the second amorphous silicon layer, the laser light used for laser annealing preferably has a wavelength of 400 nm or less. This is because only the second amorphous silicon layer can be heated more locally by setting the wavelength of the laser light to a short wavelength of 400 nm or less.

  In the manufacturing method according to the present invention, it is preferable that crystallized silicon always exists in the first crystallized silicon layer throughout the second crystallization step.

  As described above, when all of the crystallized silicon in the first crystallized silicon layer is melted in the second crystallization step, crystallization of the second amorphous silicon layer does not proceed appropriately. Further, recrystallization of the melted portion of the first crystallized silicon layer does not proceed appropriately. For this reason, a high-quality crystallized silicon layer cannot be obtained. When the second crystallization process is performed in a state where silicon crystals are always present in the first crystallized silicon layer, the second crystallized silicon layer is crystallized and the first silicon layer is melted. The recrystallization of the portion can be preferably promoted, and a high-quality crystallized silicon layer can be formed.

  In the manufacturing method according to the present invention, the first amorphous silicon layer preferably has a layer thickness of 1 nm to 200 nm.

  In the production method according to the present invention, the catalyst layer is one or more selected from the group consisting of nickel, iron, cobalt, platinum, and palladium as a catalyst for promoting crystallization of the first amorphous silicon layer. Two or more elements may be included.

  In the manufacturing method according to the present invention, in the first crystallization step, a part of the first amorphous silicon layer is crystallized by heating, and a part of the first crystallization step is crystallized by the partial crystallization step. A step of further crystallizing the first amorphous silicon layer by irradiating the first amorphous silicon layer with a laser.

  By doing so, a crystallized silicon layer having excellent semiconductor characteristics can be formed. The reason is not clear at present, but by leaving some amorphous regions in the partial crystallization process, the remaining amorphous regions are preferentially melted during laser annealing, This is considered to be due to the fact that it is crystallized reflecting only the good crystal components present in the crystallized region.

  As described above, according to the present invention, a high-quality crystallized silicon layer with little silicide can be obtained, so that a high-performance semiconductor device can be manufactured.

  In the present embodiment, a manufacturing process of the TFT substrate 1 using the present invention among manufacturing processes of the liquid crystal display device will be described in detail with reference to the drawings.

  FIG. 1 is a follow chart showing a manufacturing process of the TFT substrate 1.

  2 to 10 are cross-sectional views sequentially showing the manufacturing process of the TFT substrate 1.

  FIG. 11 is a plan view of the TFT substrate 1 manufactured by the manufacturing method according to this embodiment.

  First, as shown in FIG. 2, an overcoat layer 11 is formed on a substrate (for example, a glass substrate or a quartz substrate) 10. The overcoat layer 11 can be formed with a layer thickness of about 30 to 500 nm, for example, by sputtering. Examples of the material for the overcoat layer 11 include silicon oxide and silicon nitride.

  The overcoat layer 11 has a function of suppressing the diffusion of impurities present in the substrate 10 into the first amorphous silicon layer (semiconductor layer) 12 formed in a later step.

  A first amorphous silicon layer (first amorphous conductor layer) 12 made of substantially amorphous silicon is formed on the overcoat layer 11 (see FIG. 2). The first amorphous silicon layer 12 can be formed to a thickness of about 1 to 200 nm (preferably 5 to 50 nm, more preferably 10 to 30 nm) by a plasma chemical vapor deposition (plasma CVD) method or the like. From the viewpoint of obtaining the first amorphous silicon layer 12 of good quality, the first amorphous silicon layer 12 is preferably formed at 400 ° C. or lower.

  By forming the catalyst layer 13 on the first amorphous silicon layer 12, a stacked layer 14 including the overcoat layer 11, the first amorphous silicon layer 12, and the catalyst layer 13 is formed (FIG. 1). Step 1). The catalyst layer 13 includes one or more elements selected from the group consisting of nickel, iron, cobalt, platinum, and palladium as a catalyst for promoting crystallization of the first amorphous silicon layer 12. Preferably. Among these, it is particularly preferable to include nickel.

  As shown in FIG. 2, the substrate 10 on which the stack 14 is formed is thermally annealed (heat treatment) to crystallize a part of the first amorphous silicon layer 12 (partial crystallization process). The thermal annealing is preferably performed in an inert gas atmosphere, for example, a nitrogen gas atmosphere. In the step of raising the temperature in order to perform thermal annealing, hydrogen desorption treatment of the first amorphous silicon layer 12 is performed. It is preferable that after the hydrogen desorption treatment, the temperature is further raised to partially crystallize the first amorphous silicon layer 12. Specifically, for example, the hydrogen desorption treatment is performed by annealing at about 450 to 520 ° C. for 1 to 2 hours, and then the partial crystallization process is performed by annealing at about 520 to 570 ° C. for 2 to 8 hours. be able to.

  This thermal annealing process causes silicidation of a catalyst such as nickel contained in the catalyst layer 13. Partial crystallization of the first amorphous silicon layer 12 proceeds using the silicided catalyst as a nucleus. The silicided catalyst (catalyst silicide) 15 moves in the silicon layer 12 as the first amorphous silicon layer 12 partially crystallizes (see FIG. 3). Crystallization proceeds to some extent in the portion where the catalyst silicide 15 has passed, but crystallization hardly proceeds in the portion where the catalyst silicide 15 has not passed. That is, amorphous silicon and crystallized silicon are mixed in the first amorphous silicon layer 12 after the thermal annealing.

  After the thermal annealing, laser annealing is performed by irradiating light (preferably ultraviolet light), and the crystallization of the first amorphous silicon layer 12 is further promoted to complete the first crystallized silicon layer 12a. .

  In this way, by performing thermal annealing, a state in which a part of the first amorphous silicon layer 12 is crystallized is formed, and then by performing laser annealing, the first crystallized silicon layer 12a is formed, The first crystallized silicon layer 12a having a good crystal state can be formed. The reason for this is not clear at present, but by leaving some amorphous regions partially in the crystallization process, the remaining amorphous regions are preferentially melted during laser annealing, This is considered to be due to the fact that it is crystallized reflecting only the good crystal components present in the crystallized region.

  For laser annealing, it is preferable to use a laser that can emit light having a wavelength of 400 nm or less. For example, a XeCl excimer laser (wavelength 308 nm) or the like can be used. The first amorphous silicon layer 12 can be locally heated by using a laser beam having a relatively short wavelength of 400 nm or less. Moreover, when performing laser annealing, it is preferable to heat the board | substrate 10 to about 200-450 degreeC, for example.

  The catalyst silicide 15 that has moved inside the first amorphous silicon layer 12 in the thermal annealing step described above is exposed on the surface of the first crystallized silicon layer 12a depending on the thermal annealing conditions, the layer thickness of each layer, and the like. In some cases, the first crystallized silicon layer 12a is buried. In this embodiment, for convenience of explanation, it is assumed that a part of the catalyst silicide 15 is exposed on the surface of the first crystallized silicon layer 12a and a part of the catalyst silicide 15 is buried in the first crystallized silicon layer 12a. In the following description, it is assumed that the catalyst silicide exposed on the surface of the first crystallized silicon layer 12a is 15a, and the catalyst silicide buried in the first crystallized silicon layer 12a is 15b.

  In this embodiment, the first amorphous silicon layer 12 is crystallized by using both thermal annealing using a catalyst and laser annealing. However, the first amorphous silicon layer is only crystallized by thermal annealing using a catalyst. Layer 12 may be crystallized. The degree of crystallization of the first amorphous silicon layer 12 can be performed by adjusting the amount of the catalyst. When the first amorphous silicon layer 12 is to be crystallized only by thermal annealing using a catalyst, it is preferable to use a relatively large amount of catalyst.

  Next, as shown in FIG. 4, the catalyst silicide 15a exposed on the surface of the first crystallized silicon layer 12a is removed by etching using an etchant such as an aqueous hydrogen fluoride solution (hydrofluoric acid) (step in FIG. 1). 3). By removing the catalyst silicide 15a, a crystallized silicon layer with high purity can be produced. Note that since the etching solution hardly erodes the first crystallized silicon layer 12a, the catalyst silicide 15b buried in the first crystallized silicon layer 12a cannot be removed in this step.

  As shown in FIG. 5, a second amorphous silicon layer 16 substantially made of amorphous silicon is formed on the first crystallized silicon layer 12a (step 4 in FIG. 1). The second amorphous silicon layer 16 can be formed to a thickness of about 1 to 200 nm (preferably 5 to 50 nm, more preferably 10 to 30 nm) by plasma chemical vapor deposition (plasma CVD) or the like. From the viewpoint of obtaining a high-quality second amorphous silicon layer 16, it is preferable to perform the step of forming the second amorphous silicon layer 16 at 400 ° C. or lower.

  A second crystallized silicon layer 16a is formed by irradiating the second amorphous silicon layer 16 with ultraviolet light and laser annealing (step 5 in FIG. 1). For laser annealing, it is preferable to use a laser having a wavelength of 400 nm or less. For example, a XeCl excimer laser (wavelength 308 nm) or the like can be used. The second amorphous silicon layer 16 can be locally heated by using a laser beam having a relatively short wavelength. Specifically, only the second amorphous silicon layer 16 can be effectively heated without heating the first crystallized silicon layer 12a so much. Moreover, when performing laser annealing, it is preferable to heat the board | substrate 10 to about 200-450 degreeC, for example.

  In this laser annealing step, crystallization proceeds with a silicon crystal existing in the first crystallized silicon layer 12a as a nucleus. For this reason, it is preferable that crystallized silicon (silicon crystal) is always present in the first crystallized silicon layer 12a during the laser annealing process of the second amorphous silicon layer 16. In other words, by applying laser annealing, heat is also supplied to the first crystallized silicon layer 12a, and a part of the crystallized silicon in the first crystallized silicon layer 12a is melted. It is preferable to form the first crystallized silicon layer 12a so as not to melt all of the layer 12a. By doing so, a high-quality crystallized silicon layer can be manufactured.

  The preferred thickness of the first crystallized silicon layer 12a (the thickness of the first amorphous silicon layer 12) varies depending on the wavelength, output, aperture, etc. of the laser used. For example, when an excimer laser is used, the thickness of the first crystallized silicon layer 12a (the thickness of the first amorphous silicon layer 12) is preferably 1 nm or more and 200 nm or less. As described above, local heating becomes possible as the laser light having a short wavelength is used. Therefore, when a laser capable of emitting light having a shorter wavelength than the excimer laser is used, the first crystallized silicon layer is used. The layer thickness of 12a (the layer thickness of the first amorphous silicon layer 12) may be 1 nm or less.

  The surface of the formed second crystallized silicon layer 16a is cleaned using, for example, an aqueous hydrogen fluoride solution, thereby producing a crystallized silicon layer 17 composed of the first crystallized silicon layer 12a and the second crystallized silicon layer 16a. (Step 6 in FIG. 1).

  In the step of removing the catalyst silicide 15a by etching, overetching may occur, and a part of the overcoat layer 11 may be etched (see FIG. 4). However, in the manufacturing method according to the present embodiment, the second crystallized silicon layer 16a is formed thereon. Therefore, the crystallized silicon layer 17 having excellent semiconductor characteristics with few defects in the crystallized silicon layer and a relatively smooth surface can be manufactured (see FIG. 6). For this reason, generation | occurrence | production of the coverage defect of the layer formed on a crystallized silicon layer later can also be suppressed effectively.

  In the manufacturing method according to the present embodiment, the crystallized silicon layer is not formed at a time, but is formed in two steps from the first amorphous silicon layer 12 and the second amorphous silicon layer 16. For this reason, when forming a crystallized silicon layer having the same thickness, the first amorphous silicon layer 12 in the manufacturing method according to the present invention is thinner than the amorphous silicon layer in the conventional manufacturing method. . Here, the amount of catalyst required for crystallization of the amorphous silicon layer correlates with the layer thickness of the amorphous silicon layer to be crystallized. Specifically, the amount of catalyst required for crystallization increases as the thickness of the amorphous silicon layer to be crystallized increases. For this reason, the amount of silicide generated in the manufacturing process according to the present embodiment is smaller than the amount of silicide generated in the conventional manufacturing process. Therefore, according to the manufacturing method according to the present embodiment, a high-quality crystallized silicon layer 17 with little silicide can be obtained, so that a high-performance TFT substrate 1 can be manufactured.

  Next, an insulating thin film such as a silicon oxide film or a silicon nitride film is formed on the crystallized silicon layer 17, and a mask 18 is formed by patterning into a desired shape using a photolithography method or the like. The mask 18 is preferably formed so as to completely cover the region to be the TFT active region. For example, when the mask 18 is formed from a silicon oxide film, it can be formed using tetraethoxyorthosilicate (TEOS) as a raw material and RF plasma CVD method together with oxygen. The mask 18 preferably has a layer thickness of 100 nm to 400 nm.

  As shown in FIG. 7, the crystallized silicon layer 17 is doped with phosphorus from above the mask 18 (step 7 in FIG. 1). Thereby, phosphorus is implanted into the crystallized silicon layer 17 in a region not covered with the mask 18. On the other hand, phosphorus is not doped in the crystallized silicon layer 17 in the region covered with the mask 18. In the following description, it is assumed that the crystallized silicon layer in the region not doped with phosphorus is 17a, and the crystallized silicon layer in the region doped with phosphorus is 17b.

  After doping the crystallized silicon layer 17 with phosphorus, the substrate 10 is subjected to heat treatment. By this heat treatment, a catalyst (such as nickel) slightly remaining in the crystallized silicon layer 17 is attracted to phosphorus. As a result, since the concentration of the catalyst in the crystallized silicon layer 17a can be greatly reduced, the semiconductor characteristics of the crystallized silicon layer 17a can be greatly improved.

  Next, the mask 18 is removed by etching. The mask 18 can be removed by wet etching using, for example, 1:10 buffered acid (BHF). Thereafter, unnecessary portions of the crystallized silicon layer 17 are removed, and element isolation is performed (step 8 in FIGS. 8 and 1).

  A gate oxide film 19 is formed on the crystallized silicon layer 17 (step 9 in FIG. 1). The gate oxide film 19 can be formed of a silicon oxide film, a silicon nitride film, or the like. For example, when the gate oxide film 19 is formed of a silicon oxide film, it can be formed using tetraethoxyorthosilicate (TEOS) as a raw material and RF plasma CVD method together with oxygen.

  After the formation of the gate oxide film 19, in order to improve the bulk characteristics of the gate oxide film 19 itself and the interface characteristics between the crystallized silicon layer 17 and the gate oxide film 19, the atmosphere is 400 in an inert gas (nitrogen, argon, etc.) atmosphere. It is preferable to anneal at about 600 ° C. for about 1 to 4 hours.

  A gate electrode 20 is formed on the gate oxide film 19 (step 10 in FIG. 1). The gate electrode 20 can be formed of, for example, aluminum using a sputtering method and a photolithography method. The layer thickness of the gate oxide film 19 is preferably about 400 to 800 nm.

  An oxide layer 21 is formed on the surface of the gate electrode 20 by anodizing the surface of the gate electrode 20 (FIG. 9).

Next, an impurity (phosphorus or the like) is implanted into the TFT active region of the crystallized silicon layer 17 using the gate electrode 20 and the oxide layer 21 as a mask (step 11 in FIG. 1). For example, phosphine (PH ₃ ) can be used as the doping gas. The TFT active region into which impurities are implanted (doped) becomes a source region or a drain region in a later step. A region where no impurity is implanted later becomes a channel region of the TFT.

  After the impurity implantation, annealing is performed by irradiating a laser beam to activate the implanted impurity. At the same time, it is possible to improve the crystallinity of the crystallized silicon layer 17 where the crystallinity has deteriorated in the impurity implantation step.

  As shown in FIG. 10, an interlayer insulating film 22 is formed (step 12 in FIG. 1). The interlayer insulating film 22 can be formed of, for example, a silicon oxide film or a silicon nitride film using a CVD method or the like.

  Contact holes 22a and 22b that open to the crystallized silicon layer 17b are formed in the interlayer insulating film 22, respectively. A source electrode 23 is formed of a metal material (for example, a laminate of a titanium nitride film and an aluminum film) so as to cover the contact hole 22a. Source electrode 23 is electrically connected to crystallized silicon layer 17b via contact hole 22a. The titanium nitride film functions as a barrier layer that prevents aluminum from diffusing into the crystallized silicon layer 17.

  A pixel electrode 24 is formed of a transparent electrode material (such as indium tin oxide) so as to cover the contact hole 22b (step 13 in FIG. 1). The pixel electrode 24 is electrically connected to the crystallized silicon layer 17b via the contact hole 22b.

  Finally, the TFT substrate 1 shown in FIGS. 10 and 11 is completed by annealing, for example, in a hydrogen atmosphere.

  As described above, according to the manufacturing method according to the present embodiment, the crystallized silicon layer 17 having high purity, smoothness, and excellent semiconductor characteristics can be formed, so that a semiconductor such as a high-performance liquid crystal display device or the like can be formed. The device can be manufactured.

  As described above, according to the manufacturing method of the present invention, a high-performance semiconductor device can be manufactured, which is useful for manufacturing mobile phones, digital cameras, PDAs, subnote (wearable) personal computers, HMDs, and the like. It is.

2 is a follow chart showing a process for producing a TFT substrate 1. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. 5 is a cross-sectional view for explaining a manufacturing process of the TFT substrate 1. FIG. It is a top view of TFT substrate 1 produced by the manufacturing method concerning this embodiment. It is a cross-sectional view for explaining a manufacturing process of a conventional crystalline silicon layer 103. It is a cross-sectional view for explaining a manufacturing process of a conventional crystalline silicon layer 103. It is a cross-sectional view for explaining a manufacturing process of a conventional crystalline silicon layer 103. It is a cross-sectional view for explaining a manufacturing process of a conventional crystalline silicon layer 103.

Explanation of symbols

1 TFT substrate
10 Substrate
11 Overcoat layer
12 First amorphous silicon layer
12a First crystallized silicon layer
13 Catalyst layer
14 Lamination
15 Catalytic silicide
16 Second amorphous silicon layer
16a Second crystallized silicon layer
17 Crystallized silicon layer
18 mask
19 Gate oxide film
20 Gate electrode
21 Oxide layer
22 Interlayer insulation film
23 Source electrode
24 pixel electrode

Claims (8)

A first amorphous silicon layer substantially made of amorphous silicon and a catalyst for promoting crystallization of the first amorphous silicon layer, and is laminated on the first amorphous silicon layer Forming a laminate having a catalyst layer;
A first crystallization step of forming the first crystallized silicon layer by crystallizing the first amorphous silicon layer using the catalyst;
Forming a second amorphous silicon layer substantially made of amorphous silicon on the first crystallized silicon layer;
A second crystallization step of forming a second crystallized silicon layer by crystallizing the second amorphous silicon layer;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor device further includes a removal step of removing a part or all of the silicide generated by the reaction between the catalyst and the silicon contained in the first amorphous silicon layer by etching in the first crystallization step. Production method. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the crystallization of the second amorphous silicon layer is performed by irradiating a laser beam. In the manufacturing method of the semiconductor device according to claim 3,
The method of manufacturing a semiconductor device, wherein the laser beam has a wavelength of 400 nm or less. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein crystallized silicon is always present in the first crystallized silicon layer throughout the second crystallization step. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first amorphous silicon layer has a thickness of 1 nm to 200 nm. In the manufacturing method of the semiconductor device according to claim 1,
The said catalyst layer is a manufacturing method of the semiconductor device containing 1 type, or 2 or more types of elements chosen from the group which consists of nickel, iron, cobalt, platinum, and palladium as said catalyst. In the manufacturing method of the semiconductor device according to claim 1,
The first crystallization process includes a partial crystallization process in which a part of the first amorphous silicon layer is crystallized by heating, and the first non-crystallized part of which is crystallized in the partial crystallization process. And a step of further crystallizing the first amorphous silicon layer by irradiating the crystalline silicon layer with a laser.

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