JP2003085972A5 - - Google Patents
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- JP2003085972A5 JP2003085972A5 JP2001277675A JP2001277675A JP2003085972A5 JP 2003085972 A5 JP2003085972 A5 JP 2003085972A5 JP 2001277675 A JP2001277675 A JP 2001277675A JP 2001277675 A JP2001277675 A JP 2001277675A JP 2003085972 A5 JP2003085972 A5 JP 2003085972A5
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- JP
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- Prior art keywords
- input gate
- reference voltage
- signal
- transition
- detecting
- Prior art date
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Claims (5)
この入力ゲートの出力電圧の遷移を遅延させる遅延要素と、
前記入力ゲートの出力電圧を基準電圧と比較してタイミング信号を発生する比較回路と、
前記入力ゲートに与えられる電源電圧と同じ電源電圧を分圧して前記基準電圧を発生する基準電圧発生回路と、
を有することを特徴とするタイマ回路。An input gate for detecting a level transition of the input signal;
A delay element that delays the transition of the output voltage of the input gate;
A comparator circuit that compares the output voltage of the input gate with a reference voltage to generate a timing signal;
A reference voltage generating circuit that divides a power supply voltage that is the same as the power supply voltage applied to the input gate to generate the reference voltage;
A timer circuit comprising:
前記遅延要素は、前記ＣＭＯＳインバータの出力ノードとＮＭＯＳトランジスタとの間に挿入されている
ことを特徴とする請求項１記載のタイマ回路。The input gate is constituted by a CMOS inverter for detecting a transition from a low level state to a high level state of the input signal,
2. The timer circuit according to claim 1, wherein the delay element is inserted between an output node of the CMOS inverter and an NMOS transistor.
前記遅延要素は、前記ＣＭＯＳインバータの出力ノードとＰＭＯＳトランジスタとの間に挿入されている
ことを特徴とする請求項１記載のタイマ回路。The input gate is constituted by a CMOS inverter for detecting a transition from a high level state to a low level state of the input signal,
2. The timer circuit according to claim 1, wherein the delay element is inserted between an output node of the CMOS inverter and a PMOS transistor.
ことを特徴とする請求項１記載のタイマ回路。2. The timer circuit according to claim 1, wherein the reference voltage generating circuit has a control terminal capable of changing a generated reference voltage from the outside.
前記タイマ回路は、
前記疑似ワード線回路から発生される疑似ワード線信号を検出するための入力ゲートと、
この入力ゲートの出力電圧の遷移を遅延させる遅延要素と、
前記入力ゲートの出力電圧を基準電圧と比較してタイミング信号を発生する比較回路と、
前記入力ゲートに与えられる電源電圧と同じ電源電圧を分圧して前記基準電圧を発生する基準電圧発生回路と、
を有することを特徴とする半導体メモリ装置。A memory cell array, a row decoder for selectively driving the word lines of the memory cell array, a sense amplifier for detecting and amplifying bit line data of the memory cell array, and the activation timing of the word lines of the memory cell array are monitored in a pseudo manner A pseudo word line circuit that generates a pseudo word line signal, and a timer circuit that generates a sense amplifier activation signal for activating the sense amplifier with a predetermined time delay from the output of the pseudo word line signal,
The timer circuit is
An input gate for detecting a pseudo word line signal generated from the pseudo word line circuit;
A delay element that delays the transition of the output voltage of the input gate;
A comparator circuit that compares the output voltage of the input gate with a reference voltage to generate a timing signal;
A reference voltage generating circuit that divides a power supply voltage that is the same as the power supply voltage applied to the input gate to generate the reference voltage;
A semiconductor memory device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001277675A JP2003085972A (en) | 2001-09-13 | 2001-09-13 | Timer circuit and semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001277675A JP2003085972A (en) | 2001-09-13 | 2001-09-13 | Timer circuit and semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003085972A JP2003085972A (en) | 2003-03-20 |
| JP2003085972A5 true JP2003085972A5 (en) | 2005-07-21 |
Family
ID=19102162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001277675A Pending JP2003085972A (en) | 2001-09-13 | 2001-09-13 | Timer circuit and semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003085972A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006252721A (en) | 2005-03-14 | 2006-09-21 | Elpida Memory Inc | Overdrive period controller unit and overdrive period determination method |
| FR2977077B1 (en) * | 2011-06-27 | 2013-08-02 | Commissariat Energie Atomique | DELAY GENERATOR USING PROGRAMMABLE RESISTANCE BASED ON PHASE CHANGE MATERIAL |
| JP2024002737A (en) | 2022-06-24 | 2024-01-11 | ローム株式会社 | Timer circuit, oscillator circuit, and semiconductor device |
-
2001
- 2001-09-13 JP JP2001277675A patent/JP2003085972A/en active Pending
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