KR0141939B1 - Pulse generator - Google Patents

Abstract

The present invention discloses a pulse generator. The circuit includes an initialization circuit for initializing an output pulse signal in response to a first state of a clock signal, and feedbacks the output pulse signal through a feedback input terminal in response to a second state of the clock signal, and outputs the feedback output pulse. A feedback circuit for extending and outputting the pulse length of the input signal by delaying the input signal a predetermined time in response to the signal and feeding the predetermined number of times; and in response to the transition from the second state to the first state of the clock signal. And a pulse output circuit for inverting the output pulse signal of the feedback circuit and ending the extension of the output pulse. Therefore, the circuit configuration is simple and the chip area can be reduced at the time of integration.

Description

Pulse generator

1 is a circuit diagram of a conventional pulse generator.

FIG. 2 is a detailed circuit diagram of the delay element shown in FIG.

A-g in FIG. 3 is an operation timing diagram for explaining the operation of the conventional pulse generator shown in FIG.

4 is a circuit diagram of the pulse generator of the present invention.

5A to 5D are operation timing diagrams for explaining the operation of the pulse generator of the present invention shown in FIG.

* Explanation of symbols for main parts of the drawings

66: Delay element 67,69,71,81,120,130,150,170: Inverter

68, 70, 72, 80, 110, 140: NAND gate 82, 180: capacitor

100: PMOS transistor 160: CMOS transmission gate

The present invention relates to a pulse generator, and more particularly to a pulse generator that can be generated by varying the pulse length.

1 is a circuit diagram of a conventional pulse generator.

In FIG. 1, the pulse generator is composed of a delay element 66, inverters 67, 69, 71 and NAND gates 68, 70, 72. In FIG.

The delay element 66 is reset in response to the reset signal RESET_, and inputs and delays the signal DWL. The inverter 67 inverts the output signal of the delay element 66 and outputs the signal TOR_. The inverter 69 inverts and outputs the write enable signal WE. The inverter 71 inverts the output signal of the delay element 66 and outputs the signal TOW_. The NAND gate 68 inputs an output signal of the signal TOR_, the signal DWL, and the inverter 69, and outputs the result by non-logic multiplication. The NAND gate 70 inputs the write enable signal WE, the signal TO, and the output signal TOW_ of the inverter 71 to be non-logically output. The NAND gate 72 inputs the output signals and the signal SETPLS of the NAND gates 68 and 70 to be non-multiplied and outputs an output signal PULSE.

FIG. 2 is a detailed circuit diagram of the delay element 66 shown in FIG.

In FIG. 2, the delay element 66 is composed of a NAND gate 80, an inverter 81, and a capacitor 82.

The NAND gate 80 non-logically multiplies the input reset signal RESET_ with the signal DWL and outputs the result.

The capacitor 82 is connected between the output terminal of the NAND gate 80 and the ground voltage.

The inverter 81 inverts and outputs the output signal of the NAND gate 80.

3A to 3G are operation timing diagrams for explaining the operation of the conventional pulse generator shown in FIG.

The operation of the pulse generator shown in FIG. 1 will be described with reference to FIGS.

The operation of the pulse generator will be described by dividing the read mode and the write mode. The read mode and the write mode are controlled by the write enable signal WE, the write mode when the write enable signal WE is high level, and the read mode when the write enable signal WE is low level. .

First, in the read mode, when the write enable signal WE is at the low level, the reset signal RESET_ transitions from the low level to the high level as shown in FIG. It becomes an operational state. At this time, when the high level signal DWL is input as shown in FIG. 3c, the inverter 67 inverts the signal delayed by the delay element 66, and the signal TOR_ as shown in FIG. Makes the low level.

Since the write enable signal WE of the low level is inverted to the high level through the inverter 69 and input to the NAND gate 69, the signals DWL and TOR_ are shown in FIG. The low level signal is output from the NAND gate 68 while the mode high level is input, and the low level write enable signal WE is input to the NAND gate 70 so that the NAND gate 70 is high. The level signal is maintained and the signal SETPLS is input at a high level. Therefore, while the low level signal is output from the NAND gate 68, the high level signal PULSE is output from the NAND gate 72 as shown in FIG. 3G.

By performing such an operation, the pulse signal PULSE having a short pulse width can be generated in the read mode.

Next, the write mode will be described. When the write enable signal WE is at the high level, the reset signal RESET_ transitions from the low level to the high level as shown in FIG. The element 66 outputs the signal DWL with a predetermined time delay. The inverter 71 inverts the signal delayed by the delay element 66 and outputs a high level signal TOW_ as shown in FIG.

Since the high level signal TO is input as shown in b of FIG. 3, the low level at the NAND gate 70 while the signals TO and TOW_ are high level as shown in FIGS. Signal is output. In addition, since the high-level write enable signal WE is inverted into a low-level signal through the inverter 69 and input to the NAND gate 68, the high-level signal is output from the NAND gate 68. Will be maintained. Therefore, while the low level signal is output from the NAND gate 70, the high level output signal PULSE is output from the NAND gate 72 as shown in FIG.

By performing such an operation, a pulse signal of long pulse width PULSE can be generated in the write mode.

The circuits shown in FIGS. 1 and 2 are disclosed in US Pat. No. 5,258,952. In the above description, only the pulse generator is described, and various pulses RESET_, used as the input of the pulse generator shown in FIG. 1 by using the address state transition pulse ATD and the data state transition pulse DTD in the semiconductor memory device, are described. Circuits for generating DWL, TO, SETPLS) are described in detail in US Patent Publication No. 5,258,952.

Conventional pulse generators have a problem in that the circuit configuration for varying the pulse width is too complicated and the number of delay elements is too large to occupy a large chip area at the time of integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse generator capable of reducing the chip area and varying the pulse width at the time of integration due to the simple circuit configuration.

In order to achieve the above object, the pulse generator includes an initialization means for initializing an output pulse signal in response to a first state of a clock signal, and a feedback input terminal for returning the output pulse signal in response to a second state of the clock signal. Feedback means for delaying the input signal by a predetermined time in response to the feedback output pulse signal and feeding the predetermined number of times to extend the pulse length of the input signal and output the pulse signal to the second state of the clock signal. And pulse output means for inverting the output pulse number signal of the feedback means in response to the transition from the first state to the end of the output pulse.

Hereinafter, the pulse generator of the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram of the pulse generator of the present invention.

In FIG. 4, the pulse generator includes a PMOS transistor 100, NAND gates 110 and 140, inverters 120, 130, 150, and 170, a CMOS transmission gate 160, and a capacitor 180. have.

The NAND gate 110 inputs an address state transition signal (ATDS) and a signal from the node N3, and outputs the result by non-logic multiplication. The inverter 120 inverts and outputs the output signal of the NAND gate 110. The capacitor 180 is connected between the output terminal of the inverter 120 and the ground voltage Vss. The inverter 130 inverts the output signal of the inverter 120 and outputs it to the node N2. The NAND gate 140 inputs a clock signal CLK and a signal from the node N2, and outputs the result of a non-logical multiplication.

The inverter 150 inverts the signal from the node N2 and outputs the inverted signal. The inverter 170 inverts and outputs the click signal CLK.

The CMOS transmission gate 160 inputs an output signal of the inverter 150 and outputs the output signal to the node N3 in response to the clock signal CLK and the output signal of the inverter 170. The PMOS transistor 100 includes a gate electrode to which the clock signal CLK is applied, a source electrode to which the power supply voltage Vcc is applied, and a drain electrode connected to an output terminal of the CMOS transmission gate 160. In response to CLK, the power supply voltage Vcc is output to the node N3.

5 (a) shows the waveform of the clock signal CLK, FIG. 5 (b) shows the waveform of the address state transition signal ATDS, and FIG. 5 (c) shows the waveform from one to n times. The output waveforms of the nodes N1, N2, and N3 are shown in FIG. 5, and (d) of FIG. 5 shows the waveform of the output pulse signal PLGB.

The operation of the circuit shown in FIG. 4 will be described with reference to FIGS. 5A to 5D.

First, when the clock signal CLK is at the low level, the PMOS transistor 100 is turned on to output the high level power supply voltage Vcc to the node N3. The NAND gate 110 nonlogically multiplies the high level address state transition signal ATDS and the high level signal from the node N3 and outputs a low level signal to the node N1. The inverter 120, the capacitor 180, and the inverter 130 delay and buffer the low level signal of the node N1 to output the low level signal to the node N2. The inverter 150 inverts the low level signal of the node N2 and applies the high level signal to the CMOS transmission gate 160. The CMOS transfer gate 160 is turned off by the low level clock signal CLK. The NAND gate 140 nonlogically multiplies the low level clock signal CLK and the low level signal of the node N2 to output the high level output signal PLGB.

Next, when the clock signal CLK changes to a high level as shown in FIG. 3A, the PMOS transistor 100 is turned off, and the inverter 170 inverts the high level signal to output a low level signal. do. Accordingly, the CMOS transmission gate 160 is turned on in response to the clock signal CLK and transfers a high level signal output from the inverter 150 to the node N3.

In this state, when the address state transition signal ATDS is input at a low level as shown in FIG. 5 (b), the NAND gate 110 receives the low level address state transition signal ATDS from the node N3. The high-level signal of? Is non-logically multiplied and outputs the high-level sino to the node N1. The inverter 120, the capacitor 180, and the inverter 130 delay and output a high level signal of the node N1 to the node N2.

The inverter 150 inverts the high level signal of the node N2 and outputs the low level signal to the node N3 through the CMOS transmission gate 160.

The NAND gate 140 non-logically multiplies the high level signal of the node N2 by the high level clock signal CLK to output the low level output signal PLGB. In this way, the one-time feedback operation is completed.

The feedback from 2 to n times is also repeatedly performed to maintain the output signal PLGB at a low level. As shown in FIG. 5 (C), each time one feedback is performed, the pulse length is delayed by a predetermined time (TRC). The end of the pulse delay is obtained by non-logically multiplying the high level signal of the nose N2 and the low level clock signal CLK at the time when the clock signal CLK falls from the high level to the low level after n feedback is completed. Outputs the output signal PLGB. Thus, the output signal PLGB whose pulse length is extended by nTRC time is output. If the delay time of the feedback circuit is substantially the same as the pulse time of the clock signal CLK, the clock signal PLGB may be generated with only one feedback. However, if the pulse time of the clock signal CLK is long, the delay time of the feedback circuit should be increased or the number of feedback should be increased. Of course, there may be a method of increasing the number of delay elements, but in this case, there is a disadvantage in that the chip area is increased. In order to increase the delay time, a resistor and a capacitor may be additionally connected between the inverter 120 and the inverter 130. In addition, to simplify the circuit configuration, the inverters 120 and 130 and the capacitor 180 may be removed and configured.

In the pulse generator shown in FIG. 4, the PMOS transistor 100 includes an initialization means for initializing a circuit, a NAND gate 110, an inverter 120, 130, 150, and 170, a CMOS transmission gate 160, and a capacitor. Reference numeral 180 denotes a feedback means, and the NAND gate 140 performs a function of a pulse output means, respectively.

The pulse generator of the present invention is configured in the semiconductor memory device to control the read operation and the write operation. That is, the pulse lengths of the read operation and the write operation can be controlled by using the address state transition pulse ATDS and the output signal of the sense amplifier generated as the clock signal CLK, which are generated according to the state transition of the address signal of the semiconductor memory device. have.

Therefore, the pulse generator of the present invention is simple in circuit configuration, so that the area can be reduced during integration and the pulse length can be arbitrarily controlled by the clock signal CLK. In addition, since the pulse length is generated by the feedback loop and the clock signal, it is easy to apply to a circuit that operates quickly.

Claims (6)

A PMOS transistor for applying a power supply voltage to the feedback input terminal in response to a first state of a clock signal, a first NAND gate for NAND combining an input signal and a signal of the feedback input terminal, and a first NAND gate of the first NAND gate; Delay means for outputting an output signal with a predetermined time delay, feedback means for inverting an output signal of the delay means to the feedback input terminal in response to a second state of the clock signal, and a second state of the clock signal. And a pulse output means for reversing and outputting the output signal of the delay means in response. The method of claim 1, wherein the feedback means comprises an inverter for inverting the output signal of the delay means and a switching means for transmitting the output signal of the inverter to the feedback input terminal in response to the second state of the clock signal. Pulse generator characterized in that. 3. The pulse generator according to claim 2, wherein said switching means comprises a CMOS transmission gate which is brought into a conductive state in response to a second state of said clock signal. The pulse generator according to claim 1, wherein the output means comprises a second NAND gate for NAND combining the clock signal and the output signal of the delay means. The pulse generator according to claim 1, wherein the delay means comprises an even number of inverters for sequentially inverting and outputting the output signal of the first NAND gate. 6. The pulse generator as claimed in claim 5, wherein the delay means further comprises a capacitor connected between a common connection point of the inverters and a ground voltage.