KR20070056445A - Apparatus for generating of clock enable signal in semiconductor memory apparatus - Google Patents

Abstract

An apparatus for generating a clock enable signal of a semiconductor memory device is provided to prevent the generation of an undesired internal clock signal and an undesired mode register set in a power down mode, by maintaining the level of a clock enable signal in the power down mode until an address and a command arrive at a latch part. In an apparatus(200) for generating a clock enable signal of a semiconductor memory device, the level of a clock enable signal output in response to a power down enable signal is maintained for a fixed time and then an internal clock generation device is disabled for the fixed time by the clock enable signal. The fixed time is the time until an address and a command arrive at an address latch part and a command latch part, respectively, after an address receiver/buffer and a command receiver/buffer are turned on.

Description

Apparatus for Generating of Clock Enable Signal in Semiconductor Memory Apparatus

1 is a diagram for describing a process of transmitting an address, a command, and a clock signal in a general semiconductor memory device;

2 is a detailed circuit diagram of the clock enable signal generator shown in FIG. 1;

3 and 4 are timing diagrams for explaining an operation in a power down mode in the semiconductor memory device having the clock enable signal generator shown in FIG. 2;

5A and 5B are configuration diagrams of a clock enable signal generator according to the present invention;

6 is a detailed circuit diagram of the pulse generator shown in FIG. 5;

FIG. 7 is a timing diagram for describing an operation in a power down mode in the semiconductor memory device having the clock enable signal generator shown in FIG. 5.

<Description of the symbols for the main parts of the drawings>

110: address receiver / buffer 120: command receiver / buffer

130: clock receiver / buffer 140: address latch unit

150: instruction latch unit 160: internal clock generator

170: clock enable signal latch unit 180: command decoder

190, 200: Clock enable signal generator

210: power down enable signal generator 212: driver

214: latch portion 216: transmission and latch portion

220: delay modeling unit 230: pulse generator

240: switching unit 250: level holding unit

260: buffer

The present invention relates to a clock enable signal generator, and more particularly, to a clock enable signal generator for preventing an unwanted internal clock from occurring in a power down mode of a semiconductor memory device.

As the use of portable electronic devices continues to expand, the need for low power memory is increasing. Semiconductor memory devices are designed to ensure high cell capacity and high speed with low power consumption. Therefore, the semiconductor memory device operates in a power-down mode that uses a minimum of drive current when the data access operation is not performed.

In general, the semiconductor memory device enters a power down mode as the clock enable signal is inactivated, maintains the power down mode, and releases the power down mode when the clock enable signal is activated. The clock enable signal is a signal for interfacing between the external chipset and the semiconductor memory device and becomes a reference signal for determining whether to transfer a clock signal input from the external chipset to the memory device to the memory core region.

That is, the semiconductor memory device transfers the clock signal to the memory core region only when the clock enable signal is activated, and maintains the power down mode in which the clock signal is not transmitted to the memory core region when the clock enable signal is inactivated. do.

1 is a diagram illustrating a process of transmitting an address, a command, and a clock signal in a general semiconductor memory device.

As shown in FIG. 1, the external address signals A0 to An are switched to the internal level in the address receiver / buffer 110 (A0Z_OUT to AnZ_OUT) and then the internal address signals INT_A0 to An through the address latch unit 140. INT_An) and the command (CS, RAS, CAS, WE) is converted to the internal level in the command receiver / buffer 120 (CSZ_OUT, RASZ_OUT, CASZ_OUT, WEZ_OUT). It is outputted as (CS2 / CS2Z, RAS2 / RAS2Z, CAS2 / CAS2Z, WE2 / WE2Z). The output signals CS2 / CS2Z, RAS2 / RAS2Z, CAS2 / CAS2Z, WE2 / WE2Z of the instruction latch unit 150 are input to the instruction decoder 180, and the mode register set MREG and the active signal ACTIVE. The precharge signal PRECHARGE, the write signal WRITE and the read signal READ are output.

In addition, the external clock signal CLK is input to the internal clock generator 160 after being converted to the internal level from the clock receiver / buffer 130 (CLKZ_OUT), and the internal clock generator 160 receives the clock receiver / buffer ( The internal clock signal INT_CLK and the clock enable signal latch unit 170 control signal CLKZ_CKE are output by inputting the clock signal CLKZ_OUT and the pulse generation signal PULSE_GEN which are level-converted at 130.

In addition, the external clock enable signal CKE is converted into the internal level in the clock receiver / buffer 130 (CKEZ_OUT) and then input to the clock enable signal latch unit 170, and the clock enable signal latch unit 170. The internal clock enable signal CKE2 / CKE2Z is output according to the control signal CLKZ_CKE output from the internal clock generator 160.

Subsequently, the internal clock enable signal CKE2 / CKE2Z, which is an output signal of the clock enable signal latch unit 170, is input to the clock enable signal generator 190, and the clock enable signal generator 190 is clocked. The clock enable signal CKEZ_CLK_EN and the receiver / buffer driving signal CKEZ_CA_EN are output according to the signal CLKZ_OUT and the power-up signal PWRUP. The receiver / buffer driving signal CKEZ_CA_EN controls the on / off of the address receiver / buffer 110 and the command receiver / buffer 120.

In the power-down mode, the external clock enable signal CKE transitions to a low level, whereby the level-converted clock enable signal CKEZ_OUT output from the clock receiver / buffer 130 becomes a high level. In addition, the clock enable signal latch unit 170 latches the level of the clock enable signal CKEZ_OUT, which is level-converted, by the control signal CLKZ_CKE output from the internal clock generator 160, thereby causing the internal clock enable signal ( CKE2 and CKE2Z), which are input to the clock enable signal generator 190 and output as the clock enable signal CKE_CLK_EN.

FIG. 2 is a detailed circuit diagram of the clock enable signal generator shown in FIG. 1.

When the internal clock enable signal CKE2Z becomes high in the power-down mode, the first MOS transistor Q1 is turned on and the second MOS transistor Q2 is turned off, and at the initial power-up, the third MOS transistor ( Q3) is turned off and the fourth MOS transistor Q4 is turned on so that a high level signal is input to the latch unit 192.

The low level signal CKEZ_CA_EN_PRE output from the latch unit 192 is inverted and used as the receiver / buffer driving signal CKEZ_CA_EN, and the address receiver / buffer 110 and the command receiver / buffer 120 are turned according to the signal. Is off.

In addition, the output signal of the latch unit 192 is input to the transmission and latch unit 194 driven by the level-converted clock signals CLK_0UT and CLKZ_OUT output from the clock receiver / buffer 130 to transmit and latch the unit. The power down enable signal NET may be output as a signal having a pulse having a predetermined width through 194.

On the other hand, the inverted signal CKEZ_CLK_EN_PRE of the power down enable signal NET is delayed and output from the delay modeling unit 196 (CKEZ_CLK_EN_PRE_DELAY), and the comparator 198 is an inverted signal of the power down enable signal NET ( The clock enable signal CKEZ_CLK_EN is output by comparing the CKEZ_CLK_EN_PRE and its delay signal CKEZ_CLK_EN_PRE_DELAY. In this case, the delay modeling unit 196 is configured to latch the on / off time (X) of the address receiver / buffer 110 and the instruction receiver / buffer 120 and the output signals of the receiver / buffer 110 and 120 respectively. Model the time (Y) until delivery to the unit (140, 150).

When the clock enable signal CKEZ_CLK_EN is activated, the internal clock signal INT_CLK is generated, and when the signal level reaching the address latch unit 140 and the instruction latch unit 150 is the level for the mode register set MRS. The command decoder 180 configures an internal MRS.

3 and 4 are timing diagrams for describing an operation in a power down mode in the semiconductor memory device including the clock enable signal generator shown in FIG. 2.

First, FIG. 3 shows a case in which the power-down mode is maintained and escaped during 1 tCK. As illustrated, when the external clock enable signal CKE transitions to a low level and enters a power down mode, the internal clock enable signal CKE2Z goes high and the receiver / buffer drive signal CKEZ_CA_EN goes high. The address receiver / buffer 110 and the command receiver / buffer 120 are turned off by being outputted as.

The power down enable signal NET is output as a pulse signal having a predetermined width from the transmission and latch unit 194, and the inversion signal CKEZ_CLK_EN_PRE and the delay modeling unit 196 of the power down enable signal NET are output. The clock enable signal CKEZ_CLK_EN is output by comparing the delayed signal CKEZ_CLK_EN_PRE_DELAY.

At this time, the power-down enable signal NET is disabled, and the delayed power-down enable signal CKEZ_CLK_PRE_DELAY is disabled after being delayed by the delay modeling unit 196, and the inverted delay with the inverted power-down enable signal CKEZ_CLK_PRE is performed. The clock enable signal CKE_CLK_EN is output by comparing the power-down enable signal CKEZ_CLK_PRE_DELAY, which is delayed after the inverted power-down enable signal CLEZ_CLK_PRE is disabled as shown in FIG. 3. There is a problem that an unwanted internal clock signal (INT_CLK) occurs during the process.

The mode register setting is performed by an instruction reaching the instruction latch unit 150 by the invalid internal clock signal INT_CLK. Since the mode register set is also an invalid signal, the semiconductor memory device operates abnormally.

FIG. 4 shows a case in which the power-down mode is maintained and escaped for 2 tCK, and in this case, an unwanted internal clock signal INT_CLK is also applied while delaying the inverted power-down enable signal CKEZ_CLK_PRE after it is disabled. Occurs, which causes a problem of invalid MRS.

This problem may occur frequently in power down periods depending on the external environment (Process, Voltage, Temperature, PVT) and frequency of the semiconductor memory device, and the problem is exacerbated in the case of a high frequency semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and there is a technical problem to provide a clock enable signal generator capable of operating a semiconductor memory device normally by preventing an internal clock from being generated in a power-down mode. .

Another technical problem of the present invention is to maintain the level of the clock enable signal in the power down mode for the time that the address and the instruction reach the latch, so that an unwanted internal clock signal and mode register set are not generated in the power down mode. There is.

In accordance with an aspect of the present invention, a clock generation device maintains a level of a clock enable signal output in response to a power down enable signal for a predetermined time, and is controlled by the clock enable signal. And disabling the internal clock generator for the specified time.

In addition, the clock enable signal generating apparatus according to another embodiment of the present invention includes a power down enable signal generator for generating a power down enable signal and a receiver / buffer driving signal by the internal clock enable signal and the clock signal; A delay modeling unit configured to delay the power down enable signal by a predetermined time; A pulse generator configured to generate a power down release signal for escaping a power down mode in response to an output signal of the delay modeling unit; A switching unit controlled according to a power down enable signal output from the power down enable signal generator and a power down release signal output from the pulse generator; And a level maintaining unit configured to output a clock enable signal for maintaining or escaping a power-down mode according to the output signal of the switching unit.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

5A and 5B are configuration diagrams of a clock enable signal generator according to the present invention.

The clock enable signal generator 200 according to the present invention is enabled by the power-down enable signal NET1 and is applied to a signal generated by the signal NET1D, which is a delay modeled power-down enable signal NET1. The clock enable-bar signal CKEZ_CLK_EN, which is disabled by operation, is output. Here, the power-down enable signal NET1 is delayed modeled for the time that the address and command receiver / buffer is turned on, so that the address and command reaches each latch, and the clock enable-bar signal CKEZ_CLK_EN is turned on. While enabled, the internal clock generator is disabled to prevent internal clock generation in power-down mode.

When the clock enable signal generator 200 outputs the power down enable signal NET1 and then outputs a pulse generated by a signal NET1D delayed modeling the power down enable signal NET1. It further includes a level holding unit for maintaining the level of the clock enable-bar signal (CKEZ_CLK_EN), and further includes a buffer for transmitting the clock enable-bar signal (CLEZ_CLK_EN) to the internal clock generator, etc. at the output terminal of the level holding unit. .

5A is a block diagram of a clock enable signal generator according to the present invention.

Referring to FIG. 5A, the clock enable signal generator 200 according to the present invention is powered by internal clock enable signals CKE2Z and CKE2 and a clock signal CLKZ_OUT level-converted by the clock receiver / buffer 130. The power down enable signal generator 210 generating the down enable signal NET1 and the receiver / buffer driving signal CLEZ_CA_EN, and the delay modeling unit 220 for delaying the power down enable signal NET1 by a predetermined time. In response to the output signal NET1D of the delay modeling unit, a pulse generator 230 generating a signal for escaping the power-down mode and an output signal and the pulse generator 230 of the power-down enable signal generator 210 are generated. A level maintaining unit 250 outputting a clock enable-bar signal CKEZ_CLK_EN for maintaining or escaping a power-down mode according to the output signal of the switching unit 240 and the switching unit 240 controlled according to the output signal of ), And level It may further include a buffer 260 connected to the output terminal of the branch 250 for transmitting the clock enable-bar signal CKEZ_CLK_EN to other devices.

Here, the level maintaining unit 250 enables the clock enable-bar signal CKEZ_CLK_EN under the control of the switching unit 240 while the delay modeling unit 220 delays the power-down enable signal NET1. When the delay time of the delay modeling unit 220 elapses, the clock enable-bar signal CKEZ_CLK_EN is disabled by the control of the switching unit 240.

Referring to FIG. 5B, the power down enable signal generator 210 starts an operation of the clock enable signal generator in accordance with internal clock enable signals CKE2 and CKE2Z and a power-up signal PWRUP signal. The latch unit 214 for latching the output signal of the driver 212 and the driver 212 to output the receiver / buffer drive signal CKEZ_CA_EN and the power down enable signal NET1 from the output signal of the latch unit 214. And a transmit and latch portion 216 for generating.

Here, the driving unit 212 is connected between the power supply terminal VDD and the output terminal and driven by the inverted signal of the internal clock enable-bar signal CKE2Z. The first MOS transistor Q11, the output terminal and the ground terminal ( Between the second and third MOS transistors Q12 and Q13 and the power supply terminal VDD and the output terminal, which are connected in series between the VSSs and driven by the internal clock enable signal CKE2 and the power-up signal PWRUP, respectively. A fourth MOS transistor Q14 is connected and driven by the power-up signal PWRUP.

Since the internal clock enable signal CKE2Z transitions to the high level in the power-down mode, the first MOS transistor Q11 is turned on and the second MOS transistor Q12 is turned off. In addition, since the power-up signal PWRUP is at the low level at the initial power-up, the third MOS transistor Q13 is turned off and the fourth MOS transistor Q14 is turned on, so that the output signal of the driver 212 is high. It becomes a level. The output signal of the driver 212 is latched to the low level by the latch unit 214, and a high level receiver / buffer drive signal CKEZ_CA_EN is output, whereby the address receiver / buffer and the command receiver / buffer are turned off. do.

Here, the first and fourth MOS transistors may be configured as P-type MOS transistors, and the second and third MOS transistors may be configured as N-type MOS transistors.

The output signal of the latch unit 214 passes through the transmission and latch unit 216 and is output as a power down enable signal NET1. The transmission and latch unit 216 is a level-converted clock signal CLKZ_OUT and The inverted signal CLK_OUT is driven to invert the output signal of the first transfer gate T11 and the first transfer gate T11 that transmits the output signal of the latch unit, and outputs the power-down enable signal NET1. Driven by the first inverting element IV11, the second inverting element IV12 for inverting the output signal of the first inverting element IV11, the level-converted clock signal CLKZ_OUT, and the inverting signal CLK_OUT The second transmission gate T12 outputs an output signal of the inversion element IV12 to the first inversion element IV11.

As the output signal of the latch unit 214 becomes low level, when the output signal of the transmission and latch unit 216 becomes high level, that is, when the power-down enable signal NET1 is enabled, the switching unit 240 The first MOS transistor Q21 is turned on, and the output level of the switching unit 240 becomes low, and the high level clock enable-bar signal CKEZ_CLK_EN is output through the level maintaining unit 250.

The switching unit 240 is connected between the output terminal and the ground terminal VSS and is connected between the first MOS transistor Q21 and the power supply terminal VDD and the output terminal driven by the power-down enable signal NET1. And a second MOS transistor Q22 driven by the output signal DIS_P of the pulse generator 230. In addition, the level maintaining unit 250 inputs an output signal and a power-up signal of the switching unit 240, and outputs a clock enable-bar signal CKE_CLK_EN to the logic element 252 and the logic element 252. And an inverting element 254 that inverts the output signal of the signal to provide an output terminal of the switching unit 240.

As such, the clock enable signal generator 200 outputs a high level clock enable-bar signal CKE_CLK_EN while the output signal of the switching unit 240 is at a low level.

On the other hand, the power down enable signal NET1 is input to the delay modeling unit 220 and delayed for a predetermined time, which is a delay time until the address and command receiver / buffer are turned on and the address and command reach each latch unit. It is preferable to set the time. In other words, when the address and the instruction reach the respective latch portions, the power down mode enable signal is delayed to escape from the power down mode.

The delayed power-down enable signal NET1D, which is an output signal of the delay modeling unit 220, is input to the pulse generator 230, and the pulse generator 230 is configured to disable the delayed power-down enable signal NET1D. A power down release signal DIS_P that is enabled at a time point, that is, when the power down mode is released, is output.

When the power down release signal DIS_P is enabled, the second MOS transistor Q22 of the switching unit 240 is turned on and the power down enable signal NET1 that is disabled before the delayed power down enable signal NET1D. ), The first MOS transistor Q21 is turned off, and the output signal of the switching unit 240 is at a high level.

At this time, the power-up signal PWRUP also becomes a high level, and the level maintaining unit 250 outputs a low level clock enable-bar signal CKEZ_CLK_EN to release the power-down mode.

FIG. 6 is a detailed circuit diagram of the pulse generator shown in FIG. 5.

As illustrated, the pulse generator 230 uses the inverted signal of the delayed power-down enable signal NET1D as the first input and the delayed signal of the delayed power-down enable signal NET1D as the second input. And a logic element 232 for outputting a pulse signal having a predetermined width as the power down release signal DIS_P at a time when the delayed power down enable signal NET1D is disabled.

Here, the first input signal may be inverted by the inverting element 234, and the second input signal may be delayed by a desired time by the delay unit 236 having an even number of inverting elements connected in series. .

FIG. 7 is a timing diagram for describing an operation in a power down mode in the semiconductor memory device having the clock enable signal generator shown in FIG. 5.

As shown, the power-down enable signal NET1 is enabled to enter the power-down mode and the high level clock enable-bar signal CKE_CLK_EN from the level maintaining unit 250 under the control of the switching unit 240. ) Is outputted, and a power-down mode release signal DIS_P is output when the signal NET1D delay-modeling the power-down enable signal NET1 is disabled, and under the control of the switching unit 240. Allow the clock enable-bar signal CKEZ_CLK_EN to transition to the low level to exit the power down mode.

At this time, the clock enable-bar signal CKEZ_CLK_EN is maintained at that level until the delay modeled power-down enable signal NET1D is disabled, thereby preventing an unwanted internal clock from being generated in the power-down mode. As a result, malfunction of the semiconductor memory device can be prevented in advance.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, in controlling the clock enable signal for determining whether the semiconductor memory device is in a power down mode, the clock enable signal is powered down until the delay modeled signal of the power down enable signal is disabled. By maintaining this level, unnecessary internal clocks can be prevented from occurring in the power-down mode.

In addition, since the power-down mode is maintained regardless of the frequency of the semiconductor memory device, operation reliability of the high speed semiconductor memory device can be ensured.

Claims (14)

And maintaining the level of the clock enable signal output in response to the power down enable signal for a predetermined time, thereby disabling the internal clock generator for the specified time by the clock enable signal. Clock enable signal generator. The method of claim 1, And the specified time is a time at which an address receiver / buffer and an instruction receiver / buffer are turned on so that an address and an instruction reach an address latch section and an instruction latch section, respectively. The method of claim 1, The clock enable signal generator is configured to output the clock enable signal until the pulse signal is output in response to a signal delaying the power down enable signal for the predetermined time after the power down enable signal is output. And a level holding unit for holding a level. The method of claim 3, wherein The clock enable signal generator is connected to an output terminal of the level maintaining unit, the clock enable signal generator of the semiconductor memory device, characterized in that it further comprises a buffer for transmitting the clock enable signal to other devices. A power down enable signal generator configured to generate a power down enable signal and a receiver / buffer drive signal by the internal clock enable signal and the clock signal; A delay modeling unit configured to delay the power down enable signal by a predetermined time; A pulse generator configured to generate a power down release signal for escaping a power down mode in response to an output signal of the delay modeling unit; A switching unit controlled according to a power down enable signal output from the power down enable signal generator and a power down release signal output from the pulse generator; And A level maintaining unit outputting a clock enable signal for maintaining or escaping a power-down mode according to the output signal of the switching unit; A clock enable signal generator of a semiconductor memory device comprising a. The method of claim 5, The clock enable signal generator further comprises a buffer connected to an output terminal of the level maintaining unit and configured to transmit the clock enable signal to another device. The method of claim 5, The level maintaining unit enables the clock enable signal to be enabled by the control of the switching unit while delaying the power down enable signal by the delay modeling unit. When the delay time of the delay modeling unit has elapsed, the control unit controls the switching unit. And enabling the clock enable signal to be disabled. The method of claim 5, The power down enable signal generator may include a driver configured to initiate an operation of the clock enable signal generator according to an internal clock enable signal and a power-up signal signal; A latch unit for latching an output signal of the driver to output a receiver / buffer driving signal; And A transmission and latch unit for generating a power down enable signal from an output signal of the latch unit; A clock enable signal generator of a semiconductor memory device comprising a. The method of claim 8, A first transmission gate driven by the clock signal to transmit and output the latch signal of the latch unit; A first inversion device for outputting a power down enable signal by inverting an output signal of the first transmission gate; A second inversion element inverting the output signal of the first inversion element; And A second transfer gate driven by the clock signal to output an output signal of the second inverting element to the first inverting element; A clock enable signal generator of a semiconductor memory device comprising a. The method of claim 5, A first MOS transistor connected between a power supply terminal and an output terminal and driven by an output signal of the pulse generator; And A second MOS transistor connected between the output terminal and the ground terminal and driven by the power down enable signal; A clock enable signal generator of a semiconductor memory device comprising a. The method of claim 5, A logic device configured to output the clock enable signal by inputting an output signal and a power-up signal of the switching unit; And An inverting element inverting an output signal of the logic element and providing the inverted signal to an output terminal of the switching unit; A clock enable signal generator of a semiconductor memory device comprising a. The method of claim 11, And the logic element is a NAND gate. The method of claim 5, The delay modeling unit turns on an address receiver / buffer and an instruction receiver / buffer by the receiver / buffer driving signal to delay the power-down enable signal until an address and an instruction reach the address latch unit and the instruction latch unit, respectively. And a clock enable signal generator of the semiconductor memory device. The method of claim 5, The pulse generating unit uses the inverted signal of the delay modeling unit output signal as the first input signal and the delay signal of the delay modeling unit output signal as the second input, and is predetermined at a time when the output signal of the delay modeling unit is disabled. And a logic element for outputting a pulse signal having a width as a power down release signal.

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