JP2003081695A - SiC SEMICONDUCTOR AND METHOD OF EPITAXIALLY GROWING SiC - Google Patents
SiC SEMICONDUCTOR AND METHOD OF EPITAXIALLY GROWING SiCInfo
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- JP2003081695A JP2003081695A JP2001270242A JP2001270242A JP2003081695A JP 2003081695 A JP2003081695 A JP 2003081695A JP 2001270242 A JP2001270242 A JP 2001270242A JP 2001270242 A JP2001270242 A JP 2001270242A JP 2003081695 A JP2003081695 A JP 2003081695A
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- sic
- wafer
- buffer layer
- epitaxial growth
- semiconductor
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、SiC半導体
と、SiCエピタキシャル成長方法に関する。TECHNICAL FIELD The present invention relates to a SiC semiconductor and a SiC epitaxial growth method.
【0002】[0002]
【従来の技術】基板になるシリコンと、そのシリコン基
板上にエピタキシャル成長させるSiCとの間には、格
子不整合がある。そのため、ミスフィット転位による結
晶欠陥が多数発生し、デバイス作成時に問題となってい
る。2. Description of the Related Art There is a lattice mismatch between silicon that becomes a substrate and SiC that is epitaxially grown on the silicon substrate. As a result, many crystal defects are generated due to misfit dislocations, which is a problem during device fabrication.
【0003】そのため、格子定数の違いによる結晶欠陥
を抑制する技術の導入が重要になる。Therefore, it is important to introduce a technique for suppressing crystal defects due to the difference in lattice constant.
【0004】シリコン基板の表面を炭化水素ガスで炭化
し、これをバッファー層としてSiCを成長させる方法
が知られている。A method is known in which the surface of a silicon substrate is carbonized with a hydrocarbon gas and SiC is grown using this as a buffer layer.
【0005】[0005]
【発明が解決しようとする課題】この従来の方法による
と、シリコン基板中のSi原子が炭化処理により基板表
面に持ち去られ、シリコン基板中に空孔が生じ、シリコ
ン基板が荒れてしまう現象が見られる。According to this conventional method, the phenomenon that Si atoms in the silicon substrate are carried away to the substrate surface by the carbonization treatment and voids are formed in the silicon substrate, and the silicon substrate is roughened, is found. To be
【0006】本発明の目的は、格子定数の違いによるミ
スフィット転位を抑制し、しかも、品質の高いSiC半
導体とSiCエピタキシャル成長方法を提供することで
ある。An object of the present invention is to provide a high-quality SiC semiconductor and a SiC epitaxial growth method that suppresses misfit dislocations due to a difference in lattice constant.
【0007】[0007]
【課題を解決するための手段】本発明の解決手段を例示
すると、次のとおりである。The solution means of the present invention is exemplified as follows.
【0008】(1)Siウェーハの表面に、BPのバッ
ファー層を介して、3C−SiCがエピタキシャル成長
により形成されていることを特徴とするSiC半導体。(1) A SiC semiconductor characterized in that 3C-SiC is formed by epitaxial growth on the surface of a Si wafer via a BP buffer layer.
【0009】(2)BPが閃亜鉛鉱型の単結晶である前
述のSiC半導体。(2) The aforementioned SiC semiconductor in which BP is a zinc blende type single crystal.
【0010】(3)シリコン基板上にバッファー層を介
して単結晶SiC膜を形成したSiCウェーハ。(3) A SiC wafer in which a single crystal SiC film is formed on a silicon substrate via a buffer layer.
【0011】(4)バッファー層が閃亜鉛鉱型結晶のB
Pである前述のSiCウエーハ。(4) The buffer layer is B of zinc blende type crystal
The aforementioned SiC wafer which is P.
【0012】(5)基板となるSiウェーハの上に3C
−SiCをエピタキシャル成長させる際に、BPをバッ
ファー層として介在させることを特徴とするSiCエピ
タキシャル成長方法。(5) 3C on the Si wafer to be the substrate
-A SiC epitaxial growth method characterized in that when epitaxially growing SiC, BP is interposed as a buffer layer.
【0013】(6)BPが閃亜鉛鉱型の単結晶である前
述のSiCエピタキシャル成長方法。(6) The above-mentioned SiC epitaxial growth method in which BP is a zinc blende type single crystal.
【0014】[0014]
【発明の実施の形態】この発明は、Siに比べて半導体
機能として優れた性能を持つSiC半導体とエピタキシ
ャル成長方法を提供するものである。BEST MODE FOR CARRYING OUT THE INVENTION The present invention provides an SiC semiconductor having an excellent performance as a semiconductor function as compared with Si and an epitaxial growth method.
【0015】SiC半導体とくに3C−SiC半導体
は、主にSi(シリコン)基板上に3C−SiCをエピ
タキシャル成長させることにより製造される。SiC semiconductors, especially 3C-SiC semiconductors, are manufactured mainly by epitaxially growing 3C-SiC on a Si (silicon) substrate.
【0016】このようなエピタキシャル成長において
は、シリコン基板の結晶性を成膜層が受け継ぐ。それゆ
え、良質な結晶を得る上で基板の荒れは避けるべきであ
る。In such epitaxial growth, the film formation layer inherits the crystallinity of the silicon substrate. Therefore, the roughening of the substrate should be avoided in order to obtain a good quality crystal.
【0017】そこで、基板の荒れをもたらさないよう
に、適当な物質によるバッファー層を設けることが好ま
しいのである。Therefore, it is preferable to provide a buffer layer of an appropriate substance so as not to cause the roughness of the substrate.
【0018】たとえば、基板となるSiウェーハ上に3
C−SiCをエピタキシャル成長させる際に、閃亜鉛鉱
型単結晶のBP(リン化ホウ素)をバッファー層として
用いる。それにより、結晶欠陥を減少させる。For example, 3 is formed on a Si wafer which is a substrate.
When C-SiC is epitaxially grown, zinc blende type single crystal BP (boron phosphide) is used as a buffer layer. Thereby, crystal defects are reduced.
【0019】閃亜鉛鉱型結晶であるBP(リン化ホウ
素)の格子定数は、4.538オングストロームであ
り、3C−SiCの4.358オングストロームとほぼ
同等であり、格子不整合によるミスフィット転位を抑制
できる。また、熱膨脹率もほぼ同等である。The lattice constant of BP (boron phosphide), which is a zinc blende type crystal, is 4.538 angstroms, which is almost the same as 4.358 angstroms of 3C-SiC, and misfit dislocations due to lattice mismatching occur. Can be suppressed. Also, the coefficient of thermal expansion is almost the same.
【0020】また、BPは、Siと格子定数にして1
6.4%の違いがあるものの、BPはSi上にヘテロエ
ピタキシャル成長できるものである。BP has a lattice constant of 1 with Si.
BP can be heteroepitaxially grown on Si with a difference of 6.4%.
【0021】まず、Si基板上にBPをエピタキシャル
成長させ、続いて、3C−SiCを成長させることによ
り、ミスフィット転位を抑制した結晶を得ることができ
る。First, by epitaxially growing BP on a Si substrate and then growing 3C-SiC, a crystal in which misfit dislocations are suppressed can be obtained.
【0022】[0022]
【実施例】以下に、好適な実施例の1つを説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One of the preferred embodiments will be described below.
【0023】(1)基板のSi(100)もしくは(1
11)を水素雰囲気中で1000℃以上に加熱すること
により、基板の自然酸化膜を除去する。(1) Substrate Si (100) or (1
By heating 11) above 1000 ° C. in a hydrogen atmosphere, the native oxide film on the substrate is removed.
【0024】(2)キャリアガスを水素として、B原料
のBCl3 とP原料のPCl3 を反応管に流し、低温成
長を約200〜500℃で30分程度行う。[0024] As hydrogen (2) carrier gas, flowing BCl 3 and PCl 3 in P raw material B material in the reaction tube, for about 30 minutes at about 200 to 500 ° C. The low temperature growth.
【0025】(3)低温成長終了時にBPの原料供給を
止め、BPの結晶成長温度である900〜1200℃ま
で昇温する。(3) At the end of the low temperature growth, the supply of the BP raw material is stopped and the temperature is raised to 900 to 1200 ° C. which is the BP crystal growth temperature.
【0026】(4)900〜1200℃の成長温度にな
ったら、BPの原料供給を開始し、そのまま30分以上
保持し、BP層を1〜5μm程度成膜する。(4) When the growth temperature reaches 900 to 1200 ° C., the supply of the BP raw material is started and maintained for 30 minutes or longer to form a BP layer of about 1 to 5 μm.
【0027】(5)所定の結晶成長時間を終えたのち、
BPの原料供給を停止し、その温度のまま30分程度保
持する。(5) After completing the predetermined crystal growth time,
The supply of the BP raw material is stopped and the temperature is maintained for about 30 minutes.
【0028】(6)ついで、SiCの低温成長温度であ
る200〜500℃にし、原料であるメチルシランの供
給を開始し、10分程度保持する。(6) Next, the low temperature growth temperature of SiC is set to 200 to 500 ° C., the supply of methylsilane as a raw material is started, and the temperature is maintained for about 10 minutes.
【0029】(7)3C−SiCの結晶成長温度である
800〜1200℃程度にし、そのまま30分以上保持
し、SiC層を10〜30μm成膜する。(7) The crystal growth temperature of 3C-SiC is set to about 800 to 1200 ° C. and kept for 30 minutes or longer to form a SiC layer of 10 to 30 μm.
【0030】(8)3C−SiC結晶成長時間が終了し
た時点でメチルシラン原料供給を停止し、その温度のま
ま30分程度保持する。(8) The methylsilane raw material supply is stopped at the time when the 3C-SiC crystal growth time ends, and the temperature is maintained for about 30 minutes.
【0031】上記工程(1)〜(8)により製造した3
C−SiC半導体(とくにその結晶)と比較するため
に、BP層を介さないで、すなわち上記工程(2)から
(5)を除いた条件で、Si基板上に3C−SiC結晶
を成長させた3C−SiC半導体の製造を試みた。これ
らを比較したところ、BPのバッファー層を設けて作成
した3C−SiC半導体の結晶は、格子欠陥違いによる
ミスフィット転位が良好に抑制されており、高品質な結
晶になっていたが、BPのバッファ層なしで製造したも
のは、多結晶SiCが形成されるのみで、単結晶SiC
を製造することはできなかった。3 produced by the above steps (1) to (8)
For comparison with a C-SiC semiconductor (particularly its crystal), a 3C-SiC crystal was grown on a Si substrate without a BP layer, that is, under the conditions in which the step (2) to (5) were excluded. An attempt was made to manufacture a 3C-SiC semiconductor. Comparing these, the 3C-SiC semiconductor crystal prepared by providing the BP buffer layer had high quality crystals in which misfit dislocations due to the difference in lattice defects were satisfactorily suppressed. The one manufactured without the buffer layer only forms polycrystalline SiC,
Could not be manufactured.
【0032】本発明は、実施例に限定されるものではな
い。たとえば、原料ガスとしては、塩化物の他にも、水
素化物、有機金属原料など、種々のものが利用できる。The present invention is not limited to the embodiments. For example, as the source gas, various substances such as hydride, organic metal source material, etc. can be used in addition to chloride.
【図1】(a)は、Siウェーハ上に、SiCを直接成
長させた場合の様子を示す模式図。(b)は、本発明の
好適な実施例による3C−SiC単結晶の成長を示す模
式図。FIG. 1A is a schematic view showing a state where SiC is directly grown on a Si wafer. FIG. 3B is a schematic diagram showing growth of a 3C-SiC single crystal according to a preferred embodiment of the present invention.
フロントページの続き (72)発明者 中西 秀夫 神奈川県秦野市曽屋30番地 東芝セラミッ クス株式会社開発研究所内 (72)発明者 寺嶋 一高 神奈川県海老名市中野206−3 Fターム(参考) 4G077 AA03 BE08 DB05 DB09 ED06 EF02 HA06 TK01 5F045 AA03 AB06 AB09 AC03 AD06 AD07 AD08 AD09 AD12 AD13 AD14 AD15 AD16 AF03 BB12 DA53 EB15 Continued front page (72) Inventor Hideo Nakanishi 30 Soya, Hadano City, Kanagawa Prefecture Kusu Co., Ltd. Development Laboratory (72) Inventor Kazutaka Terashima 206-3 Nakano, Ebina City, Kanagawa Prefecture F-term (reference) 4G077 AA03 BE08 DB05 DB09 ED06 EF02 HA06 TK01 5F045 AA03 AB06 AB09 AC03 AD06 AD07 AD08 AD09 AD12 AD13 AD14 AD15 AD16 AF03 BB12 DA53 EB15
Claims (6)
ー層を介して、3C−SiCがエピタキシャル成長によ
り形成されていることを特徴とするSiC半導体。1. A SiC semiconductor, wherein 3C-SiC is formed by epitaxial growth on the surface of a Si wafer via a BP buffer layer.
特徴とする請求項1に記載のSiC半導体。2. The SiC semiconductor according to claim 1, wherein BP is a zinc blende type single crystal.
単結晶SiC膜が形成されていることを特徴とするSi
Cウェーハ。3. A single crystal SiC film is formed on a silicon substrate via a buffer layer.
C wafer.
あることを特徴とする請求項3に記載のSiCウェー
ハ。4. The SiC wafer according to claim 3, wherein the buffer layer is BP of zinc blende type crystal.
iCをエピタキシャル成長させる際に、BPをバッファ
ー層として介在させることを特徴とするSiCエピタキ
シャル成長方法。5. A 3C-S film is formed on a Si wafer as a substrate.
A SiC epitaxial growth method characterized by interposing BP as a buffer layer when epitaxially growing iC.
特徴とする請求項5に記載のSiCエピタキシャル成長
方法。6. The SiC epitaxial growth method according to claim 5, wherein BP is a zinc blende type single crystal.
Priority Applications (5)
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JP2001270242A JP4766642B2 (en) | 2001-09-06 | 2001-09-06 | SiC semiconductor and SiC epitaxial growth method |
PCT/JP2002/009035 WO2003023095A1 (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and its manufacturing method |
TW091120310A TWI222104B (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and method of fabricating the same |
US10/432,597 US6936490B2 (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and its manufacturing method |
EP02765418A EP1424409A4 (en) | 2001-09-06 | 2002-09-05 | Semiconductor wafer and its manufacturing method |
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JP2001270242A JP4766642B2 (en) | 2001-09-06 | 2001-09-06 | SiC semiconductor and SiC epitaxial growth method |
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JP2003081695A true JP2003081695A (en) | 2003-03-19 |
JP4766642B2 JP4766642B2 (en) | 2011-09-07 |
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Cited By (4)
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---|---|---|---|---|
JP2007095858A (en) * | 2005-09-28 | 2007-04-12 | Toshiba Ceramics Co Ltd | Substrate for compound semiconductor device, and compound semiconductor device using it |
JP2010092917A (en) * | 2008-10-03 | 2010-04-22 | Seiko Epson Corp | Method of manufacturing semiconductor device, and semiconductor device |
US20110079793A1 (en) * | 2009-10-02 | 2011-04-07 | Seiko Epson Corporation | Semiconductor substrate and its manufacturing method |
CN104871060A (en) * | 2012-12-17 | 2015-08-26 | 旭硝子株式会社 | Optical element, optical system, and imaging device |
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JPH02275682A (en) * | 1989-01-13 | 1990-11-09 | Toshiba Corp | Compound semiconductor material and semiconductor element using same and manufacture thereof |
JPH02229476A (en) * | 1989-03-01 | 1990-09-12 | Toyoda Gosei Co Ltd | Vapor growth of gallium nitride compound semiconductor and light-emitting element |
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JP2000351692A (en) * | 1999-06-11 | 2000-12-19 | Toshiba Ceramics Co Ltd | Si WAFER FOR GROWING GaN SEMICONDUCTOR CRYSTAL, WAFER FOR GaN LIGHT EMISSION ELEMENT USING THE SAME Si WAFER AND THEIR PRODUCTION |
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JP2007095858A (en) * | 2005-09-28 | 2007-04-12 | Toshiba Ceramics Co Ltd | Substrate for compound semiconductor device, and compound semiconductor device using it |
JP2010092917A (en) * | 2008-10-03 | 2010-04-22 | Seiko Epson Corp | Method of manufacturing semiconductor device, and semiconductor device |
US20110079793A1 (en) * | 2009-10-02 | 2011-04-07 | Seiko Epson Corporation | Semiconductor substrate and its manufacturing method |
JP2011077478A (en) * | 2009-10-02 | 2011-04-14 | Seiko Epson Corp | Semiconductor and method for manufacturing the same |
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CN104871060A (en) * | 2012-12-17 | 2015-08-26 | 旭硝子株式会社 | Optical element, optical system, and imaging device |
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