JP4301592B2 - Manufacturing method of substrate with nitride semiconductor layer - Google Patents
Manufacturing method of substrate with nitride semiconductor layer Download PDFInfo
- Publication number
- JP4301592B2 JP4301592B2 JP14032198A JP14032198A JP4301592B2 JP 4301592 B2 JP4301592 B2 JP 4301592B2 JP 14032198 A JP14032198 A JP 14032198A JP 14032198 A JP14032198 A JP 14032198A JP 4301592 B2 JP4301592 B2 JP 4301592B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nitride layer
- silicon nitride
- silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】
【発明の属する技術分野】
本発明は光電子デバイスや半導体発光素子に用いられる窒化物半導体層付き基板の製造方法に関する。更に詳しくは単結晶シリコン基板上に窒化物半導体層を形成した窒化物半導体層付き基板の製造方法に関するものである。
【０００２】
【従来の技術】
従来より、単結晶シリコン基板上にＧａＮ、ＩｎＮ、ＡｌＮ等の窒化物半導体層を形成する方法として、単結晶シリコン基板上に窒化物半導体層を直接形成する第１の方法が知られている。この方法には低温で窒化物半導体バッファ層を形成してこのバッファ層上に高温で窒化物半導体層を形成する方法が含まれる。
また別の第２の方法として、単結晶シリコン基板上にシリコンカーバイド（ＳｉＣ）やヒ素化ガリウム（ＧａＡｓ）からなる中間層を形成し、その上に窒化物半導体層を形成する方法が知られている。
【０００３】
しかし上記第１の方法では、図１８に示すように単結晶シリコン基板１上に例えばＧａＮ層２を直接形成した場合、ＧａＮ層２の形成時にシリコン基板１表面の一部にランダムにアモルファス窒化シリコン層３が形成される。このアモルファス窒化シリコン層３は、シリコン基板１とＧａＮ層２の界面の平坦度を悪化させ、ＧａＮ層２に結晶欠陥を生じさせ、更にはＧａＮ層の多結晶化の原因となる等の問題がある。このように形成されたＧａＮ層２の発光特性を示すフォトルミネッセンスを測定した場合には、３．４ｅＶにフォトルミネッセンスのピークは現れるが、強度が低く、またそのピークの半値幅が広いため、発光特性が劣る。
また上記第２の方法では窒化物半導体層を構成する元素以外の元素の原料ソースが必要となり、窒化物半導体層を連続的に成長させることが困難である。また上記原料ソースからの元素が窒化物半導体層中に不純物として混入する問題が生じる。それを防ぐためにはＳｉＣやＧａＡｓ等からなる中間層を形成した後、製造装置の内部を十分にクリーニングすることが必要になる。
【０００４】
この点を解決するために、単結晶シリコン基板上に窒化シリコン膜のような絶縁膜を介して窒化ガリウム系化合物半導体層を形成する窒化物半導体発光素子の製造方法が開示されている（特開平８−６４９１３）。この窒化シリコン膜は、基板表面の自然酸化膜を除去した単結晶シリコン基板を窒素雰囲気中で５００〜９００℃で熱処理を行って、基板表面のシリコンを窒化して形成される。
【０００５】
【発明が解決しようとする課題】
しかし、一般的に窒素による直接の熱窒化では、１１００〜１３００℃の高温で安定相の窒化シリコンとなる（志村史夫著、"半導体シリコン結晶工学"、丸善、平成５年９月３０日発行、第200〜206頁）ことから、上記特開平８−６４９１３号公報に示される５００〜９００℃の低い温度での窒素による熱窒化では、安定な窒化シリコンは形成されていないことが十分に考えられる。そのため、窒化シリコン膜が平坦に形成されず、窒化シリコン膜上に平坦な窒化ガリウム系化合物半導体層が形成されない恐れがあった。また一方、上記窒化シリコン膜は部分的に膜が形成されない箇所を生じ易く、絶縁膜としての機能を十分果せない問題点もあった。
【０００６】
本発明の目的は、完全に単結晶化した、結晶欠陥が極めて少ない、高品質で平坦な窒化物半導体層を比較的簡便に形成する窒化物半導体層付き基板の製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
請求項１に係る発明は、図１に示すように、単結晶シリコン基板１１上に窒化シリコン層１２を形成する工程と、この窒化シリコン層１２上に窒化物半導体層１３を形成する工程とを含む窒化物半導体層付き基板１０の製造方法において、窒化シリコン層１２を基板１１の表面全体にＲＦ−分子線エピタキシャル成長法により１００〜７００℃の温度で０．０５〜２０ｎｍの厚さで均一にアモルファス窒化シリコン薄膜を形成することを特徴とする窒化物半導体層付き基板の製造方法である。
シリコン基板１１上に窒化シリコン層１２をエピタキシャル成長して形成することにより、基板の表面全体に均一な厚さの平坦なアモルファス窒化シリコン薄膜からなる窒化シリコン層１２を形成し、基板と窒化物半導体層の間にこの窒化シリコン層を介装することにより、シリコン基板と窒化物半導体層の界面における格子定数の差が緩和され、窒化シリコン層上により高品質で平坦な窒化物半導体層を形成することができる。
【０００８】
請求項２に係る発明は、請求項１に係る発明であって、窒化シリコン層１２の形成とこの窒化シリコン層１２に続く窒化物半導体層１３の形成をＲＦプラズマ（radio frequency plasma）−分子線エピタキシャル成長（以下、ＲＦ−ＭＢＥという）法により一連に行い、かつ窒化シリコン層１２及び窒化物半導体層１３を形成するときの窒素源が主に励起状態の中性窒素原子又は分子である窒化物半導体層付き基板の製造方法である。
窒化シリコン層１２のエピタキシャル成長をＲＦ−ＭＢＥ法で行い、このときの窒素源として励起状態の中性窒素原子又は分子を用いることにより、反応性窒素となってシリコン基板上に平坦な結晶性の窒化シリコン層が形成される。この窒素源にクヌーセンセルからのＧａ，Ｉｎ，Ａｌ等の原料ソースを加えて、引き続き窒化物半導体層を形成すれば、より高品質で平坦な単結晶窒化物半導体層を窒化シリコン層上に簡便に形成することができる。
【０００９】
【発明の実施の形態】
本発明の窒化物半導体層は、ＧａＮ（窒化ガリウム系化合物半導体）、ＩｎＮ（窒化インジウム系化合物半導体）又はＡｌＮ（窒化アルミニウム系化合物半導体）からなる層である。単結晶シリコン基板とこの窒化物半導体層との間に介装される窒化シリコン層の厚さは０．０５〜２０００ｎｍである。０．０５ｎｍ未満では窒化シリコン層が均一でなく、部分的にシリコン基板上に形成されて、基板表面が露出する恐れがある。また２０００ｎｍを超えると窒化シリコン層に剥離やクラックを生じる不都合がある。窒化シリコン層を均一な厚さにし、かつ単結晶シリコン基板の結晶方位を保ったままの単結晶窒化物半導体層を作り出すためには、窒化シリコン層の厚さは０．１５〜５０ｎｍが好ましい。特に窒化シリコン層においてアモルファスの割合が高い場合にはその厚さはシリコン基板の結晶方位を窒化物半導体層に引継ぐために０．１５〜２０ｎｍ程度に薄い方が好ましい。反対に窒化シリコン層において結晶の割合が高い場合にはその厚さは２０〜２０００ｎｍ程度に厚くてもよい。
【００１０】
本発明の窒化物半導体層付き基板はシリコン基板の表面全体に均一な厚さで形成された窒化シリコン層の上にエピタキシャル成長で作られる。このエピタキシャル成長法としては、ＭＢＥ（分子線エピタキシャル成長）法、ＭＯＣＶＤ（有機金属気相成長）法、ＡＬＥ（原子層エピタキシャル成長）法等が挙げられる。特に成膜に十分な量の励起状態の中性窒素原子又は分子（反応性窒素）が得られ、かつ平坦な窒化シリコン層が得られるＲＦ−ＭＢＥ法が好ましい。これらのエピタキシャル成長法は窒化シリコン層に続く窒化物半導体層の形成にも適用できる。従って、本発明の製造方法は、窒化シリコン層と窒化物半導体層とを一連に形成することができる利点がある。
窒化シリコン層のエピタキシャル成長時の温度は１００〜１３００℃の範囲から選ばれるこの温度の高低により、アモルファス窒化シリコン層又は結晶性窒化シリコン層、或いはアモルファス窒化シリコンと結晶性窒化シリコンが混在したエピタキシャル層のいずれかが形成され、また同時に窒化シリコン層の組成が変化する。温度が低いほどアモルファス窒化シリコンの割合が増加し、温度が高いほど結晶性窒化シリコンの割合が増加する。アモルファス窒化シリコンのエピタキシャル層を形成するためには１００〜７００℃程度が、アモルファス窒化シリコンと結晶性窒化シリコンが混在したエピタキシャル層を形成するためには７００〜９５０℃程度が、更に結晶性窒化シリコンのエピタキシャル層を形成するためには９５０〜１３００℃程度がそれぞれ好ましい。窒化シリコン層の組成をＳｉXＮYで表した場合に、本発明の窒化シリコン層の組成は、次式（１）の関係を満たす範囲にある。
０．８≦Ｙ／Ｘ≦１．６ …… （１）
例えば、窒化シリコン層の形成時の温度が７００℃の場合には、Ｓｉ3Ｎ4が生成し、９５０℃の場合にはＳｉ1Ｎ1が生成する。
単結晶シリコンの格子定数と単結晶窒化物半導体の格子定数とは大きな差が存在するが、本発明の製造方法により得られる窒化物半導体層付き基板では、シリコン基板を構成するシリコンと窒化物半導体層を構成する窒素を含む窒化シリコン層を基板と窒化物半導体層との間に介装することにより、基板と窒化物半導体層との界面における格子定数の差が大幅に緩和され、シリコン基板と窒化物半導体層との間の化学的親和性は向上する。特に窒化シリコン層が基板の表面全体に均一な厚さで平坦化されて成膜されたエピタキシャル層であると、この窒化シリコン層上に高品質で平坦な窒化物半導体層が形成される。
従って、本発明の製造方法により得られる窒化物半導体層付き基板は、発光強度の高い発光素子及び光電子デバイスを作り出すことができる。
【００１１】
【実施例】
次に本発明の実施例を図面を参照して説明する。
＜実施例１＞
先ず、自然酸化膜を除去した結晶方位が（１１１）のｐ型シリコンウェーハをＲＦ−ＭＢＥ装置の基板ホルダ（図示せず）に保持した後、窒素源として主に励起状態の中性窒素原子又は分子を用い、ＲＦプラズマソースの出力を２５０Ｗ、窒素ガス流量を１．５ＣＣＭにして、６５０℃で２分間窒化処理することにより、シリコンウェーハ上に窒化シリコン層をエピタキシャル成長させた。
この窒化シリコン層を形成したシリコンウェーハを同一の基板ホルダに保持したまま、７００℃で励起状態の中性窒素原子又は分子とクヌーセンセルからのＧａを３時間照射して、窒化シリコン層上に窒化ガリウム層を形成した。
【００１２】
＜参考例１＞
窒化シリコン層のエピタキシャル成長時の温度を９５０℃にした以外は、実施例１と同様にしてシリコンウェーハ上に窒化シリコン層を介して窒化ガリウム層を形成した。
＜参考例２＞
窒化シリコン層のエピタキシャル成長時の温度を８００℃、時間を３分にした以外は、実施例１と同様にしてシリコンウェーハ上に窒化シリコン層を介して窒化ガリウム層を形成した。
＜比較例１＞
窒化シリコン層を設けない以外は実施例１と同様にしてシリコンウェーハ上に直接窒化ガリウム層を形成した。
【００１３】
＜比較評価＞
(a) ＲＨＥＥＤ像の観察
ＲＦ−ＭＢＥ装置の真空容器内に反射型高速電子回折装置（ＲＨＥＥＤ）を挿入して、実施例１、参考例１，２及び比較例１のエピタキシャル成長過程をその場（in situ）観察した。
図２は実施例１、参考例１，２及び比較例１に共通する窒化シリコン層又は窒化ガリウム層をエピタキシャル成長させる前のシリコンウェーハのＲＨＥＥＤ像（反射型高速電子線回折像）である。図２にはシリコンの再配列構造に起因する７×７構造が現れ、このことからシリコンウェーハの表面酸化層は完全に除去され、この表面が清浄で平坦であることがわかる。
【００１４】
(1) 実施例１（アモルファス窒化シリコン層）のＲＨＥＥＤ像の観察
図３は窒化シリコン層を形成した直後の窒化ガリウム層を形成する前のＲＨＥＥＤ像である。図３よりアモルファス窒化シリコンからなる窒化シリコン層が形成されていることがわかる。図４はアモルファス窒化シリコン層上に窒化ガリウム層を形成し始めて１５秒後のＲＨＥＥＤ像、図５は３０秒後のＲＨＥＥＤ像、図６は６０秒後のＲＨＥＥＤ像、図７は３時間後のＲＨＥＥＤ像である。図４から窒化ガリウムの結晶化を示すスポットが現れ始め、図５から単結晶状のスポットが現れ始め、図６から単結晶窒化ガリウムのスポットが明瞭になってきたことがそれぞれわかる。窒化ガリウム層を３時間かけて成長させた後の図７からはスポットがほぼ消失し、ストリーク状になっていることが見られ、このことから非常に平坦で結晶性の良い窒化ガリウムが次式（２）の方位関係を保って成長していることがわかる。
【００１５】
【数１】
【００１６】
(2) 参考例１（アモルファスと結晶が混在した窒化シリコン層）のＲＨＥＥＤ像の観察
図８は窒化シリコン層を形成した直後の窒化ガリウム層を形成する前のＲＨＥＥＤ像である。図８より下地のシリコン基板との格子の整合性を示す単結晶状の窒化シリコン層が形成されており、その格子定数はシリコンより約２９％小さく、窒化ガリウムの格子定数との差は約９％になり、その差が小さくなっていることがわかる。しかし、それらのストリークは十分明瞭であるとは言えず、背景がぼけていることからアモルファス状窒化シリコンが存在していると考えられる。
図９は窒化ガリウム層の成長開始から５分後の窒化ガリウム層のＲＨＥＥＤ像であって、図９からは窒化ガリウムのスポットが明瞭になっていて、ウルツ鉱型単結晶窒化ガリウム層が窒化シリコン層上に連続的にエピタキシャル成長していることがわかる。図１０は窒化ガリウム層を３時間かけて成長させた後のＲＨＥＥＤ像であって、図１０からは図７と同様にスポットがほぼ消失し、ストリーク状になっているのが見られ、このことから非常に平坦で結晶性の良い窒化ガリウムが形成できたことがわかる。
【００１７】
(3) 参考例２（結晶性窒化シリコン層）のＲＨＥＥＤ像の観察
図１１は窒化シリコン層を形成した直後の窒化ガリウム層を形成する前のＲＨＥＥＤ像である。図１１より単結晶状の窒化シリコンからなる窒化シリコン層が形成されており、その格子定数はシリコンより約２６％小さく、窒化ガリウムの格子定数との差は約６％になり、その差が小さくなっていることがわかる。図１２は結晶性窒化シリコン層上に窒化ガリウム層を形成し始めて６０秒後のＲＨＥＥＤ像、図１３は３時間後のＲＨＥＥＤ像である。図１２から単結晶窒化ガリウムのスポットが明瞭になり、図１３からは図７及び図１０と同様にスポットがほぼ消失し、ストリーク状になっていることが見られ、このことから非常に平坦で結晶性の良い窒化ガリウムが形成できたことがわかる。
【００１８】
(4) 比較例１（窒化シリコン層なし）のＲＨＥＥＤ像の観察
図１４はシリコンウェーハ上に窒化ガリウム層を成長させてから３０秒後の窒化ガリウム層のＲＨＥＥＤ像、図１５は３時間後のＲＨＥＥＤ像である。図１４からアモルファス状の窒化ガリウムが成長し始め、図１５からはリングパターンが現れ、多結晶状の窒化ガリウムが形成されていることがわかる。
【００１９】
(b) フォトルミネッセンス強度
窒化ガリウム層を３時間かけて成長させた後の参考例１及び比較例１のフォトルミネッセンス強度を測定した。その結果を図１６に示す。図１６から明らかなように比較例１では３．４３ｅＶ（３６１ｎｍ）でのピーク強度が低いの対して、参考例１では３．４７ｅＶ（３５８．８ｎｍ）で非常に高いピーク強度が現れ、しかもそれ以外のピークが観察されていないことから紫外領域に強い発光をもつ高品質の窒化ガリウム層が成長していることがわかる。
【００２０】
(c) 窒化シリコン層及び窒化ガリウム層の平坦度及び厚さ
実施例１、参考例１，２の窒化シリコン層及び窒化ガリウム層の平坦度と厚さ、並びに比較例１の窒化ガリウム層の平坦度と厚さを透過電子顕微鏡を用いて各層の断面を観察することにより測定した。平坦度に関して、比較例１の窒化ガリウム層が平坦でないのに対して、実施例１、参考例１，２の窒化シリコン層及び窒化ガリウム層はともに平坦であった。厚さに関して、その結果を表１に示す。
【００２１】
【表１】
【００２２】
(d) オージェ分析結果
参考例１の窒化シリコン層上に窒化ガリウム層を形成する前の窒化シリコン層についてそれぞれ表面分析法であるオージェ分析により窒化シリコン層の表面から深さ方向の組成を調べた。その結果を図１７に示す。図１７において、横軸はオージェ電子エネルギを、縦軸はオージェ電子により検出される各元素の信号強度をそれぞれ示す。図１７において１６１２ｅＶのピークはシリコンウェーハに由来するＳｉ−ＫＬＬのオージェ遷移を、１６０７ｅＶのピークは窒化シリコンに由来するＳｉ−ＫＬＬのオージェ遷移を、また３７７ｅＶのピークは窒化シリコンに由来するＮ−ＫＬＬオージェ遷移をそれぞれ示している。これらの結果から窒化シリコン層のＳｉと窒素の組成比（原子数）、即ち前述した式（１）のＸ／Ｙは、０．９７であった。
同様に実施例１の窒化シリコン層のＳｉと窒素の組成比（原子数）をオージェ分析したところ、Ｘ／Ｙ＝１．４であった。
【００２３】
【発明の効果】
以上述べたように、本発明によれば、シリコン基板上にアモルファス窒化シリコンからなるエピタキシャル層を基板表面全体に均一な厚さで形成し、その上に窒化物半導体を成長するようにしたので、窒化物半導体層中に格子欠陥が少なく、シリコン基板上に単結晶で高品質で平坦な窒化物半導体層が得られる。
特に本発明のエピタキシャル成長した窒化シリコン層に引続いて窒化物半導体層を同一のエピタキシャル装置で積層できる利点がある。
【図面の簡単な説明】
【図１】 本発明の窒化物半導体層付き基板の断面構成図。
【図２】 シリコン基板上に窒化ガリウム層を成長させる前のシリコン基板表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図３】 実施例１のアモルファス窒化シリコン層を形成した直後の窒化ガリウム層形成前の窒化シリコン層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図４】 実施例１の窒化ガリウム層の成長開始して１５秒後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図５】 実施例１の窒化ガリウム層の成長開始して３０秒後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図６】 実施例１の窒化ガリウム層の成長開始して６０秒後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図７】 実施例１の窒化ガリウム層の成長開始して３時間後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図８】 参考例１のアモルファスと結晶が混在した窒化シリコン層を形成した直後の窒化ガリウム層形成前の窒化シリコン層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図９】 参考例１の窒化ガリウム層の成長開始して５分後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１０】 参考例１の窒化ガリウム層の成長開始して３時間後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１１】 参考例２の結晶性窒化シリコン層を形成した直後の窒化ガリウム層形成前の窒化シリコン層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１２】 参考例２の窒化ガリウム層の成長開始して６０秒後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１３】 参考例２の窒化ガリウム層の成長開始して３時間後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１４】 比較例１の窒化ガリウム層の成長開始して６０秒後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１５】 比較例１の窒化ガリウム層の成長開始して３時間後の窒化ガリウム層表面の結晶構造を示す反射型高速電子線回折像の写真図。
【図１６】 参考例１及び比較例１の窒化物半導体層付き基板から作製した発光素子のフォトルミネッセンス強度を示す図。
【図１７】 参考例１の窒化シリコン層のオージェ分析結果を示す図。
【図１８】 従来の窒化物半導体層付き基板の断面構成図。
【符号の説明】
１０ 窒化物半導体層付き基板
１１ 単結晶シリコン基板
１２ 窒化シリコン層
１３ 窒化物半導体層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a process for the production of optoelectronic devices and nitride is used in a semiconductor light-emitting device semiconductor layer with board. And more particularly to a method for manufacturing a nitride semiconductor layer-board forming a nitride semiconductor layer on a single crystal silicon substrate.
[0002]
[Prior art]
Conventionally, as a method for forming a nitride semiconductor layer of GaN, InN, AlN or the like on a single crystal silicon substrate, a first method for directly forming a nitride semiconductor layer on a single crystal silicon substrate is known. This method includes a method of forming a nitride semiconductor buffer layer at a low temperature and forming a nitride semiconductor layer on the buffer layer at a high temperature.
As another second method, a method of forming an intermediate layer made of silicon carbide (SiC) or gallium arsenide (GaAs) on a single crystal silicon substrate and forming a nitride semiconductor layer thereon is known. Yes.
[0003]
However, in the first method, when the GaN layer 2 is directly formed on the single crystal silicon substrate 1 as shown in FIG. 18, for example, amorphous silicon nitride is randomly formed on a part of the surface of the silicon substrate 1 when the GaN layer 2 is formed. Layer 3 is formed. This amorphous silicon nitride layer 3 deteriorates the flatness of the interface between the silicon substrate 1 and the GaN layer 2, causes crystal defects in the GaN layer 2, and further causes polycrystallization of the GaN layer. is there. When photoluminescence showing the emission characteristics of the GaN layer 2 formed in this way is measured, a peak of photoluminescence appears at 3.4 eV, but the intensity is low and the half-value width of the peak is wide. Inferior properties.
In the second method, a source of an element other than the elements constituting the nitride semiconductor layer is required, and it is difficult to continuously grow the nitride semiconductor layer. Further, there arises a problem that elements from the source material are mixed as impurities into the nitride semiconductor layer. In order to prevent this, it is necessary to thoroughly clean the inside of the manufacturing apparatus after forming an intermediate layer made of SiC, GaAs, or the like.
[0004]
In order to solve this problem, a method for manufacturing a nitride semiconductor light-emitting device is disclosed in which a gallium nitride-based compound semiconductor layer is formed on a single crystal silicon substrate via an insulating film such as a silicon nitride film (Japanese Patent Laid-open No. Hei. 8-64913). This silicon nitride film is formed by nitriding silicon on the substrate surface by subjecting the single crystal silicon substrate from which the natural oxide film on the substrate surface has been removed to a heat treatment at 500 to 900 ° C. in a nitrogen atmosphere.
[0005]
[Problems to be solved by the invention]
However, in general, direct thermal nitridation with nitrogen results in silicon nitride in a stable phase at a high temperature of 1100 to 1300 ° C. (Shimura Fumio, “Semiconductor Silicon Crystal Engineering”, Maruzen, published on September 30, 1993, From page 200 to 206), it is considered that stable silicon nitride is not formed by thermal nitridation with nitrogen at a low temperature of 500 to 900 ° C. disclosed in the above-mentioned JP-A-8-64913. . For this reason, the silicon nitride film is not formed flat, and a flat gallium nitride compound semiconductor layer may not be formed on the silicon nitride film. On the other hand, the silicon nitride film has a problem that a portion where the film is not formed is easily formed, and the function as an insulating film cannot be sufficiently achieved.
[0006]
The purpose of the present invention, fully a single crystal, the crystal defects are extremely small, to provide a method for manufacturing a nitride semiconductor layer substrate with a relatively easily form a flat nitride semiconductor layer with high quality is there.
[0007]
[Means for Solving the Problems]
As shown in FIG. 1, the invention according to claim 1 includes a step of forming a silicon nitride layer 12 on a single crystal silicon substrate 11 and a step of forming a nitride semiconductor layer 13 on the silicon nitride layer 12. In the manufacturing method of the substrate 10 with a nitride semiconductor layer, the silicon nitride layer 12 is uniformly formed on the entire surface of the substrate 11 at a temperature of 100 to 700 ° C. and a thickness of 0.05 to 20 nm by an RF-molecular beam epitaxial growth method. An amorphous silicon nitride thin film is formed . A method for producing a substrate with a nitride semiconductor layer .
By forming a silicon substrate 11 a silicon nitride layer 12 over by epitaxial growth, a silicon nitride layer 12 consisting of a flat amorphous silicon nitride film having a uniform thickness on the entire surface of the substrate, the substrate and the nitride By interposing this silicon nitride layer between the semiconductor layers, the difference in lattice constant at the interface between the silicon substrate and the nitride semiconductor layer is alleviated, and a higher quality and flat nitride semiconductor layer is formed on the silicon nitride layer. can do.
[0008]
The invention according to claim 2 is the invention according to claim 1 , wherein the formation of the silicon nitride layer 12 and the formation of the nitride semiconductor layer 13 subsequent to the silicon nitride layer 12 are performed by RF plasma-molecular beam. Nitride semiconductors in which the nitrogen source is mainly neutral nitrogen atoms or molecules in an excited state when the silicon nitride layer 12 and the nitride semiconductor layer 13 are formed in series by an epitaxial growth (hereinafter referred to as RF-MBE) method. It is a manufacturing method of a board | substrate with a layer.
Perform epitaxial growth of silicon nitride layer 12 by RF-MBE method, by using a neutral nitrogen atom or molecule in the excited state as a nitrogen source at this time, flat crystalline silicon substrate becomes reactive nitrogen The silicon nitride layer is formed. If a source material such as Ga, In, Al or the like from Knudsen cell is added to this nitrogen source and a nitride semiconductor layer is subsequently formed, a higher quality flat single crystal nitride semiconductor layer can be easily formed on the silicon nitride layer. Can be formed.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The nitride semiconductor layer of the present invention is a layer made of GaN (gallium nitride compound semiconductor), InN (indium nitride compound semiconductor) or AlN (aluminum nitride compound semiconductor). The thickness of the silicon nitride layer interposed between the single crystal silicon substrate and the nitride semiconductor layer is 0.05 to 2000 nm. If the thickness is less than 0.05 nm, the silicon nitride layer is not uniform and may be partially formed on the silicon substrate, exposing the substrate surface. On the other hand, if the thickness exceeds 2000 nm, there is a disadvantage that peeling or cracking occurs in the silicon nitride layer. In order to produce a single crystal nitride semiconductor layer with a uniform thickness of the silicon nitride layer and maintaining the crystal orientation of the single crystal silicon substrate, the thickness of the silicon nitride layer is preferably 0.15 to 50 nm. In particular, when the amorphous ratio in the silicon nitride layer is high, the thickness is preferably as thin as about 0.15 to 20 nm in order to take over the crystal orientation of the silicon substrate to the nitride semiconductor layer. On the contrary, when the ratio of crystals in the silicon nitride layer is high, the thickness may be as large as about 20 to 2000 nm.
[0010]
Nitride semiconductor layer-substrate of the present invention is made of epitaxially grown on the silicon nitride layer formed with a uniform thickness on the entire surface of the silicon substrate. Examples of this epitaxial growth method include MBE (molecular beam epitaxial growth) method, MOCVD (metal organic chemical vapor deposition) method, ALE (atomic layer epitaxial growth) method and the like. In particular, an RF-MBE method is preferable, in which neutral nitrogen atoms or molecules (reactive nitrogen) in an excited state sufficient for film formation can be obtained, and a flat silicon nitride layer can be obtained. These epitaxial growth methods can also be applied to the formation of a nitride semiconductor layer following the silicon nitride layer. Therefore, the manufacturing method of the present invention has an advantage that a silicon nitride layer and a nitride semiconductor layer can be formed in series.
Temperature during the epitaxial growth of silicon nitride layer by high and low of the temperature selected from the range of 100-1300 ° C., the amorphous silicon nitride layer or a crystalline silicon nitride layer, or amorphous et silicon and the crystalline silicon nitride nitride are mixed epitaxially Any of the layers is formed and at the same time the composition of the silicon nitride layer changes. The lower the temperature, the higher the proportion of amorphous silicon nitride, and the higher the temperature, the higher the proportion of crystalline silicon nitride. In order to form an epitaxial layer of amorphous silicon nitride, about 100 to 700 ° C., to form an epitaxial layer in which amorphous silicon nitride and crystalline silicon nitride are mixed, about 700 to 950 ° C. is further used. Is preferably about 950 to 1300 ° C. When the composition of the silicon nitride layer is expressed by Si x N y , the composition of the silicon nitride layer of the present invention is in a range satisfying the relationship of the following formula (1).
0.8 ≦ Y / X ≦ 1.6 (1)
For example, when the temperature at the time of forming the silicon nitride layer is 700 ° C., Si 3 N 4 is generated, and when it is 950 ° C., Si 1 N 1 is generated.
Although there is a large difference between the lattice constant of single crystal silicon and the lattice constant of single crystal nitride semiconductor, in the substrate with a nitride semiconductor layer obtained by the manufacturing method of the present invention, silicon constituting the silicon substrate and the nitride semiconductor By interposing the silicon nitride layer containing nitrogen constituting the layer between the substrate and the nitride semiconductor layer, the difference in lattice constant at the interface between the substrate and the nitride semiconductor layer is greatly reduced, The chemical affinity between the nitride semiconductor layer is improved. In particular, when the silicon nitride layer is an epitaxial layer formed by planarizing the entire surface of the substrate with a uniform thickness, a high quality and flat nitride semiconductor layer is formed on the silicon nitride layer.
Therefore, the substrate with a nitride semiconductor layer obtained by the manufacturing method of the present invention can produce a light emitting element and an optoelectronic device with high emission intensity.
[0011]
【Example】
Next, embodiments of the present invention will be described with reference to the drawings.
<Example 1>
First, a p-type silicon wafer having a crystal orientation (111) from which a natural oxide film has been removed is held on a substrate holder (not shown) of an RF-MBE apparatus, and then neutral nitrogen atoms mainly excited as nitrogen sources or using molecular, 250 W output of the RF plasma source, and a nitrogen gas flow rate 1.5CCM, by nitriding 2-minute treatment at 650 ° C., the silicon nitride layer was epitaxially grown on a silicon wafer.
While the silicon wafer on which the silicon nitride layer is formed is held in the same substrate holder, neutral nitrogen atoms or molecules in an excited state and Ga from Knudsen cell are irradiated for 3 hours at 700 ° C. to nitride the silicon nitride layer. A gallium layer was formed.
[0012]
< Reference Example 1 >
Except that the temperature of the epitaxial growing the silicon nitride layer was 950 ° C. formed a gallium nitride layer through the silicon nitride layer on a silicon wafer in the same manner as in Example 1.
< Reference Example 2 >
The temperature of the epitaxial growing the silicon nitride layer 800 ° C., except that the time 3 minutes to form a gallium nitride layer through the silicon nitride layer on a silicon wafer in the same manner as in Example 1.
<Comparative Example 1>
A gallium nitride layer was directly formed on the silicon wafer in the same manner as in Example 1 except that no silicon nitride layer was provided.
[0013]
<Comparison evaluation>
(a) Observation of RHEED image A reflection type high-energy electron diffractometer (RHEED) is inserted into the vacuum vessel of the RF-MBE apparatus, and the epitaxial growth processes of Example 1 , Reference Examples 1, 2 and Comparative Example 1 are performed in situ ( observed in situ).
FIG. 2 is an RHEED image (reflection high-energy electron diffraction image) of a silicon wafer before epitaxial growth of a silicon nitride layer or a gallium nitride layer common to Example 1 , Reference Examples 1 and 2, and Comparative Example 1. FIG. 2 shows a 7 × 7 structure resulting from the rearrangement structure of silicon, which indicates that the surface oxide layer of the silicon wafer is completely removed, and that the surface is clean and flat.
[0014]
(1) Observation of RHEED Image of Example 1 (Amorphous Silicon Nitride Layer) FIG. 3 is an RHEED image before forming a gallium nitride layer immediately after forming a silicon nitride layer. FIG. 3 shows that a silicon nitride layer made of amorphous silicon nitride is formed. 4 shows an RHEED image 15 seconds after the start of forming a gallium nitride layer on the amorphous silicon nitride layer, FIG. 5 shows an RHEED image after 30 seconds, FIG. 6 shows an RHEED image after 60 seconds, and FIG. It is a RHEED image. FIG. 4 shows that spots indicating crystallization of gallium nitride begin to appear, FIG. 5 shows that single crystal spots begin to appear, and FIG. 6 shows that single crystal gallium nitride spots have become clear. From FIG. 7 after growing the gallium nitride layer over 3 hours, it can be seen that the spots almost disappeared and become streak-like. It can be seen that the growth is maintained while maintaining the orientation relationship of (2).
[0015]
[Expression 1]
[0016]
(2) Reference Example 1 Observation of RHEED Image (Silicon Nitride Layer Mixed with Amorphous and Crystal) FIG. 8 is an RHEED image before forming a gallium nitride layer immediately after forming a silicon nitride layer. As shown in FIG. 8, a single-crystal silicon nitride layer showing lattice matching with the underlying silicon substrate is formed, the lattice constant of which is about 29% smaller than that of silicon, and the difference from the lattice constant of gallium nitride is about 9 It can be seen that the difference is small. However, these streaks are not sufficiently clear, and the background is blurred, so it is considered that amorphous silicon nitride exists.
FIG. 9 is a RHEED image of the gallium nitride layer 5 minutes after the start of the growth of the gallium nitride layer. FIG. 9 shows the gallium nitride spot clearly, and the wurtzite single crystal gallium nitride layer is formed of silicon nitride. it can be seen that you are continuously epitaxially grown on the layer. FIG. 10 is a RHEED image after the gallium nitride layer is grown for 3 hours. From FIG. 10, it can be seen that the spots almost disappear and become streak like FIG. It can be seen that gallium nitride having a very flat and good crystallinity was formed.
[0017]
(3) Reference Example 2 Observation of RHEED Image of (Crystalline Silicon Nitride Layer) FIG. 11 is an RHEED image before forming a gallium nitride layer immediately after forming a silicon nitride layer. As shown in FIG. 11, a silicon nitride layer made of single-crystal silicon nitride is formed, the lattice constant of which is about 26% smaller than that of silicon, and the difference from the lattice constant of gallium nitride is about 6%, which is small. You can see that FIG. 12 shows an RHEED image 60 seconds after starting to form a gallium nitride layer on the crystalline silicon nitride layer, and FIG. 13 shows an RHEED image after 3 hours. From FIG. 12, the spot of the single crystal gallium nitride becomes clear, and from FIG. 13, it can be seen that the spot almost disappears and has a streak shape like FIG. 7 and FIG. It can be seen that gallium nitride with good crystallinity was formed.
[0018]
(4) Observation of RHEED image of Comparative Example 1 (without silicon nitride layer) FIG. 14 shows an RHEED image of the gallium nitride layer 30 seconds after the gallium nitride layer was grown on the silicon wafer, and FIG. It is a RHEED image. FIG. 14 shows that amorphous gallium nitride starts to grow, and FIG. 15 shows that a ring pattern appears and polycrystalline gallium nitride is formed.
[0019]
(b) Photoluminescence intensity The photoluminescence intensity of Reference Example 1 and Comparative Example 1 after the gallium nitride layer was grown over 3 hours was measured. The result is shown in FIG. As is clear from FIG. 16, the peak intensity at 3.43 eV (361 nm) is low in Comparative Example 1, whereas the peak intensity at 3.47 eV (358.8 nm) appears in Reference Example 1 , and Since no other peaks are observed, it can be seen that a high-quality gallium nitride layer having strong emission in the ultraviolet region has grown.
[0020]
(c) Flatness and thickness of silicon nitride layer and gallium nitride layer Flatness and thickness of silicon nitride layer and gallium nitride layer of Example 1 , Reference Examples 1 and 2 and flatness of gallium nitride layer of Comparative Example 1 The degree and thickness were measured by observing the cross section of each layer using a transmission electron microscope. Regarding the flatness, the gallium nitride layer of Comparative Example 1 was not flat, whereas the silicon nitride layers and gallium nitride layers of Example 1 and Reference Examples 1 and 2 were both flat. The results for thickness are shown in Table 1.
[0021]
[Table 1]
[0022]
(d) Auger analysis results
The composition in the depth direction from the surface of the silicon nitride layer was examined by Auger analysis which is a surface analysis method for the silicon nitride layer before forming the gallium nitride layer on the silicon nitride layer of Reference Example 1 . The result is shown in FIG. In FIG. 17, the horizontal axis represents Auger electron energy, and the vertical axis represents the signal intensity of each element detected by Auger electrons. In FIG. 17, the peak at 1612 eV represents the Auger transition of Si-KLL derived from a silicon wafer, the peak at 1607 eV represents the Auger transition of Si-KLL derived from silicon nitride, and the peak at 377 eV represents N-KLL derived from silicon nitride. Each Auger transition is shown. From these results, the composition ratio (number of atoms) of Si and nitrogen of the silicon nitride layer, that is, X / Y in the above-described formula (1) was 0.97.
Similarly, when the composition ratio (number of atoms) of Si and nitrogen in the silicon nitride layer of Example 1 was subjected to Auger analysis, X / Y = 1.4.
[0023]
【The invention's effect】
As described above, according to the present invention, the A Amorphous nitride silicon down or Rana Rue epitaxial layer formed with uniform thickness on the entire substrate surface on a silicon substrate, growing a nitride semiconductor thereon As a result, there are few lattice defects in the nitride semiconductor layer, and a single crystal, high quality and flat nitride semiconductor layer can be obtained on the silicon substrate.
Can advantageously be laminated in the same epitaxial device nitride semiconductor layer subsequently particularly silicon nitride layer epitaxially grown to the present invention.
[Brief description of the drawings]
FIG. 1 is a cross-sectional configuration diagram of a substrate with a nitride semiconductor layer of the present invention.
FIG. 2 is a photograph of a reflection high-speed electron diffraction image showing a crystal structure of a silicon substrate surface before a gallium nitride layer is grown on the silicon substrate.
3 is a photograph of a reflection type high-energy electron diffraction image showing a crystal structure of the surface of the silicon nitride layer immediately after forming the amorphous silicon nitride layer of Example 1 and before forming the gallium nitride layer. FIG.
4 is a photograph of a reflection type high-energy electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 15 seconds after the start of growth of the gallium nitride layer of Example 1. FIG.
5 is a photograph of a reflection type high-speed electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 30 seconds after the start of growth of the gallium nitride layer of Example 1. FIG.
6 is a photograph of a reflection high-energy electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 60 seconds after the start of growth of the gallium nitride layer of Example 1. FIG.
7 is a photograph of a reflection high-speed electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 3 hours after the start of growth of the gallium nitride layer of Example 1. FIG.
8 is a photograph of a reflection high-speed electron diffraction image showing the crystal structure of the surface of the silicon nitride layer immediately before forming the gallium nitride layer immediately after forming the silicon nitride layer in which amorphous and crystals are mixed in Reference Example 1. FIG.
9 is a photograph of a reflection type high-energy electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 5 minutes after the start of growth of the gallium nitride layer of Reference Example 1. FIG.
10 is a photograph of a reflection type high-energy electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 3 hours after the start of growth of the gallium nitride layer of Reference Example 1. FIG.
11 is a photograph of a reflection high-speed electron diffraction image showing the crystal structure of the surface of the silicon nitride layer immediately after the crystalline silicon nitride layer of Reference Example 2 is formed and before the gallium nitride layer is formed.
12 is a photograph of a reflection type high-energy electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 60 seconds after the start of growth of the gallium nitride layer of Reference Example 2. FIG.
13 is a photograph of a reflection type high-speed electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 3 hours after the start of growth of the gallium nitride layer of Reference Example 2. FIG.
14 is a photograph of a reflection type high-speed electron diffraction image showing the crystal structure of the surface of the gallium nitride layer 60 seconds after the start of growth of the gallium nitride layer of Comparative Example 1. FIG.
15 is a photograph of a reflection high-speed electron beam diffraction image showing the crystal structure of the surface of the gallium nitride layer 3 hours after the start of growth of the gallium nitride layer of Comparative Example 1. FIG.
16 is a graph showing photoluminescence intensity of a light-emitting element manufactured using a substrate with a nitride semiconductor layer in Reference Example 1 and Comparative Example 1. FIG.
17 is a view showing an Auger analysis result of the silicon nitride layer of Reference Example 1. FIG.
FIG. 18 is a cross-sectional configuration diagram of a conventional substrate with a nitride semiconductor layer.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Substrate with nitride semiconductor layer 11 Single crystal silicon substrate 12 Silicon nitride layer 13 Nitride semiconductor layer
Claims (2)
前記窒化シリコン層(12)を前記基板(11)の表面全体にＲＦ−分子線エピタキシャル成長法により１００〜７００℃の温度で０．０５〜２０ｎｍの厚さで均一にアモルファス窒化シリコン薄膜を形成することを特徴とする窒化物半導体層付き基板の製造方法。 A substrate with a nitride semiconductor layer, comprising: a step of forming a silicon nitride layer (12) on a single crystal silicon substrate (11); and a step of forming a nitride semiconductor layer (13) on the silicon nitride layer (12). In the production method of (10),
Uniformly forming a silicon amorphous nitride film by the silicon nitride layer (12) of said substrate (11) a thickness of 0.05 to 20 nm on the entire surface by RF- molecular beam epitaxy at a temperature of 100 to 700 ° C. of method for manufacturing a nitride semiconductor layer-substrate, characterized in that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14032198A JP4301592B2 (en) | 1998-01-16 | 1998-05-22 | Manufacturing method of substrate with nitride semiconductor layer |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1831698 | 1998-01-16 | ||
| JP10-18316 | 1998-01-16 | ||
| JP14032198A JP4301592B2 (en) | 1998-01-16 | 1998-05-22 | Manufacturing method of substrate with nitride semiconductor layer |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009037272A Division JP4981079B2 (en) | 1998-01-16 | 2009-02-20 | Manufacturing method of substrate with nitride semiconductor layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11265853A JPH11265853A (en) | 1999-09-28 |
| JP4301592B2 true JP4301592B2 (en) | 2009-07-22 |
Family
ID=26354982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14032198A Expired - Lifetime JP4301592B2 (en) | 1998-01-16 | 1998-05-22 | Manufacturing method of substrate with nitride semiconductor layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4301592B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692287B2 (en) | 2011-05-16 | 2014-04-08 | Kabushiki Kaisha Toshiba | Nitride semiconductor device, nitride semiconductor wafer, and method for manufacturing nitride semiconductor layer |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4784012B2 (en) * | 2001-07-27 | 2011-09-28 | 日亜化学工業株式会社 | Nitride semiconductor substrate and manufacturing method thereof |
| TW574762B (en) * | 2002-10-16 | 2004-02-01 | Univ Nat Cheng Kung | Method for growing monocrystal GaN on silicon substrate |
| KR100507610B1 (en) * | 2002-11-15 | 2005-08-10 | 광주과학기술원 | Nitride semiconductor nanophase opto-electronic cell and the preparation method thereof |
| US7339205B2 (en) * | 2004-06-28 | 2008-03-04 | Nitronex Corporation | Gallium nitride materials and methods associated with the same |
| US7687827B2 (en) | 2004-07-07 | 2010-03-30 | Nitronex Corporation | III-nitride materials including low dislocation densities and methods associated with the same |
| TWI300632B (en) | 2006-05-25 | 2008-09-01 | Ind Tech Res Inst | Group-iii nitride vertical-rods substrate |
| JP5513763B2 (en) * | 2009-03-27 | 2014-06-04 | 学校法人同志社 | Method and apparatus for manufacturing silicon nitride substrate having Si3N4 heteroepitaxial buffer layer on silicon substrate |
| JP5746544B2 (en) * | 2011-04-05 | 2015-07-08 | 日本放送協会 | Nitride semiconductor substrate and method for manufacturing nitride semiconductor substrate |
| WO2014073585A1 (en) * | 2012-11-08 | 2014-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Metal oxide film and method for forming metal oxide film |
| JP6185398B2 (en) | 2014-01-31 | 2017-08-23 | 東京エレクトロン株式会社 | Gallium nitride crystal growth method and heat treatment apparatus |
| FR3031833B1 (en) * | 2015-01-21 | 2018-10-05 | Centre National De La Recherche Scientifique (Cnrs) | PROCESS FOR MANUFACTURING A PASSIVE ELEMENTS III-BASED NITRIDE SEMICONDUCTOR STRUCTURE AND SUCH A STRUCTURE |
| FR3031834B1 (en) * | 2015-01-21 | 2018-10-05 | Centre National De La Recherche Scientifique (Cnrs) | FABRICATION OF A SEMICONDUCTOR SUPPORT BASED ON ELEMENT III NITRIDE |
| JP6909191B2 (en) * | 2018-09-27 | 2021-07-28 | 信越化学工業株式会社 | Laminates, semiconductor devices and methods for manufacturing laminates |
| US20230154748A1 (en) * | 2019-10-24 | 2023-05-18 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing semiconductor substrate and semiconductor substrate |
-
1998
- 1998-05-22 JP JP14032198A patent/JP4301592B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692287B2 (en) | 2011-05-16 | 2014-04-08 | Kabushiki Kaisha Toshiba | Nitride semiconductor device, nitride semiconductor wafer, and method for manufacturing nitride semiconductor layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11265853A (en) | 1999-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8142566B2 (en) | Method for producing Ga-containing nitride semiconductor single crystal of BxAlyGazIn1-x-y-zNsPtAs1-s-t (0<=x<=1, 0<=y<1, 0<z<=1, 0<s<=1 and 0<=t<1) on a substrate | |
| US7811902B2 (en) | Method for manufacturing nitride based single crystal substrate and method for manufacturing nitride based light emitting diode using the same | |
| US6440823B1 (en) | Low defect density (Ga, Al, In)N and HVPE process for making same | |
| JP4301592B2 (en) | Manufacturing method of substrate with nitride semiconductor layer | |
| US20070138505A1 (en) | Low defect group III nitride films useful for electronic and optoelectronic devices and methods for making the same | |
| US20050106849A1 (en) | Method for growing group-III nitride semiconductor heterostructure on silicon substrate | |
| JP2005320237A (en) | NON-POLAR SINGLE CRYSTALLINE a-PLANE NITRIDE SEMICONDUCTOR WAFER AND ITS MANUFACTURING METHOD | |
| TW200912054A (en) | Method for preparing substrate for growing gallium nitride and method for preparing gallium nitride substrate | |
| JP4981079B2 (en) | Manufacturing method of substrate with nitride semiconductor layer | |
| JP2004111848A (en) | Sapphire substrate, epitaxial substrate using it, and its manufacturing method | |
| US6906351B2 (en) | Group III-nitride growth on Si substrate using oxynitride interlayer | |
| US6946370B2 (en) | Semiconductor crystal producing method | |
| JP3353527B2 (en) | Manufacturing method of gallium nitride based semiconductor | |
| JP2927768B1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2004269313A (en) | Method for manufacturing gallium nitride crystal substrate | |
| JP3508356B2 (en) | Semiconductor crystal growth method and semiconductor thin film | |
| US6031252A (en) | Epitaxial wafer and method of preparing the same | |
| JP3504851B2 (en) | Method for manufacturing compound semiconductor film | |
| JP2005001928A (en) | Self-supporting substrate and method for producing the same | |
| JP3975700B2 (en) | Method for producing compound semiconductor | |
| JP2004051446A (en) | Oxide single crystal thin film formation method and semiconductor thin film forming method | |
| KR101041659B1 (en) | A Method Of Manfacturing GaN Epitaxial Layer Using ZnO Buffer Layer | |
| JP2023532799A (en) | Semiconductor substrate with nitrided interfacial layer | |
| JP3956343B2 (en) | Manufacturing method of semiconductor device | |
| JP3870259B2 (en) | Nitride semiconductor laminate and growth method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050510 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20050510 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20050510 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061107 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061114 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061227 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090105 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090220 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20090220 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20090323 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090421 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090421 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120501 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120501 Year of fee payment: 3 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120501 Year of fee payment: 3 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120501 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130501 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140501 Year of fee payment: 5 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |