JP2003078578A - Phase shift keying signal demodulator for data carrier device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulator capable of removing the deterioration factor of the stability of communication in a data carrier device, and accurately demodulating a signal from a BPSK (bi-phase-shift keying) modulation signal. SOLUTION: The phase shift keying signal demodulator for a data carrier device is constituted as the demodulator of a phase shift keying signal constituting the wireless receiver of the data carrier device, and provided with a means 1 for generating a first reference I signal, a means 2 for generating a second reference signal Q signal having the same frequency as that of the I signal and a 90 deg. phase difference, a means 3 for generating the demodulation reference signal of the logical product of the I signal and the Q signal, a means 5 for generating the comparison signal of the logical product of the modulation reference signal and a BPSK signal, and a detection means 8 for binarizing the comparison signal, and for generating a demodulation signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shift keying signal demodulator incorporated in a data carrier device for transmitting and receiving data by wireless communication between a reader / writer and a data carrier.

[0002]

2. Description of the Related Art Entry / exit management to a specific room, logistics management, product inventory management, ski lift ticket, railway ticket, parking entry / exit management, expressway pass ticket, electronic money, etc. A data carry device is being used for. The device is
A fixed installation type interrogator called a reader / writer and a transponder called a data carrier made of a portable IC (Integral Circuit) are connected by wireless communication. For each of the interrogator and responder,
The digital signal modulator and demodulator for such wireless communication are provided.

Conventionally, BPSK is used for modulating digital data.
(Bi-Phase-shift Keying: binary phase shift keying) system was adopted. Modulation and demodulation of a signal by BPSK will be described. As shown in the time chart of FIG. 7, the digital data signal (A) to be carried is BPSK.
It is modulated into a modulation signal (B). That is, "0" of the data signal (A) is 0 ° BPSK phase, and the data signal (A) is
"1" is switched to the 180 ° BPSK phase. This BPSK modulated signal (B) is oscillated from the transmitting side. The receiving side of the data carrier device generates a reference signal (C), compares the phase with the received BPSK modulated signal (B),
The comparison output (AND output) signal (D) is detected (binarized) to obtain a demodulation signal (E).

[0004]

In the above-described conventional data carrier device, if the response timing on the receiving side is slightly different from that on the transmitting side, synchronization cannot be established, and accurate demodulation is difficult. , Was a factor that deteriorated the stability of communication. For example, as shown in the time chart of FIG. 8, when the rising edge of the reference signal (C) is slightly delayed from the rising edge of the BPSK modulated signal (B) obtained by modulating the data signal (A) (see Δ), the reference signal (C)
The comparison signal (D) between the BPSK modulated wave (B) and the BPSK modulated wave (B) produces a pulse even in a region corresponding to "0" of the data signal (A). Therefore, the demodulated signal (E) obtained by detecting and binarizing the comparison output signal (D) does not correspond to the data signal (A).

The present invention has been made in order to eliminate such a deterioration factor of communication stability in a data carrier device, and can accurately demodulate a signal from a BPSK modulated signal, and to both the interrogator and the responder. It is intended to provide an applicable demodulator.

[0006]

A phase shift keying signal demodulator of a data carrier device of the present invention made to achieve the above object is a phase shift keying signal which constitutes a radio receiving device of a data carrier device. A demodulator for generating a first reference signal, a means for generating a second reference signal having the same frequency as the first reference signal and a phase difference of 90 °, and a first reference signal Means for generating a demodulation reference signal of a logical product with the second reference signal, means for generating a comparison signal of a logical product of the demodulation reference signal and the phase shift keying signal, and binarizing the comparison signal It has a detection means for generating a demodulated signal.

This can be appropriately implemented by providing a means for switching the phase of the second reference signal by 180 ° on the way from the means for generating the second reference signal to the means for generating the demodulation reference signal.

The phase switching means operates by detecting a phase error in the demodulated signal.

A detector for detecting a phase error of the demodulated signal is provided as a trigger of the phase switching means.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of a phase shift keying signal demodulator (BPSK demodulator) of a data carrier device to which the present invention is applied. The BPSK demodulator exists as part of the circuitry within the data carrier device along with the receiving circuitry.

As shown in FIG. 1, in the BPSK demodulator, the means for generating the first reference signal (I signal) has a first oscillator 1,
The means for generating the second reference signal (Q signal) is the second oscillator 2, the AND gate 3 having means for generating the demodulation reference signal, the demodulation reference signal and the phase shift keying signal (BPSK signal)
An AND gate 5 is a means for generating a comparison signal with the AND, and a wave detector 8 is a means for binarizing the comparison signal. The I signal which is the output of the first oscillator 1 and the Q signal which is the output of the second oscillator 2 have the same frequency but are out of phase with each other by 90 °. The output of the first oscillator 1 is connected to one input of the AND gate 3, and the output of the second oscillator 2 is connected to the other input via the exclusive OR gate 4. The output of the AND gate 3 is connected to one input of the AND gate 5, and the BPSK signal is input to the other input. The output of the AND gate 5 is connected to the detector 8. The output of the detector 8 outputs a demodulated signal and is connected to the input of the exclusive OR gate 4 via the phase error detector 7.

The operation of the BPSK demodulator shown in FIG. 1 is shown in FIG.
This will be described with reference to the timing charts of FIGS. 3 and 4. The digital data signal (A) is modulated into the BPSK modulated signal (B), received by the receiving circuit, and input to the demodulator. In the BPSK demodulator, initially, the I signal from the first oscillator 1 and the Q signal from the second oscillator 2 (Q = I + 90 °)
The output of the AND gate 3 and is used as a demodulation reference signal (F) and compared with the BPSK modulated signal (B) by the AND gate 5.

As shown in FIG. 2, if there is no timing difference between the BPSK modulated signal (B) and the I signal, the comparison signal (D) from the AND gate 5 is amply output and binarized by the detector 8. Then, a demodulated signal (E) is obtained. The demodulated signal (E) is a source corresponding to the data signal (A).

As shown in FIG. 3, when the BPSK modulated signal (B) and the I signal have a timing deviation Δ, the demodulation reference signal (F) also has a timing deviation Δ from the BPSK modulated signal (B). Therefore, the pulse width at "1" of the demodulation reference signal (F) exceeds the pulse width at "1" of the BPSK modulation signal (B), and the demodulation reference signal (F)
The comparison signal (D) which is the AND output of the BPSK modulated signal (B) and the comparison signal (D) produces a pulse even in the area corresponding to "0" of the data signal (A). Therefore, the noise pulse g is also mixed in the detected demodulated signal (E) and the data signal (A)
Cannot be demodulated correctly.

The phase error detector 7 detects the noise pulse g
Is detected and the signal of "1" is sent to the exclusive OR gate 4, this becomes a toggle flag of the Q signal, the output (Q 'signal) passing through the exclusive OR gate 4 is inverted, and the phase of the signal is switched by 180 °. To be As shown in FIG. 2, the phase of the I signal is shifted by −90 ° (Q ′ = I−
90 °). Therefore, the pulse width of "1" of the demodulation reference signal (F ') which is the output of the AND gate 3 of the I signal and the Q'signal falls within the range of the pulse width of "1" of the BPSK modulated signal (B). From the demodulation reference signal (F ') and BP
Comparison signal (D) which is the AND output of SK modulation signal (B)
Does not emit a pulse in the area corresponding to "0" of the data signal (A). As a result, even if there is a timing deviation Δ between the BPSK modulated signal (B) and the I signal, the detected demodulated signal (E) has no noise and the data signal (A) can be correctly demodulated.

The BPSK demodulator of the present invention is incorporated in the data carrier device shown in FIG. The data carrier device includes a microprocessor unit (MPU) 10, a field programmable gate array (Field Programmab).
le Gate Array: FPGA) 11 and FPGA 11
It has a BPSK demodulator inside. In addition, the data carrier device includes an oscillation amplifier 12, a reception amplifier 13, and a transmission / reception antenna array 14.

In the data carrier device of this example, the FPG
When the MPU receives the demodulated signal (received data) obtained by the BPSK demodulator in A11, and when the MPU determines that the received data is not normal, it issues a toggle flag of the Q signal,
Switching the signal phase by 180 °. When the MPU takes charge of the phase error detection function of the received data in this way, it is not necessary to provide the phase error detector 7 in the BPSK demodulator shown in FIG.

In the BPSK demodulator shown in FIG. 1, the first oscillator 1 and the second oscillator 1 as means for generating the first reference signal.
Although the example in which the second oscillator 2 as a means for generating the reference signal is provided separately is shown, a delay circuit 9 for the I signal may be provided to obtain the Q signal as shown in FIG.
The delay circuit 9 delays the phase of the I signal by 90 °
The Q'signal that inverts the signal by 180 ° is switched by the toggle flag. The Q signal toggle flag is obtained by the phase error detector 7 or the phase error detecting function of the received data in the MPU.

Not only the Q signal but also the I signal can be oscillated without providing the independent first oscillator as described above.
It is optional to obtain a predetermined I signal by a frequency multiplier for the frequency of the clock incorporated in the MPU or FPGA.

[0021]

As described above in detail, the BPSK demodulator of the data carrier device to which the present invention is applied can always synchronize with the transmitting side even if the response timing of the receiving side varies. Therefore, a demodulated signal faithful to the data signal can be accurately reproduced from the BPSK modulated signal.
Therefore, stable wireless communication of the data carrier device can be realized.

[Brief description of drawings]

FIG. 1 is a BPS of a data carrier device to which the present invention is applied.
It is a block circuit diagram which shows the Example of a K demodulator.

FIG. 2 is a diagram showing an example of an operation timing chart of a BPSK demodulator to which the present invention is applied.

FIG. 3 is a diagram showing an example of an operation timing chart of a BPSK demodulator to which the present invention is applied.

FIG. 4 is a diagram showing an example of an operation timing chart of a BPSK demodulator to which the present invention is applied.

FIG. 5 is a block circuit diagram showing an embodiment of a data carrier device including a BPSK demodulator to which the present invention is applied.

FIG. 6 is a block circuit diagram showing an embodiment of a main part of a BPSK demodulator to which the present invention is applied.

FIG. 7 is a diagram showing an example of an operation timing chart of a conventional BPSK demodulator.

FIG. 8 is a diagram showing an example of an operation timing chart of a conventional BPSK demodulator.

[Explanation of symbols]

1 is a first oscillator, 2 is a second oscillator, 3 is an AND gate, 4 is an exclusive OR gate, 7 is a phase error detector, 8 is a detector, 9 is a delay circuit, 10 is an MPU, and 11 is an FPGA. , 12 is an oscillation amplifier, 13 is a reception amplifier, 14
Is a transmitting and receiving antenna array.

Claims (4)

[Claims] 1. A demodulator of a phase shift keying signal constituting a radio receiving device of a data carrier device, comprising: means for generating a first reference signal; and a first reference signal having the same frequency of 90 °. Means for generating a second reference signal having a phase difference, means for generating a demodulation reference signal of the logical product of the first reference signal and the second reference signal, and the demodulation reference signal and the phase shift keying signal A demodulator having means for generating a comparison signal of the logical product of and a detection means for binarizing the comparison signal to generate a demodulation signal. 2. The demodulation according to claim 1, further comprising means for switching the phase of the second reference signal by 180 ° on the way from the means for generating the second reference signal to the means for generating the demodulation reference signal. vessel. 3. The demodulator according to claim 2, wherein the phase switching means operates when the phase error of the demodulated signal is detected. 4. The demodulator according to claim 1, further comprising a detector that detects a phase error of the demodulated signal as a trigger of the phase switching means.