JPH02230846A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To prevent the effect of phase noise by providing a delay circuit in parallel with a carrier regenerating circuit and retarding a PSK signal inputted to a multiplier by a signal delay in the carrier regenerating circuit. CONSTITUTION:A delay circuit 2 gives a delay nearly equal to a signal delay in a carrier regenerating circuit 1 to an input PSK signal and supplies the result to other input terminal of a multiplier 3. That is, the PSK signal inputted to the multiplier 3 is retarded by a signal delay in the carrier regenerating circuit 1. As a result, let a signal delay in the carrier regenerating circuit 1 be tau and the delay in the delay circuit 2 be tau', then phase jitter theta2J in the multiplier 3 caused by phase noise is expressed as beta(tau-tau')+gamma(tau-tau')<2>. That is, when a difference between tau and tau' is decreased, the phase jitter can be decreased. Thus, the effect of the phase noise is much decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a demodulation circuit for PSK (phase shift keying) signals, and more particularly to improvement of a demodulation circuit using a synchronous detection method. (Prior Art) As is well known, PSK signal demodulation circuits include those using a synchronous detection method and those using a delayed detection method. For example, as shown in FIG. 3 (1), the synchronous detection method uses a carrier regeneration circuit 31 that regenerates a carrier (carrier wave) from an input PSK signal, and synchronizes the input PSK signal using the regenerated carrier (reference carrier wave). It basically consists of a multiplier 32 for detection. There are various carrier regeneration methods, but a frequency multiplication method consisting of a multiplier circuit, a bandpass filter, and a frequency divider circuit is often used. This synchronous detection method uses C/
It is characterized by good N (carrier-to-noise ratio) characteristics.
In satellite communications, a PLL (phase lock loop) circuit is used in the bandpass filter of the carrier regeneration circuit to narrow the band and further improve the C/N characteristics. On the other hand, the delayed detection method, as shown in FIG. 3 (2), includes a delay circuit 34 that delays the input PSK signal by one time slot, and a multiplier that synchronously detects the input PSK signal using the output of this delay circuit 34. It basically consists of 35.
In this delayed detection method, the same level of noise as the input PSK signal is added to the signal corresponding to the recovered carrier (reference carrier) in the synchronous detection method, so the bit error rate characteristics are better than in the synchronous detection method. It is also known that it is inferior.
However, this delayed detection method has the advantage of not requiring a reference carrier wave, so in demodulating the 2-P;K signal,
It is sometimes used because it can obtain bit error rate characteristics that are not much different from those of the synchronous detection method. <<Problems to be Solved by the Invention>> However, in the conventional demodulation circuit using the synchronous detection method, phase noise may be superimposed on the carrier of the input PSK signal in the transmission path. In this case, if the equivalent bandwidth of the carrier recovery circuit is narrowed, there is a problem in that the bit error rate of demodulated data deteriorates due to phase jitter caused by phase noise. Incidentally, this phase jitter 《θ1》 is approximately θ the βτ + γτ·《1》, where τ is the signal delay amount ``group delay amount'' generated in the carrier recovery circuit. However, β and γ are quantities representing the phase jitter of the input carrier, and represent terms resulting from Brownian motion and 1/f drift, respectively, and the phase of the input carrier and the phase noise power spectrum SIω are determined by these two terms. It is expressed as By the way, in future satellite communications, it is expected that higher frequencies will be used and low-speed communications such as so-called personal communications will expand, but generally speaking, the higher the frequency, the greater the frame noise, and the lower the speed, the greater the noise. However, since the group delay τ of the carrier regeneration circuit becomes large, it is desired to develop a phase noise removal technique. The present invention was made in view of these problems, and its purpose is to provide a demodulation circuit using a synchronous detection method that can suppress the influence of phase noise. <Means for Solving the Problems> In order to achieve the above object, the demodulation circuit of the present invention has the following configuration. That is, the demodulation circuit of the present invention, as shown in FIG. a delay circuit 2 that applies a delay amount equal to the signal delay amount and outputs the signal; a multiplier 3 that receives the output of the carrier recovery circuit 1 and the output of the delay circuit 2 and performs synchronous detection; <Operation> Next, the operation of the demodulation circuit of the present invention configured as described above will be explained. The amount of signal delay in the carrier regeneration circuit 1 is τ. The amount of delay in the delay circuit 2 is τ. ′, the phase jitter θ caused by phase noise in the multiplier 3 is expressed by the above formula 《
1》, θte=β《τ1τ'》10γ(τ1τ')2
(3). In other words, by reducing the difference between τ and ′, the phase jitter can be reduced. Thus, according to the demodulation circuit of the present invention, the demodulation circuit uses a synchronous detection method. In this method, a delay circuit is installed in parallel with the carrier regeneration circuit, and the PSK signal input to the multiplier is delayed by the signal delay in the carrier regeneration circuit, which suppresses the effects of phase noise and provides good C/N characteristics. Synchronous detection. The original characteristics of the method can be fully demonstrated. <<Example>> Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 2 shows a demodulation circuit according to an embodiment of the present invention. Second
In the figure, an input PSK signal is input to a carrier recovery circuit 1 and a delay circuit 2, respectively. Carrier regeneration circuit 1
is of a frequency multiplication type, and in this embodiment, it is composed of a multiplying circuit 11, a PLL circuit 12, and a frequency dividing circuit 13. For example, when the input PSK signal is a 2-PSK signal, the signal multiplied by 2 in the multiplying circuit 11 is subjected to phase synchronization control in the PLL circuit 12, and the signal for which phase synchronization has been established is subjected to phase synchronization control in the frequency dividing circuit 13. If you divide the frequency by 2 at
You will get a regenerated carrier. This reproduced carrier is supplied to one input terminal of the multiplier 3 as a reference carrier wave. The delay circuit 2 applies a delay amount approximately equal to the signal delay amount in the carrier regeneration circuit 1 to the input PSK signal, and
Supplied to the other input terminal of multiplier 3. That is, multiplier 3
The PSK signal input to the carrier regeneration circuit 1 is delayed by the signal delay in the carrier regeneration circuit 1. As a result, the phase jitter that occurs during synchronous detection in the multiplier 3 is expressed by the above equation (3), but since the difference between τ and τ' can be made as small as possible, the influence of phase noise can be minimized. can do. (Effects of the Invention) As explained above, according to the demodulation circuit of the present invention, in a demodulation circuit using a synchronous detection method, a delay circuit is arranged in parallel with a carrier recovery circuit, and the PSK signal input to the multiplier is transferred to the carrier recovery circuit. Since the signal is delayed by the signal delay in , the influence of phase noise can be suppressed and the original characteristics of the synchronous detection method, such as good C/N characteristics, can be fully demonstrated. In particular, in satellite communication, mobile satellite communication has become possible with the advancement of satellite communication technology, but this system uses higher frequencies to transmit slower signals.
The effect of phase noise becomes even more pronounced. In this case, demodulation circuits based on digital signal processing are widely used due to low-speed communication, but digital signal processing makes it possible to accurately match the amount of signal delay in the carrier regeneration circuit with the amount of delay in the delay circuit. , the use of the demodulation circuit of the present invention has the effect of eliminating characteristic deterioration due to phase noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a demodulation circuit according to the present invention, FIG. 2 is a block diagram of a demodulation circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional demodulation circuit. 1... Carrier regeneration circuit, 2... Delay circuit, 3... Multiplier, 11... Multiplier circuit, 12... PLL circuit , 13...
...Frequency dividing circuit. Agent: Patent Attorney Yoshi Yahata Hiromoto Rakuhan Alpha Submissive A Circuit No. 2 j5mi) The 4l Nagi episode of ``1 Narisugi'' of the 4l Nagi episode. 3rd ward

Claims (1)

[Claims] a carrier regeneration circuit that regenerates a carrier from an input PSK (phase shift keying) signal; a delay circuit that applies a delay amount approximately equal to a signal delay amount in the carrier regeneration circuit to the input PSK signal and outputs the signal; and the carrier regeneration circuit. A demodulation circuit comprising: a multiplier that performs synchronous detection upon receiving the output of the circuit and the output of the delay circuit.