JP2003078051A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To structure a memory transistor having a charge storage means suitable when made fine. SOLUTION: This device has a first conductive semiconductor substrate SUB, a gate insulating film, and a gate electrode WL formed on the semiconductor substrate. The device is internally provided with the charge storage means and has a second conductive source area S and a drain area D formed on the surface area of the semiconductor substrate on one side and the other side of the gate electrode WL in the width direction. A source contact plug SC is formed on one terminal of the source area S orthogonal in the width direction of its gate electrode WL. A bit contact plug BC is formed on the other terminal of the drain area D orthogonal in the width direction of its gate electrode. A source line SL is electrically connected to the source contact plug SC, and a bit line BL is electrically connected to the bit contact plug BC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a charge storage means inside a gate insulating film.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory is an FG in which charge storage means (floating gate) for holding charges are planarly continuous.
In addition to the (Floating Gate) type, the charge storage means (charge trap) is planarly discretized, for example, MONOS (Met
al-Oxide-Nitride-Oxide Semiconductor) type.

In an FG type non-volatile memory transistor, a floating gate made of polysilicon or the like is laminated on a semiconductor channel formation region via a gate insulating film, and further, for example, ONO (Oxide-Nitride-) is formed on the floating gate. The control gate is laminated via an inter-gate insulating film made of an oxide film or the like.

On the other hand, in a MONOS type non-volatile memory transistor, a tunnel insulating film made of, for example, a silicon oxide film or a nitride oxide film, an intermediate insulating film made of a nitride film or a nitride oxide film is formed on a semiconductor channel formation region. , A top oxide film made of a silicon oxide film is sequentially stacked, and a gate electrode is formed on the top insulating film.

In a MONOS type non-volatile semiconductor memory, a nitride film [Si _x N _y, which is mainly responsible for holding charges, is used.
(0 <x <1, 0 <y <1)] Carrier traps in the film or at the interface between the top oxide film and the nitride film are spatially (that is, in the plane direction and the film thickness direction) discretely spread. . For this reason, the charge retention characteristics depend not only on the tunnel insulating film thickness but also on the energy and spatial distribution of the charges trapped by the carrier traps in the Si _x N _y film.

When a leak current path locally occurs in the tunnel insulating film, in the FG type, a large amount of charge leaks through the leak path, and the charge retention characteristic is likely to deteriorate. On the other hand, in the MONOS type, since the charge storage means is spatially discrete, the local charges around the leak path only leak locally through the leak path, and the charge retention characteristic of the entire storage element deteriorates. Hard to do. Therefore, MO
In the NOS type, the problem of deterioration of charge retention characteristics due to thinning of the tunnel insulating film is not as serious as in the FG type. Therefore, the scaling property of the tunnel oxide film in a fine memory transistor having an extremely short gate length is MON.
The OS type is superior to the FG type.

[0007]

The above-mentioned FG type non-volatile memory or non-volatile memory such as MONOS type in which the charge storage means of the memory transistor is planarized is reduced in cost per bit and highly integrated. In order to realize a large-scale non-volatile memory by realizing the above, it is essential to realize a one-transistor cell structure. However, particularly in a MONOS type non-volatile memory, a two-transistor type in which a selection transistor is connected to a memory transistor is the mainstream, and various studies are currently being made toward establishment of a one-transistor cell technology.

An object of the present invention is to provide a non-volatile semiconductor memory device having a structure suitable for miniaturization of a memory transistor which basically operates by accumulating charges in a charge accumulating means in a gate insulating film.

[0009]

A nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate of a first conductivity type, a gate insulating film formed on the semiconductor substrate and including charge storage means inside. A gate electrode formed on the gate insulating film, a source region of the second conductivity type formed on a surface region of the semiconductor substrate on one side in the width direction of the gate electrode, and a width of the gate electrode. The second conductivity type drain region formed on the surface region of the semiconductor substrate on the other side in the direction, and the source formed on one end of the source region in a direction orthogonal to the width direction of the gate electrode. A contact plug; a bit contact plug formed at the other end of the drain region in a direction orthogonal to the width direction of the gate electrode;
A source line electrically connected to the plug and a bit line electrically connected to the bit contact plug.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a diagram showing a schematic configuration of a source-isolated NOR type nonvolatile semiconductor memory according to an embodiment of the present invention.

In the non-volatile memory device 90 of this example,
Each memory cell of the NOR type memory cell array is composed of one memory transistor. As shown in FIG. 1, the memory transistors M11 to M22 are arranged in a matrix,
A word line, a bit line, and a separate source line are connected between these transistors. That is, the drains of the memory transistors M11 and M12 adjacent in the column direction are connected to the bit line BL1 and the sources are connected to the source line SL1. Similarly, the drains of the memory transistors M21 and M22 adjacent in the column direction are connected to the bit line BL2, and the sources are connected to the source line SL.
Connected to 2. Further, the gates of the memory transistors M11 and M21 adjacent in the row direction are connected to the word line WL1.
Similarly, each gate of the memory transistors M12 and M22 adjacent in the row direction is connected to the word line WL2. Such cell arrangement and inter-cell connection are repeated in the entire memory cell array.

FIG. 2 is a schematic plan view of a fine NOR type cell array using a self-alignment technique as an example of a specific cell arrangement pattern. FIG. 3 is a perspective view seen from the cross-section side along the line AA ′ in FIG. 2.

In this fine NOR type cell array 100,
As shown in FIG. 3, an element isolation insulating layer 102 is formed from a trench, LOCOS, or the like on the surface of a P-type semiconductor substrate 101 (may be a P well). Element isolation insulation layer 1
As shown in FIG. 2, 02 are arranged in parallel stripes that are long in the column direction (vertical direction in FIG. 2). The word lines WL1, WL2, and the word lines WL1, WL2 are substantially orthogonal to the element isolation insulating layer 102.
WL3, WL4, ... Are wired at equal intervals. This word line has a tunnel insulating film, a nitride film, a
It is configured by stacking a gate insulating film made of a top insulating film and a gate electrode. In this embodiment, the gate length (word line width) is 0.13 μm or less, for example, 0.1.
It is miniaturized to μm.

In the active region within the space of each element isolation insulating layer 102, a source region S and a drain region D are alternately formed by introducing a high concentration of, for example, N-type impurities into the space between the word lines. There is. The sizes of the source region S and the drain region D are in the row direction (horizontal direction in FIG. 2).
Is a device isolation insulating layer 10 such as a trench or LOCOS.
It is defined only by the interval of 2 and only by the word line interval in the column direction. Therefore, the source region S and the drain region D are formed extremely uniformly because almost no mask alignment error is introduced with respect to variations in size and arrangement.

The upper part and the side wall of the word line are covered with an insulating layer. That is, the offset insulating layer is arranged in the same pattern on the word lines WL1, WL2, ...
Sidewall insulating layers are formed on both side walls of a laminated pattern including an offset insulating layer, a gate electrode (word line) thereunder, and a gate insulating film. The offset insulating layer and the sidewall insulating layer form elongated self-aligned contacts along the word lines in the space portions between the word lines.

The self-aligned contacts are alternately filled with conductive materials so as to partially overlap the source region S or the drain region D, thereby forming the bit contact plug BC and the source contact plug SC. In forming the bit contact plug BC and the source contact plug SC, a conductive material is deposited so as to fill the entire area of the self-aligned contact, and a resist pattern for an etching mask is formed thereon. At this time, the resist pattern is made slightly larger than the width of the self-aligned contact, and a part thereof is overlapped with the element isolation insulating layer. Then, using this resist pattern as a mask, the conductive material around the resist pattern is removed by etching. As a result, the bit contact plug BC
And the source contact plug SC is formed at the same time.

A recess around the contact is filled with an insulating film (not shown). Bit lines BL1, BL2, which come into contact with the bit contact plug BC on the insulating film,
, And the source lines SL contacting the source contact plugs SC are alternately formed in parallel stripes.

In this fine NOR type cell array 100, contact formation for the bit line or the source line is
This is achieved by forming self-aligned contacts and forming plugs. By forming the self-aligned contact, insulation isolation from the word line is achieved, and the exposed surface of the source region S or the drain region D is uniformly formed. The bit contact plug BC and the source contact plug SC are formed on the exposed surface of the source region S or drain region D in this self-aligned contact contact. Therefore, the size of the plug contact surface of the plug in the column direction is determined by the formation of substantially self-aligned contacts, and the variation in the contact area is correspondingly small.

The bit contact plug BC or the source contact plug SC and the word line can be easily insulated and separated. That is, the sidewall insulating layer is formed only by forming the offset insulating layer collectively at the time of forming the word line, and then forming the insulating film and etching the entire surface (etchback). Further, since the bit contact plug BC and the source contact plug SC, and the bit line and the source line are formed by patterning the conductive layers of the same layer, the wiring structure is extremely simple and the number of steps is small. The structure is advantageous for keeping the manufacturing cost low. Moreover, since there is almost no wasted space, the formation of each layer is performed with the minimum line width F of the wafer process limit.
In the case of (1), it can be manufactured with a very small cell area close to 8F ² .

FIG. 4 is a sectional view showing the element structure of the MONOS type memory transistor according to this embodiment.

In FIG. 4, reference numeral 1 is a semiconductor substrate or well such as a silicon wafer having N-type or P-type conductivity,
Reference numeral 1a indicates a channel forming region, and 2 and 4 indicate a source region and a drain region of the memory transistor. In the present invention, the “channel forming region” refers to a region where a channel through which electrons or holes are conducted is formed inside the surface side. The “channel forming region” in this example corresponds to a portion of the semiconductor substrate or well 1 sandwiched between the source region 2 and the drain region 4. The source region 2 and the drain region 4 are
This is a region having a high conductivity formed by introducing an impurity of the conductivity type opposite to that of the channel formation region 1a into the semiconductor substrate 1 in a high concentration, and has various forms. Usually source area 2
In many cases, a low concentration region called LDD (Lightly Doped Drain) is provided at a substrate surface position facing the channel formation region 1a of the drain region 4.

A gate electrode 8 of the memory transistor is laminated on the channel forming region 1a with a gate insulating film 6 interposed therebetween. The gate electrode 8 is generally made of polysilicon (doped poly-Si) in which a P-type or N-type impurity is introduced at a high concentration to make it conductive, or a laminated film of doped poly-Si and a refractory metal silicide. . The length of the gate electrode 8 in the channel direction (gate length) is 0.13 μm or less, for example, about 0.1 μm.

The gate insulating film 6 in this embodiment is composed of a tunnel insulating film 10, a nitride film 12, and a top insulating film 14 in order from the bottom layer. Tunnel insulating film 10
Is silicon oxide (SiO2) formed by thermal oxidation
However, in this example, a short time thermal oxidation method (RTO method) is used.
To form an oxide film by thermal nitriding (RT
N treatment). The film thickness of the tunnel insulating film 10 can be determined within the range of 2.0 nm to 3.5 nm depending on the intended use.
It is set to 7 nm.

The nitride film 12 is formed of, for example, a 5.0 nm silicon nitride (Si _x N _y (0 <x <1, 0 <y <1)) film. This nitride film 12 is formed under reduced pressure C, for example.
It is produced by VD (LP-CVD) and contains many carrier traps in the film. The nitride film 12 exhibits pool Frenkel type (PF type) electric conduction characteristics.

The top insulating film 14 needs to have deep carrier traps formed at a high density in the vicinity of the interface with the nitride film 12. Therefore, for example, the top insulating film 14 is formed by thermal oxidation of the nitride film after film formation. When the top insulating film 14 is formed by CVD, this trap is formed by heat treatment. The thickness of the top insulating film 14 is at least 3.0 nm, preferably 3.5 nm, in order to effectively prevent injection of holes from the gate electrode 8 and prevent a decrease in the number of times data can be rewritten.
The above is necessary.

By the way, in designing a miniaturized memory transistor, the minimum channel length L is usually calculated by using the Brews equation shown in the following equation (1) as an empirical equation for suppressing the short channel effect for CMOS logic devices and the like.
min is decided.

[0027]

## EQU1 ## Lmin = 0.4 × [rj × d × (Ws + Wd) ² ] ^1/3 (1)

Here, rj is the junction depth of the source / drain impurity regions, d is the gate insulating film thickness converted to a silicon oxide film, Ws is the length of the depletion layer extending from the source end,
Wd represents the length of the depletion layer extending from the drain end. The Brews equation is defined to include the short channel effect to some extent, and the degree of the decrease is within 10% of the threshold in the long channel (roll-off). The specification of roll-off within 10% is used in a normal logic transistor or a DRAM memory transistor in order to suppress variation in threshold value.

According to this equation, the minimum channel length is 0.13
The channel impurity concentration is 1 × 10 ¹⁸ cm at a gate length (corresponding to a gate length of about 0.18 to 0.23 μm).
^-3 , when the oxide film conversion value of the gate insulating film is set to 9.5 nm, LDD is effective for suppressing the short channel effect.
It can be seen that it is necessary to make the junction depth of 50 nm or less. On the other hand, it was also found that when the LDD junction depth was made shallower, the junction breakdown voltage decreased. In a one-transistor type MONOS memory cell, it is essential for normal operation to apply a so-called write inhibit voltage, which reverse biases the PN junction to the source / drain region of the non-selected cell at the time of writing, as described later. Therefore, further reduction of the source-drain junction breakdown voltage makes it difficult to realize a one-transistor type MONOS memory cell with a fine gate length of 0.13 μm or less. In other words, the design specification of a normal CMOS logic device that keeps roll-off within 10% is 0.13 μ.
1-transistor MO with a fine gate length of m or less
It has been found that it is difficult to directly apply it to the NOS memory cell.

Therefore, in the present embodiment, the threshold roll-off is intentionally allowed to be 10% or more, thereby expanding the design margin of the impurity concentration profile of the channel forming region and the source / drain region, and as a result,
We propose to improve the source-drain junction breakdown voltage as a new design guide for miniaturization to a gate length of 0.13 μm or less. As a result, the write disturb voltage can be applied, and the MONOS memory transistor can be further miniaturized.

Specifically, in the memory transistor according to the present embodiment (FIG. 4), although not shown, a retrograde well having an impurity concentration peak deeper than the surface is used to define the impurity concentration profile of the channel forming region. The peak impurity concentration is 5 to 20 × 10 ¹⁷ cm
Within the range of ⁻³ , the LDD junction depth is set to 100 nm or less. The oxide film thickness conversion value of this gate insulating film 6 is 10
In the case of nm or less, the roll-off of the threshold value is allowed to be 15% or more (and 50% or more in some cases). With such a concentration profile design, the gate length is 0.1
A MONOS memory transistor of about μm has been realized.

In manufacturing the memory transistor having such a structure, first, the semiconductor substrate 1 thus prepared is subjected to formation of an element isolation region, formation of a well, ion implantation for adjusting a threshold voltage, etc., if necessary. At the time of forming the well, an impurity concentration profile design for increasing the junction breakdown voltage with the source / drain regions to be formed later is performed, if necessary, based on the above-mentioned design guideline. Next,
A laminated film of the gate insulating film 6, the gate electrode 8, and the offset insulating layer (not shown) is laminated on the active region of the semiconductor substrate 1 by the above-mentioned material, film thickness and each film forming method, and the laminated film is collectively formed. Process with the same pattern. If the tunnel insulating film 10 of the gate insulating film 6 (ONO film: tunnel insulating film / nitride film / top insulating film) is thickened to, for example, about 3 nm, the typical value of the ONO film thickness specification is 3 each. It is set to 0.0 nm / 5.0 nm / 3.5 nm. In this case, the converted value of the silicon oxide film thickness of the ONO film is 9 nm. The source / drain regions 2 and 4 are formed in self-alignment with the formed laminated pattern. At this time, the impurity concentration profile design for increasing the junction breakdown voltage is performed based on the design guideline described above. Subsequently, a self-aligned contact is formed by forming a sidewall insulating layer, and a bit contact plug BC and a source contact plug SC are formed on the source / drain regions 2 and 4 exposed by the self-aligned contact. After filling the periphery of these plugs with an interlayer insulating film and forming bit lines and source lines on the interlayer insulating film, formation of upper layer wiring through an interlayer insulating layer and overcoat film formation and pad opening process, etc., which are performed as necessary Then, the nonvolatile memory transistor is completed.

In this embodiment, as a means for further improving the disturb characteristic, as shown in FIG. 1, the source region 2 and / or the drain region 4 (of the non-selected memory transistor) connected to the common line in the column direction are formed. Write inhibit voltage supply circuit 9 for applying a reverse bias voltage to (FIG. 4)
2 and the gate electrode 8 of the non-selected cell connected to the word line
And a non-selected word line bias circuit 94 for applying a reverse bias voltage to the channel formation region 1a.

Here, the "common line" refers to a line in which a source region or a drain region is commonly directly connected or capacitively coupled between a plurality of memory transistors in a column direction (column direction), for example, a bit line or a line. Besides the source lines, so-called booster plates and the like are applicable. FIG. 1 shows a case where the common line is a bit line and a source line. The "reverse bias voltage" means a voltage in the direction of reverse biasing a PN junction formed between a source region or a drain region and a bulk region of a semiconductor substrate or a semiconductor layer in which a channel formation region is formed. . Further, "the direction in which the channel forming region is reverse biased" refers to the direction in which the voltage application based on the potential of the channel forming region is the positive side or the negative side. Specifically, when the conductivity type of the channel formation region is the P type, the relevant direction is the positive side, and when it is the N type, the relevant direction is the negative side.

The write inhibit voltage supply circuit 92 and the non-selected word line bias circuit 94 apply a predetermined voltage to the gate electrode 8, the source region 2 and the drain region 4 of the non-selected memory transistor prior to programming the selected cell. This prevents erroneous writing or erasing of the non-selected cells A and B in FIG. 1 and significantly improves the program disturb margin.

Next, the write operation of the nonvolatile memory having such a configuration will be described.

Here, as shown in FIG. 1, the non-selected cells A to C are defined by the connection relationship with the selected cell S. That is, a non-selected cell connected to the same selected word line WL1 as the selected cell S is A, and a cell connected to the non-selected word line WL2 is connected to the same selected source line SL1 and selected bit line BL1 as the selected cell S. The selected unselected cells are connected to the selected word line WL2, and the unselected cells connected to the unselected source line SL2 and the unselected bit line BL2 are set to B.
It is defined as

FIG. 5 shows an example of write bias voltage setting conditions for these four types of cells. When writing data to the selected cell S, first, the non-selected word line bias circuit 9
4, the selected word line WL1 and the non-selected word line W
When the substrate potential of 0V is applied to L2, a predetermined voltage, for example 4.5.
Apply V. Further, the write inhibit voltage supply circuit 92 applies a predetermined reverse bias voltage, for example, 5V to the non-selected source line SL2 and the non-selected bit line BL2 when the substrate potential is 0V. At this time, the selected source line S
L1 and the selected bit line BL1 are held at the ground potential 0V. In this state, the word line W to which the selected cell S is connected
The applied voltage of L1 is increased from a predetermined voltage (4.5V) to a program voltage (for example, 12V).

FIG. 6A shows an MO having a gate length of 0.1 μm.
7 shows a hysteresis characteristic of a NOS type nonvolatile memory transistor. Further, FIG. 6B shows a typical write / erase characteristic. As shown in FIG. 6A, a good memory hysteresis voltage difference (hysteresis window) was obtained. As a condition for obtaining a sufficient threshold window width, the write time is the word line applied voltage 1
0.7msec at 2V, 1m at 11V applied to word line
sec, and the erase time was 80 msec when a voltage of -8 V was applied.

In this writing method, the non-selected word line W
By applying, for example, a positive voltage to L2, the disturb margin of the non-selected cell B is expanded and the non-selected cell B is not erroneously written or erased. Further, by applying the reverse bias voltage to the non-selected bit line BL2 and the non-selected source line SL2, it is possible to prevent the non-selected cell A from being in the writing state by the application of the program voltage of the selected word line WL1 and to perform the non-selection. The cell B is not erroneously written (and erased). When the bias voltage is applied at this time in the order of voltage application to the non-selected word line, reverse bias voltage application, and program voltage application as described above, it is preferable that the non-selected cells B are less likely to be disturbed.

Although the prevention of disturb has been described above, it has been investigated that the increased breakdown voltage (junction breakdown voltage) of the source and drain is a level that does not cause a problem when reverse bias is applied, and the dependency of the inhibit voltage on the gate length is examined. It is also necessary to confirm the main device characteristics.

[Withstand Voltage of Memory Transistor] The current-voltage characteristics of the memory transistor in the erased state were examined under the condition of the gate voltage of 4 V and the channel impurity concentration as a parameter. The results are shown in the graph of FIG. Here, the junction breakdown voltage is defined by a drain current of 1 nA / μm.
From the graph, the junction breakdown voltage depends on the channel impurity concentration,
The junction breakdown voltage tends to decrease as the channel impurity concentration increases. Channel impurity dose is 15 × 10 ¹²
In the case of cm ⁻² , the highest peak concentration is shown, and the value is 7 to 8 × 10 ¹⁷ cm ⁻³ . At this time, a junction breakdown voltage of 7V was obtained.

[Gate Length Dependence of Inhibit Voltage] FIG. 8 shows the gate length dependency of the lower limit value of the source / drain inhibit voltage. Write voltage Vpp is 1
The lower limit value of the inhibit voltage under the conditions of up to 2V was about 5V, and the gate length dependency was hardly shown. However, the write voltage Vpp is slightly dependent on the write voltage Vpp.
pp is 10V, and the lower limit of inhibit voltage is 4 to 4.3.
It has dropped to about V.

Further, the gate voltage dependence of the current-voltage characteristic in the erased state was examined. The breakdown voltage did not show the gate voltage dependence, and the rising voltage in the sub-breakdown region showed the gate voltage dependence. It is presumed that the sub-breakdown region is caused by the band-to-band tunnel phenomenon on the surface of the drain / source region at the gate edge portion, but since the current level is small, it is considered that there is no problem here.

From the above, the junction withstand voltage of about 7 V is
Although the lower limit of the drain applied voltage (inhibit S / D voltage) is about 5 V, there is a sufficient margin, and thus it was confirmed that the inhibit voltage can be applied to the source region and / or the drain region. . Also,
From FIG. 7, when the write voltage Vpp is set to 10 V, the lower limit of the inhibit voltage is lowered to about 4 V, so that the peak impurity concentration of the channel formation region is 2 × 10 ¹⁸ cm ^−3.
As a result, it was found that the memory transistor operates without any problem even if the junction breakdown voltage is set to 5V.

[Main device characteristics] Current in erased state-
The voltage dependence of the read current and the leak current obtained by examining the voltage characteristics is shown in the graph of FIG. When the gate voltage was 0V, the leak current value of the non-selected cell was about 3 nA at the drain voltage of 1.2V. The read current in this case is 30
Since it is μA or more, it is considered that erroneous reading of non-selected cells does not occur. Therefore, the gate length is 0.1
It was found that there is a sufficient margin of the punch-through breakdown voltage at the time of reading in the MONOS type memory transistor of μm.

The read disturb characteristic after 100,000 times of data rewriting was also evaluated, and the result is shown in FIG. It was found that the threshold window width after 10 years after data rewriting 100,000 times was 0.5 V or more, which was a level that could be sufficiently detected by the sense amplifier. Therefore, it was found that the read time of 10 years or more is possible.

Writing condition (program voltage: 12 V,
Data rewriting characteristics under a program time: 0.7 msec) and an erase condition (gate voltage during erase: -8 V, erase time: 80 msec) were examined, and the results are shown in FIG. It was found that the number of times of data rewriting was good because the carrier traps were spatially discretized, and satisfied 1 × 10 ⁵ times. Also, although the data is not shown here,
It was also confirmed that the data could be rewritten 1 × 10 ⁶ times. In addition, the data retention characteristics satisfied 85 ° C. for 10 years after the data was rewritten 1 × 10 ⁵ times.

From the above, by changing the impurity concentration profile of the channel forming region, the source region and the drain region from the optimum value for the short channel effect to improve the junction breakdown voltage, the gate length is scaled to 0.1 μm. It was confirmed that a non-volatile memory transistor was realized and sufficient characteristics were obtained. In addition, we were able to verify the actual cell operation.

In a non-volatile memory device, since there is usually a sequence in which the threshold values of the memory transistors are made uniform in the erased state by erase verification, it is easy to compensate for the threshold voltage drop of each memory transistor. You can Therefore, the relaxation of the threshold roll-off specification in the non-volatile memory does not pose a problem as much as the logic device.

[Second Embodiment] In the present embodiment, the gate length is scaled up to 85 nm in the same device structure as in FIG.

FIG. 12 shows a MONOS having a gate length of 85 nm.
Shows the current-voltage characteristics of the type memory transistor. From the figure, it can be seen that the junction breakdown voltage is 7V and there is a sufficient margin with respect to the source / drain inhibit voltage of 5V.

FIG. 13 also shows the read current from the selected cell and the leak current from the non-selected cell. Since the gate length is scaled from 100 nm in the first embodiment to 85 nm, an increase in leak current due to punch-through current was expected when the drain voltage was scaled to 1.1 V accordingly.
However, in practice, the impurity concentration of the channel formation region could be increased to a peak concentration of 8 × 10 ¹⁷ cm ⁻³ ,
The ratio of the read current to the leak current is such that the gate length is 0.1 μm.
Although it is slightly smaller than the case of m, it is as large as three digits or more.

FIG. 14 shows the read current characteristic of the memory cell in the erased state. Read drain voltage 1.1V
When scaled to, the read current was 33.5 μA / μm at a read gate voltage of 1.5 V and 59.7 μA / μm at a read gate voltage of 2 V.

FIG. 15 shows the data rewriting characteristic of a MONOS memory transistor having a gate length of 85 nm. It was found that the threshold window width up to 100,000 times is sufficiently large and data can be rewritten up to 100,000 times. Although no data is shown, it was confirmed that the data can be rewritten up to 1 million times.

FIG. 16 shows the read disturb characteristic after 10,000 times of data rewriting. The window width of the threshold value obtained by extrapolating the measured value is 0.5 V or more after 10 years. As a result, it can be seen that continuous reading for 10 years is possible.

As described above, by increasing the impurity concentration of the channel formation region to a peak concentration value of 8 × 10 ¹⁷ cm ⁻³ , a MONOS type nonvolatile memory having a gate length of 85 nm and a gate length of less than 0.1 μm is realized. It was confirmed that it was possible.

Hereinafter, modified examples of the element structure of the non-volatile memory will be shown in the third and fourth embodiments.

[Third Embodiment] In this embodiment, as a charge storage means of a memory transistor, a nonvolatile memory using a large number of mutually insulated Si nanocrystals embedded in a gate insulating film and having a grain size of, for example, 10 nanometers or less is used. Semiconductor memory device (hereinafter referred to as Si nanocrystal type).

FIG. 17 is a sectional view showing the element structure of this Si nanocrystal type memory transistor. The Si nanocrystal type nonvolatile memory of the present embodiment is different from the first embodiment described above in that the gate insulating film 30 of the present embodiment is replaced by the tunnel insulating film 10 instead of the nitride film 12 and the top insulating film 14.
That is, it is formed of the Si nanocrystal 32 as the upper charge storage means and the oxide film 34 thereon. Other configurations, that is, the semiconductor substrate 1, the channel forming region 1a, the source region 2, the drain region 4, the tunnel insulating film 10, and the gate electrode 8 are the same as those in the first embodiment.

The size (diameter) of the Si nanocrystal 32 is
However, it is preferably 10 nm or less, for example, about 4.0 nm, and the individual Si nanocrystals are spatially separated by the oxide film 34 at intervals of, for example, about 4 nm. The tunnel insulating film 10 in this example is slightly thicker than that in the first embodiment because the charge storage means (Si nanocrystal 32) is close to the substrate side, and the thickness of 2.6 nm to 5.
It can be appropriately selected within the range of 0 nm. Here, 4.
The film thickness was about 0 nm.

In the manufacture of the memory transistor having such a structure, after forming the tunnel insulating film 10, a plurality of Si nanocrystals 32 are formed on the tunnel oxide film 10 by, for example, the plasma CVD method. In addition, the oxide film 34 is filled with the Si nanocrystal 32 by, for example, about 7 nm by LP-CV.
The film is formed by D. In this LP-CVD, the source gas is a mixed gas of DCS and N2 O, and the substrate temperature is, for example, 700 ° C.
And At this time, the Si nanocrystal 32 is embedded in the oxide film 34, and the surface of the oxide film 34 is flattened. If the planarization is insufficient, a new planarization process (for example, CMP)
Good to do. After that, the gate electrode 8 is formed, and a step of collectively patterning the gate laminated film is performed to complete the Si nanocrystal type memory transistor.

Si nanocrystal 32 formed in this way
Functions as a carrier trap discretized in the plane direction. The trap level can be estimated by a band discontinuity value with surrounding silicon oxide, and the estimated value is about 3.
It is set to about 1 eV. Individual Si nanocrystals 32 of this size can hold several injected electrons. The Si nanocrystal 32 may be made smaller to hold a single electron.

With respect to the Si nanocrystal type nonvolatile memory having such a structure, the data retention characteristic was examined by the Landkist back tunneling model. In order to improve the data retention characteristics, it is important to deepen the trap level and increase the distance between the center of charge and the semiconductor substrate 1. Therefore, a trap level 3.1e was obtained by a simulation using the Landkist model as a physical model.
Data retention for V was examined. As a result, it was found that the use of a deep carrier trap with a trap level of 3.1 eV shows good data retention even when the distance from the charge retention medium to the channel formation region 1a is relatively close to 4.0 nm. The street results were obtained.

Similar to the first embodiment, the gate length is 0.
The operation of a 1-transistor cell having a 1 μm fine memory transistor was confirmed. Next, low voltage programming was considered. The write time in this example was 1 msec or less at a low program voltage of 5 V, and the high-speed writeability of the Si nanocrystal type was verified.

[Fourth Embodiment] In the present embodiment, a nonvolatile semiconductor memory device (hereinafter referred to as "fine division") using a large number of fine division type floating gates embedded in an insulating film and separated from each other as a charge storage means of a memory transistor. FG
Type).

FIG. 18 is a sectional view showing the element structure of this finely divided FG type memory transistor. The finely divided FG nonvolatile memory according to the present embodiment is different from the first embodiment described above in that the memory transistor is formed on the SOI substrate, and that the gate insulating film 40 according to the present embodiment is the nitride film 12 In place of the top insulating film 14, the finely divided floating gate 42 as the charge storage means on the tunnel insulating film 10 and the oxide film 44 thereon are formed between the gate electrode 8. is there. Among the other configurations, the tunnel insulating film 10 and the gate electrode 8 are the same as those in the first embodiment. The finely divided floating gate 42 corresponds to a specific example of the “small grain conductor” in the present invention together with the Si nanocrystal 32 of the third embodiment.

As the SOI substrate, SIMOX (Separation by Impl) in which oxygen ions are ion-implanted into a silicon substrate at a high concentration and a buried oxide film is formed at a position deeper than the substrate surface.
Anted Oxygen) substrate, or a bonded substrate in which an oxide film is formed on the surface of one silicon substrate and bonded to another substrate. The SOI substrate formed by such a method and shown in FIG. 18 is composed of a semiconductor substrate 46, an isolation oxide film 48 and a silicon layer 50. Inside the silicon layer 50, a channel forming region 50a, a source region 2 and a drain region are formed. 4 are provided. Note that a glass substrate, a plastic substrate, a sapphire substrate, or the like may be used instead of the semiconductor substrate 46.

The finely divided floating gate 42 is obtained by processing a normal FG type floating gate into fine poly-Si dots having a height of about 5.0 nm and a diameter of up to 8 nm, for example. The tunnel insulating film 10 in the present example is slightly thicker than that of the first embodiment, but is formed to be significantly thinner than the normal FG type, and is appropriately selected within the range of 2.5 nm to 4.0 nm according to the intended use. it can. Here, the thinnest film thickness is 2.5 nm.

In the manufacture of the memory transistor having such a structure, after forming the tunnel insulating film 10 on the SOI substrate, the polysilicon film (final film thickness: 5 nm) is deposited. In this LP-CVD, the source gas is a mixed gas of DCS and ammonia, and the substrate temperature is 650 ° C., for example. Next,
For example, the electron beam exposure method is used to process the polysilicon film into fine poly-Si dots having a diameter of, for example, 8 nm. The poly-Si dots function as the fine division type floating gate 42 (charge storage means). afterwards,
An oxide film 44 is formed by LP-CVD to fill the finely divided floating gate 42 by, for example, about 9 nm. In this LP-CVD, the source gas is DCS.
And a substrate temperature of 700 ° C. At this time, the fine division type floating gate 42 is embedded in the oxide film 44, and the surface of the oxide film 44 is flattened. If the planarization is insufficient, a new planarization process (for example, CMP) may be performed. After that, a gate electrode 8 is formed, and a step of collectively patterning the gate laminated film is performed to complete the fine division FG type memory transistor.

With respect to the fact that the floating gate is finely divided by using the SOI substrate as described above, as a result of evaluating the characteristics by making a device for trial, it was confirmed that the expected good characteristics were obtained. Also, as in the first embodiment, the operation of the one-transistor cell having the fine memory transistor having the gate length of 0.1 μm was confirmed.

[Modification] Various modifications can be made to the first to fourth embodiments described above.

First, as the cell structure, a NOR type of a separated source type in which bit lines and source lines are hierarchized can be adopted. FIG. 19 shows the circuit configuration of this NOR type memory cell array. 20 is a plan view showing an example of the pattern of this NOR type memory cell array, and FIG. 21 is a perspective view seen from the sectional side along the line BB ′ of FIG.

In this non-volatile memory device 110, bit lines are hierarchized into main bit lines and sub bit lines, and source lines are hierarchized into main source lines and sub source lines. The sub-bit line SBL1 is connected to the main bit line MBL1 via the selection transistor S11, and the sub-bit line SBL2 is connected to the main bit line MBL2 via the selection transistor S21. In addition, the main source line MSL (in FIG. 21, MS
L1 and MSL2), the sub-source line SSL1 is connected via the selection transistor S12, and the sub-source line SSL2 is connected via the selection transistor S22.

The memory transistors M11 to M1n are provided between the sub bit line SBL1 and the sub source line SSL1.
Are connected in parallel, and the sub bit line SBL2 and the sub source line SS are connected.
Memory transistors M21 to M2n are connected in parallel with L2. The n memory transistors connected in parallel to each other and the two selection transistors (S1
1 and S12, or S21 and S22) form a unit block forming a memory cell array.

Memory transistors M1 adjacent in the row direction
The gates of 1, M21, ... Are connected to the word line WL1. Similarly, the memory transistors M12, M22,
Each gate of ... Is connected to the word line WL2, and each gate of the memory transistors M1n, M2n, ... Is connected to the word line WLn. The selection transistors S11, S21, ... Adjacent to the row direction are controlled by the selection line SG1, and the selection transistors S12, S22 ,.
It is controlled by G2.

In this fine NOR type cell array 110,
As shown in FIG. 21, a P well 112 is formed on the surface of the semiconductor substrate 111. The P well 112 has a trench filled with an insulator, and is insulated and isolated in the word line direction by an element isolation insulating layer 113 arranged in parallel stripes.

Each P well portion isolated by the element isolation insulating layer 112 becomes an active region of the memory transistor. N-type impurities are introduced at high concentration in parallel stripes spaced apart from each other in the width direction in the active region, whereby the sub-bit line SBL and the sub-source line SSL are formed. The word lines WL are orthogonally arranged on the sub-bit lines SBL and the sub-source lines SSL via an insulating film.
1, WL2, WL3, WL4, ... Are wired at equal intervals. As will be described later, this word line is formed by laminating a gate insulating film including a tunnel insulating film, a nitride film, and a top insulating film, and a gate electrode. In the present embodiment, the gate length (word line width) is miniaturized to 0.13 μm or less, for example, 0.1 μm. Sub bit line SB
P well portion 112a between L and the sub source line SSL
And the intersection with each word line serves as a channel formation region of the memory transistor, the sub-bit line portion in contact with the channel formation region functions as a drain, and the sub-source line portion functions as a source.

Similar to the case of FIG. 3, the upper portion and the side wall of the word line are covered with the offset insulating layer and the sidewall insulating layer (in this example, a normal interlayer insulating layer is also possible). Sub-bit lines SBL are provided at predetermined intervals on these insulating layers.
And a source contact plug SC reaching the sub-source line SSL are formed. These plugs BC and SC are, for example,
About 128 memory transistors are provided in the bit line direction. In addition, the main bit lines MBL1, BL contacting the insulating layer on the bit contact plug BC
, And main source lines MSL1, BL2, ... Contacting on the source contact plugs SC are alternately formed in parallel stripes.

In this fine NOR type cell array 100, bit lines and source lines are hierarchized, and it is not necessary to form the bit contact plug BC and the source contact plug SC for each memory cell. Therefore, there is basically no variation in the contact resistance itself. Bit contact plug BC and source contact plug S
C is provided for every 128 memory cells, for example. If the plug is not formed in a self-aligned manner, the offset insulating layer and the sidewall insulating layer are not necessary. That is, only the usual step of thickly depositing the interlayer insulating film and embedding the memory transistor is sufficient. As described above, this example has an advantage that the process can be further simplified.

Sub wiring (sub bit line, sub source line)
Since there is almost no wasted space as a pseudo contactless structure composed of the impurity regions, when each layer is formed with the minimum line width F of the wafer process limit, it is possible to manufacture with a very small cell area close to 8F ² . Further, the bit line and the source line are hierarchized, and the selection transistor S11
Alternatively, since S21 disconnects the parallel main transistor group in the unselected unit block from the main bit line MBL1 or MBL2, the capacity of the main bit line is significantly reduced,
It is advantageous for high speed and low power consumption. In addition, the sub-source line can be separated from the main source line by the function of the selection transistor S12 or S22 to reduce the capacitance. In order to further increase the speed, the sub bit lines SBL1, S
BL2 or the sub-source lines SSL1 and SSL2 are formed of impurity regions to which silicide is attached, and the main bit line MBL
Metal wirings are preferably used for 1 and MBL2.

A NAND type cell system can also be adopted. In the NAND type, each of the memory transistors M11 to M in the unit block forming the memory cell array of FIG.
1n or M21 to M1n are connected in series instead of in parallel. In this case, there is no distinction between the sub-bit line and the sub-source line, and the sub-bit line and the sub-source line are the channel forming impurity regions of the NAND string. In addition, although not particularly shown, DI
The present invention can be applied to a fine NOR type cell, which is a NOR type, so-called HiCR type, and which is composed of an isolated source type cell array in which a source line is shared by two adjacent source regions.

In the description of the first embodiment, it is premised that the write inhibit voltage supply circuit 92 applies the same reverse bias voltage to both the source region 2 and the drain region 4 of the memory transistor at the same time. In the present invention, the reverse bias voltage is not limited to the same voltage, and the reverse bias voltage may be applied to one of the source region 2 and the drain region 4 and the other may be opened. It is also possible to apply different voltages to the source line and the bit line.

The "charge storage means" includes a carrier trap in the bulk of the nitride film and a carrier trap formed near the interface between the oxide film and the nitride film. The gate insulating film is N
The present invention can be applied even to the MNOS type which is an O (Nitride-Oxide) film.

The present invention can be applied to not only the stand-alone type non-volatile memory but also the embedded type non-volatile memory integrated with the logic circuit on the same substrate.
The use of the SOI substrate as in the fourth embodiment can be applied to the memory transistor structures of the first to third embodiments redundantly.

[0086]

According to the nonvolatile semiconductor memory device of the present invention, the memory transistor that basically operates by storing charges in the charge storage means in the gate insulating film has a structure suitable for miniaturization. It has become possible.

[Brief description of drawings]

FIG. 1 is a source-isolated NOR according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a schematic configuration of a nonvolatile semiconductor memory of the type.

FIG. 2 shows an example of a specific cell arrangement pattern according to the first embodiment of the present invention, in which a fine NO using a self-alignment technique is used.
It is a schematic plan view of an R-type cell array.

FIG. 3 is a perspective view of the cell array of FIG. 2 according to the first exemplary embodiment of the present invention as viewed from a cross section taken along line AA ′.

FIG. 4 is a cross-sectional view showing an element structure of a MONOS type memory transistor according to the first embodiment of the present invention.

FIG. 5 is a diagram showing an example of write bias voltage setting conditions for four types of cells in the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a gate length of 0.
7 is a graph showing a hysteresis characteristic and a write / erase characteristic of a 1 μm MONOS type nonvolatile memory transistor.

FIG. 7 is a graph showing current-voltage characteristics of a memory transistor in an erased state according to the first embodiment of the present invention.

FIG. 8 is a graph showing the gate length dependence of the lower limit value of the source / drain inhibit voltage in the first embodiment of the present invention.

FIG. 9 is a graph showing the voltage dependence of the read current and the leak current obtained from the current-voltage characteristics in the erased state in the first embodiment of the present invention.

FIG. 10 is a graph showing a read disturb characteristic after 100,000 times of data rewriting in the first embodiment of the present invention.

FIG. 11 is a graph showing a data rewriting characteristic in the first embodiment of the present invention.

FIG. 12 shows a gate length of 8 in the second embodiment of the present invention.
It is a graph which shows the current-voltage characteristic of a 5 nm MONOS type memory transistor.

FIG. 13 is a graph showing the voltage dependence of the read current and the leak current in the second embodiment of the present invention.

FIG. 14 is a graph showing read current characteristics of a memory cell in an erased state according to the second embodiment of the present invention.

FIG. 15 shows a gate length of 8 in the second embodiment of the present invention.
7 is a graph showing data rewriting characteristics of a 5 nm MONOS memory transistor.

FIG. 16 is a graph showing read disturb characteristics after 10,000 data rewritings according to the second embodiment of the present invention.

FIG. 17 is a sectional view showing an element structure of a Si nanocrystal type memory transistor according to a third embodiment of the present invention.

FIG. 18 is a cross-sectional view showing an element structure of a fine division FG type memory transistor according to a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a circuit configuration of a NOR type memory cell array as another application example of the memory cell system in the embodiment of the present invention.

20 is a plan view showing a pattern example of the NOR type memory cell array in FIG. 19. FIG.

FIG. 21 is a perspective view seen from the cross-section side along the line BB ′ of FIG. 20.

[Explanation of symbols]

1, 101, 111 ... Semiconductor substrate, 1a, 50a ... Channel formation region, 2, S ... Source region, 4, D ... Drain region, 6, 30, 40 ... Gate insulating film, 8 ... Gate electrode, 10 ... Tunnel insulation Film, 12 ... Nitride film, 14 ... Top insulating film, 32 ... Si nanocrystals, 34, 44 ... Oxide film,
42 ... Fine division type floating gate, 46 ... Semiconductor substrate, 48 ... Isolation oxide film, 50 ... Silicon layer, 90, 1
00, 110 ... Fine NOR type memory cell array, 92 ...
Write inhibit voltage supply circuit, 94 ... Non-selected word line bias circuit, 102, 113 ... Element isolation insulating layer,
112 ... P-well, M11-M22 ... Memory transistor, S11, ST0, etc .... Selection transistor, A-C ... Non-selected cell, S ... Selection cell, BL1 etc .... Bit line, MBL
1 etc .... Main bit line, SBL ... Sub bit line, SL1 etc .... Source line, MSL ... Main source line, SSL1 etc .... Sub source line, WL1 etc .... Word line, BC ... Bit contact plug, SC ... Source contact plug

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F083 EP02 EP17 EP18 EP23 EP42                       EP63 EP76 EP77 EP78 ER03                       ER14 ER21 GA09 GA15 GA16                       GA21 HA02 JA04 JA19 KA06                       KA12 MA06 MA19 MA20 NA01                       NA02 PR01 PR21 PR29                 5F101 BA16 BA45 BA46 BA54 BB05                       BC01 BD07 BD30 BD32 BD33                       BD34 BD35 BD37 BE02 BE05                       BE07 BH02 BH19

Claims (4)

[Claims] 1. A semiconductor substrate of a first conductivity type, a gate insulating film formed on the semiconductor substrate and including charge storage means therein, and a gate electrode formed on the gate insulating film. A second conductivity type source region formed in the surface region of the semiconductor substrate on one side in the width direction of the gate electrode, and a surface region of the semiconductor substrate on the other side in the width direction of the gate electrode. A drain region of the second conductivity type, a source contact plug formed at one end of the source region in a direction orthogonal to the width direction of the gate electrode, and a width of the gate electrode of the drain region. Bit contact formed at the other end in the direction orthogonal to the direction
A nonvolatile semiconductor memory device comprising: a plug; a source line electrically connected to the source contact plug; and a bit line electrically connected to the bit contact plug. 2. A plurality of memory transistors having the gate insulating film, the gate electrode, the source region, and the drain region are arranged in a matrix, and the memory transistors are arranged in a column direction.
The source regions or the drain regions are alternately formed in a column direction in a lower region between the gate electrodes, the source regions are shared by two memory transistors adjacent in the column direction, and the drain regions are formed in the column direction. 2 adjacent to each other
Shared by two memory transistors, the source contact plug is formed at one end in the row direction of the shared source region, and the bit contact plug is formed at the other end in the row direction of the shared drain region. The source line has a line shape that is long in the column direction, commonly connects the plurality of source contact plugs in the column of the memory transistor, and the bit line has a line shape that is long in the column direction. 2. The non-volatile semiconductor memory device according to claim 1, further comprising: a plurality of bit contact plugs in a corresponding column of memory transistors, which are commonly connected. 3. An element isolation insulating layer is formed between columns of the memory transistor, and the source contact plug is formed on the one side of the memory transistor in the row direction and the element isolation insulating layer. The bit contact plug is formed at a position including a boundary with the source region, and the bit contact plug includes a boundary between the drain region and another element isolation insulating layer formed on the other side in the row direction of the column of the memory transistor. The nonvolatile semiconductor memory device according to claim 2, wherein the nonvolatile semiconductor memory device is formed at a position. 4. An offset insulating layer having the same pattern shape as that of the gate electrode is formed on the gate electrode, and the offset insulating layer, the gate electrode, and the gate insulating film have side walls on both sides in the width direction of the stacked body. The wall insulating layer is formed, and the insulating isolation between the source contact plug or the bit contact plug and the gate electrode is achieved by the offset insulating layer and the sidewall insulating layer. Nonvolatile semiconductor memory device.