JP2006236424A - Nonvolatile memory device, and its electron charges injection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize preventing disturbance of a nonvolatile cell to which drain voltage of a selection cell is applied, with a method being suitable for low voltage operation. <P>SOLUTION: The device has an operation circuit 9 for injecting electron injection and a non-selection word line bias circuit 9A as a function of a peripheral circuit. The operation circuit 9 controls operation injecting high energy electron charges to a local part of its lamination insulation film for data writing or erasing of a selected memory transistor to be operated. The non-selection word line bias circuit 9A applies the prescribed voltage to a non-selection memory transistor whose drain region is connected electrically to a drain region of the selected memory transistor through a nonvolatile word line in the direction where voltage between a drain and a gate is relaxed in injecting electron charges. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is a nonvolatile memory device that is formed between a channel formation region and a gate electrode, and injects high energy charges into a local portion of a laminated insulating film including discrete traps therein, and sets or changes a data storage state; It relates to the charge injection method.

The nonvolatile memory device has a so-called FG type in which the charge holding means is made of a single conductive layer, for example, polysilicon, and a semiconductor region (channel forming area) in which the charge holding means (charge trapping means) forms a channel. It can be broadly classified into discrete trap types such as so-called MONOS type, which are discretized in the opposed in-plane and film thickness directions.
In the discrete trap type, there are various data writing methods, but focusing on the fact that charge can be injected into a part of the discrete trap by the CHE injection method, the source of the nitride film as the charge storage film There is known a technique capable of recording 2 bits per memory cell by writing binary data independently on the side and the drain side (see, for example, Non-Patent Document 1).
In this technique, data is written by a so-called “reverse read” method in which 2-bit data is written by CHE injection by switching the voltage application direction between the source and the drain and a predetermined voltage is applied between the source and the drain in the reverse direction to the writing. Is read. For this reason, even when the writing time is short and the amount of accumulated charge is small, 2-bit data can be reliably read. Erasing is performed by hot hole injection using a band-to-band tunnel current.
With this technology, a non-volatile memory with a simple structure and writable by 2 bits can be realized, which can significantly reduce the bit cost.
Boaz Eitan etc, “Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp.522-523”

In particular, in logic-embedded nonvolatile memory used in system LSIs, it is necessary to reduce the operating voltage and reduce power consumption as the power supply voltage is lowered by scaling the peripheral logic circuits. ing.
However, in the known example described in Non-Patent Document 1, since writing is performed by flowing a current through the channel of the memory transistor by the CHE injection method, the voltage Vg applied to the gate at the time of writing is as high as 9 V, and low voltage operation is performed. Has the disadvantage of being difficult.

  Further, the voltage Vd (<Vg) applied to the drain at the time of writing or erasing is relatively high. For this reason, in a plurality of memory transistors in the column direction in which the drains and the sources are connected in the cell array, voltage stress is applied to the non-selected memory transistors other than the operation target memory transistor. Due to this voltage stress, the threshold voltage on the higher side may decrease in the non-selected memory transistor, and this may cause the threshold voltage to deviate from a desired value while rewriting data many times. . This is called “disturb”, and effective anti-disturbance measures are required to realize a highly reliable device.

  The problem to be solved by the present invention relates to a nonvolatile memory having a storage insulating film including discrete carrier-traps such as a so-called MONOS type, in which charge is injected into a local portion of the storage insulating film and data To provide a non-volatile memory device capable of preventing disturbance suitable for low-voltage operation, particularly preventing a memory transistor connected to an unselected word line from being disturbed when setting or changing a memory state, and a charge injection method thereof It is.

A nonvolatile memory device according to the present invention includes a plurality of source / drain regions formed in a semiconductor substrate, and a plurality of layers stacked between a channel formation region between the two source / drain regions and a gate electrode. A plurality of memory transistors made of an insulating film, each of which includes a stacked insulating film capable of holding charges in internal discrete traps, and arranged in a matrix, and a gate electrode common to the plurality of memory transistors arranged in one direction Or a plurality of word lines formed by a conductive layer that electrically connects a plurality of gate electrodes in units of the plurality of memory transistors arranged in one direction, and a memory transistor to be operated is selected, To set or change the data storage state of the selected memory transistor, high energy is applied locally to the stacked insulating film. Charge injection to an operation circuit that injects a load and a non-selected memory transistor whose source / drain region is electrically connected to the source / drain region of the memory transistor to be operated at the time of charge injection by the operation circuit And a non-selected word line bias circuit for applying a predetermined voltage via a non-selected word line in a direction to relax the voltage between the local source / drain region and the gate electrode.
The unselected word line bias circuit preferably has a source / drain region that functions as a drain of the memory transistor to be operated with reference to a potential of the channel formation region or a potential of a source / drain region that functions as a source. The predetermined voltage having the same polarity as the voltage applied to is applied to the unselected word line.

In the present invention, preferably, the number of memory transistors whose sources and drains are connected in common in the plurality of memory transistors arranged in a matrix, and any one of the memory transistors is an operation of another memory transistor. The unselected word is based on a drain voltage range limit value that determines whether or not a difference between two threshold voltages defining the storage state of the one memory transistor changes when a drain voltage stress is applied. One limit value of an appropriate range is defined for the predetermined voltage to be applied to the non-selected word line by the line bias circuit.
More preferably, for the predetermined voltage applied to the non-selected word lines by the non-selected word line bias circuit, the other limit value of the appropriate range is the two threshold voltages defining the storage state. It is specified according to the lower value.
By applying a voltage to the non-selected word line by the non-selected word line bias circuit, the leakage current from the non-selected memory transistor is sufficiently suppressed.

According to the nonvolatile memory device charge injection method of the present invention, two source / drain regions formed in a semiconductor substrate and a channel forming region between the two source / drain regions and a gate electrode are stacked. A plurality of memory transistors, each of which includes a plurality of insulating films, each of which includes a stacked insulating film that holds charges in an internal discrete trap, and is arranged in a matrix and has a gate common to the plurality of memory transistors arranged in one direction A charge injection method for a non-volatile memory having a plurality of word lines formed as conductive electrodes electrically connecting a plurality of gate electrodes in units of the plurality of memory transistors arranged in the one direction. A step of selecting a memory transistor to be operated, and a source / drain region of the memory transistor to be operated The direction of relaxing the voltage between the source / drain region and the gate electrode on the local side of the stacked insulating film for charge injection with respect to a non-selected memory transistor electrically connected to the source / drain region of the transistor Applying a predetermined voltage via a non-selected word line, and setting or changing a data storage state by injecting high energy charges into the local part of the memory transistor to be operated. Including.
In the step of applying the predetermined voltage to the non-selected memory transistor, preferably, the potential of the channel formation region or the potential of the source / drain region functioning as a source is used as a reference. The predetermined voltage having the same polarity as the voltage applied to the source / drain region functioning as the drain is applied to the unselected word line.

In the present invention, preferably, the number of memory transistors whose sources and drains are connected in common in the plurality of memory transistors arranged in a matrix, and any one of the memory transistors is an operation of another memory transistor. When the drain voltage stress is sometimes applied, the difference between the two threshold voltages defining the memory state of the one memory transistor changes, based on the limit value of the drain voltage range that determines whether or not the non-selected One limit value of the appropriate range is defined for the predetermined voltage to be applied to the word line.
More preferably, for the predetermined voltage applied to the non-selected word line, the other limit value of the appropriate range is defined according to the lower value of the two threshold voltages defining the storage state. Has been.
By applying a voltage to the unselected word line, the leakage current from the unselected memory transistor is sufficiently suppressed.

According to the present invention, in a memory transistor in a non-selected row in which the source / drain region is connected in common with the source / drain region of the memory transistor to be operated, for example, the voltage stress in the direction in which the threshold voltage on the high side decreases is reduced. It is mitigated and disturb is effectively prevented. This disturb prevention method specializes the prevention of disturbance for the memory transistors in the non-selected rows in the memory transistor array in which the source and drain regions are commonly connected. For this reason, when a charge injection method having a gate voltage lower than that of CHE charge injection that applies an electric field between the source and the drain to flow a channel current and accelerates the charge traveling through the channel is adopted, a voltage that can be taken to prevent disturbance. The range can be made relatively wide, and more effective disturbance prevention can be achieved.
As described above, according to the present invention, it is possible to realize a device that injects charges into the local area of the charge retention layer by a low voltage operation while effectively preventing disturbance, that is, a low voltage, low bit cost, and highly reliable nonvolatile memory device.

  Embodiments of the present invention will be described below with reference to the drawings, taking as an example the case of having an N-channel type memory transistor. In the case of having a P-channel memory transistor, the following explanation can be applied by analogy by operating with the conductivity type of the impurity region reversed and inverting the polarity of several applied voltages.

FIG. 1 shows a schematic configuration of a nonvolatile memory device.
The nonvolatile memory device illustrated in FIG. 1 includes a memory cell array (MCA) 1 having memory transistors arranged in a matrix and a memory peripheral circuit that controls the operation of the memory cell array 1.
The memory peripheral circuit includes a column buffer 2a, a row buffer 2b, a pre-row decoder (PR.DEC) 3, a main row decoder (MR.DEC) 4, a column decoder (C.DEC) 5, and an input / output circuit (I / O). 6, a column selection gate array (C.SEL) 7, and a well charge / discharge circuit (WC / DC) 8. When no well bias is performed, the well charge / discharge circuit 8 can be omitted. Although not specifically illustrated, the memory peripheral circuit slightly increases the power supply voltage as necessary, and supplies the boosted voltage to the main row decoder 4 or the well charge / discharge circuit 8, and these A control circuit for controlling each unit is included.

In the present embodiment, the power supply voltage supplied from the memory peripheral circuit to the memory cell array 1 is a single power supply voltage, and the maximum value of the voltage applied to the memory cell is 6 V or less, more preferably 5 V or less. It has become.
Therefore, the transistor of the memory peripheral circuit has a withstand voltage of about 5 to 6 V, which is about the same as the withstand voltage of a normal logic circuit, for example, an input / output stage transistor. That is, when the configuration shown in FIG. 1 is embedded in the same integrated circuit as the logic circuit, the commonality of the process can be made extremely high because the high breakdown voltage transistor is not included.
Since the basic operation of each part of the memory peripheral circuit is the same as that of a normal nonvolatile memory device, description thereof is omitted here.

FIG. 2 shows a cross-sectional view of a MONOS type memory transistor.
In the memory transistor 10 shown in FIG. 2, a part of a semiconductor substrate or well made of a P-type semiconductor is a semiconductor region in which a channel is formed, that is, an active region 11A. Here, the active region 11A is formed in a part of a P-type semiconductor substrate, a P-type well formed in the semiconductor substrate through another well as necessary, or a substrate (material other than a semiconductor is also possible). There are supported P-type semiconductor layers (for example, SOI (Silicon-On-Insulator) layers). Hereinafter, the semiconductor substrate 11 and the active region 11A include, in addition to a silicon wafer, wells or SOI layers formed in the substrate and a partial region thereof.

  A laminated insulating film 12 including a first oxide film 12A, a nitride film 12B as a charge retention layer, and a second oxide film 12C is formed on the surface of the active region 11A, and a gate electrode 13 is formed thereon. . In general, the first oxide film 12A is referred to as a bottom oxide film, and the second oxide film 12C is referred to as a top oxide film.

The nitride film 12B is made of a material having a charge trap density higher than that of the first and second oxide films 12A and 12C, and functions as a charge holding layer during charge injection. The nitride film 12B in this example is formed of, for example, an 8.0 nm silicon nitride (Si _x N _y (0 <x <1, 0 <y <1)) film. The nitride film 12B is produced, for example, by low pressure CVD (LP-CVD), and contains many carrier traps. The nitride film 12B exhibits a Pool Frenkel type (PF type) electric conduction characteristic. Strictly speaking, charges may be trapped in the first and second oxide films 12A and 12C, but since the absolute amount thereof is extremely smaller than that of the nitride film 12B, the nitride film 12B is referred to as a charge holding layer. Yes.

The first and second oxide films 12A and 12C serve to electrically isolate the nitride film 12B from the active region 11A or the gate electrode 13 and confine charges in the nitride film 12B for charge retention. The first and second oxide films 12A and 12C can be replaced with other films such as an oxynitride film if they have a sufficient charge trap density difference with respect to the nitride film 12B and function as a potential barrier. .
As the first oxide film 12A in this example, for example, a silicon oxide film is formed and subjected to nitriding treatment. The film thickness of the first oxide film 12A can be determined within the range of 2.0 nm to 10.0 nm according to the intended use, and is set to 7 nm here.
The second oxide film 12C needs to be formed with high density of deep carrier traps in the vicinity of the interface with the nitride film 12B. For this reason, in this example, the formed nitride film is formed by thermal oxidation. The second oxide film 12C may be a SiO ₂ film formed by HTO (High Temperature chemical vapor deposited Oxide) method. When the second oxide film 12C is formed by CVD, this trap is formed by heat treatment. The thickness of the second oxide film 12C is at least 3.5 nm, preferably 5 nm, in order to effectively prevent the hole injection from the gate electrode (word line WL) and prevent the number of times data can be rewritten. The above is necessary.

Two N-type LDD (lightly doped drain) regions 14S and 14D that partially overlap the gate electrode 13 are formed apart from each other in the active region 11A. Further, a pocket region 15 made of a P-type impurity region is formed so as to protrude from the vicinity of the end of the LLD region 14D on the drain side to the source side. The pocket region 15 is formed by implanting P-type impurities by oblique ion implantation or the like. The ion implantation dose at this time is optimized, and finally the P-type impurity concentration in the pocket region 15 is adjusted to be as high as necessary than the P-type impurity concentration in the active region 11A. If such a pocket region 15 is present, the P-type impurity concentration locally increases at the end of the LDD region 14D on the drain side, so that when the operating voltage is applied, the depletion layer can be prevented from growing at that portion. As a result, the concentration of the lateral electric field is increased.
Since this contributes to the improvement of the charge injection efficiency, the formation of the pocket region 15 is desirable. However, in the present invention, the provision of the pocket region 15 is not an essential requirement, and can be omitted. Note that one of the features of the MONOS transistor having an operating voltage of 5 to 6 V or less as in this embodiment is that the concentration of the pocket region 16 is higher than that of the conventional channel hot electron (CHE) injection type MONOS transistor. ing.

  Spacers (sidewall spacers) 16S and 16D made of an insulator are formed on both side walls of the gate electrode 13. A source region 17S made of an N-type impurity region is formed on the surface side portion of the active region 11A whose position is defined by the sidewall spacer 16S. Similarly, the active region 11A whose position is defined by the sidewall spacer 16D is formed. A drain region 17D made of an N-type impurity region is formed in the surface side portion of the semiconductor layer.

  The source region 17S and the drain region 17D are formed by ion implantation of N-type impurities at a relatively high concentration. At this time, the side wall spacers 16S and 16D and the gate electrode 13 function as a self-alignment mask, and the positions of the source region 17S and the drain region 17D are determined. The LDD regions 14S and 14D are formed by ion-implanting N-type impurities before the sidewall spacers 16S and 16D are formed, and their concentrations are usually set lower than those of the source region 17S and the drain region 17D. . Further, each pattern of the LDD regions 14S and 14D overlaps with a pattern end of the gate electrode 13, respectively. This is because when holes are injected, the electric field of the gate easily reaches the drain, and holes can be generated at a low drain voltage.

  In order to make the electric field of the gate easily reach the drain, the LDD region 14D only needs to protrude from the drain region 17D directly below the end of the gate electrode. In this sense, the “extension region” that does not suggest a concentration relationship May be called. In this case, the N-type impurity concentration in the extension region is not necessarily lower than the N-type impurity concentration in the drain region 17D.

  Each of the source region 17S, the drain region 17D, the gate electrode 13 and the active region 11A is supplied with voltages Vs (source voltage), Vd (drain voltage), Vd (drain voltage), suitable for respective operations, via a contact portion and a wiring not shown. Vg (gate voltage) and, if necessary, Vb (back bias voltage) can be applied.

A large number of memory transistors 10 having such a structure are arranged in a matrix to constitute a memory cell array (MCA) 1 (see FIG. 1) of the nonvolatile memory device.
Hereinafter, a structural example of the memory cell array will be described with reference to the drawings.

FIG. 3 is an equivalent circuit diagram of a NOR type memory cell array. FIG. 4 is a schematic plan view of a fine NOR type cell array that can be formed using the self-alignment technique. FIG. 5 is a perspective view seen from the cross-sectional side along the line AA ′ in FIG. 4.
In the nonvolatile memory device of this example, each memory cell of the NOR type memory cell array is composed of one memory transistor. As shown in FIG. 3, memory transistors M11 to M33, each constituting a memory cell, are arranged in a matrix, and these transistors include word lines WL1 to WL3, bit lines BL1 to BL3, and separated source lines SL1 to SL1. Connected by SL3.

Each source of the memory transistors M11, M12, and M13 arranged along the column (COLUMN) direction is connected to the bit line BL1, and each drain is connected to the source line SL1. Each source of the memory transistors M21, M22, and M23 arranged along the column direction is connected to the bit line BL2, and each drain is connected to the source line SL2. Each source of the memory transistors M31, M32, and M33 arranged along the column direction is connected to the bit line BL3, and each drain is connected to the source line SL3.
The gates of the memory transistors M11, M21, and M31 arranged along the row (ROW) direction are connected to the word line WL1. Each gate of the memory transistors M12, M22 and M32 arranged along the row direction is connected to the word line WL2. Each gate of the memory transistors M13, M23 and M33 arranged along the row direction is connected to the word line WL3.
In the entire memory cell array, the cell arrangement and inter-cell connection illustrated in FIG. 2 are repeated.

  In the fine NOR type cell array, as shown in FIG. 5, an element isolation insulating layer ISO made of an insulating trench or LOCOS is formed in a surface region of a P type semiconductor substrate 11 (or P well). As shown in FIG. 4, the element isolation insulating layer ISO has a parallel line shape that is long in the column (COLUMN) direction. Word lines WL1, WL2, WL3, WL4 are formed at equal intervals, and each word line is substantially orthogonal to the element isolation insulating layer ISO.

As shown in FIG. 5, the stacked insulating film 12 of the memory transistor described above is formed between the word lines WL1 to WL4 and the active region 11A (see FIG. 2) of the semiconductor substrate 11.
In FIG. 5, the LDD regions 14S and 14D formed in the active region 11 and the pocket region 15 are not shown in FIG. 4 and FIG. 5 correspond to the gate electrode 13 shown in FIG. In this example, the width (gate length) of the word lines WL1 to WL4 is reduced to 0.18 μm or less, for example, 0.13 μm.

  As shown in FIG. 4 and FIG. 5, the source region 17S and the drain region 17D are arranged in a column (at the surface portion of the active region where the region is defined by the element isolation insulating layer ISO). It is formed alternately along the (COLUMN) direction. The dimension in the row (ROW) direction of the source region 17S and the drain region 17D is defined by the distance between the element isolation insulating layers ISO. The dimension in the column direction of the source region 17S and the drain region 17D is defined by the interval between the word lines WL1 to WL4. The source region 17S and the drain region 17D are formed to be extremely uniform because almost no mask alignment error is introduced with respect to variations in dimensions and arrangement.

In FIG. 5, the upper and side walls of the word lines WL1 to WL4 are covered with an insulating layer. Over the word lines WL1, WL2,..., An offset insulating layer OF having the same pattern as the word lines is formed.
Sidewall spacers 16 </ b> S and 16 </ b> D are formed on both side walls of the laminated pattern composed of the offset insulating layer OF, the gate electrode (word line) thereunder, and the laminated insulating film 12.

Between the two adjacent word lines, an elongated self-aligned contact portion SAC is opened along the word line. In the self-aligned contact portion SAC, the word line is covered with the offset insulating layer OF and the sidewall spacers 16S and 16D.
Conductive materials are alternately buried in the self-aligned contact portions SAC so as to partially overlap the source region 17S or the drain region 17D, thereby forming the bit contact plug BC and the source contact plug SC. The bit contact plug BC overlaps one end portion in the row (ROW) direction with respect to the source region 17S. The source contact plug SC overlaps the other end portion in the row direction with respect to the drain region 17D. As a result, the bit contact plug BC and the source contact plug SC are alternately formed as shown in FIG.
A recess around the contact plug is filled with an insulating film (not shown). Bit lines BL1, BL2,... Contacting the bit contact plug BC and source lines SL1, DL2,... Contacting the source contact plug SC are alternately formed on the insulating film. The bit line and the source line have a parallel line shape that is long in the column (COLUMN) direction.

Next, a method for manufacturing this fine NOR cell array will be described.
First, after forming the element isolation insulating layer ISO and P well on the prepared semiconductor substrate 11, the source region 17S and the drain region 17D are formed by ion implantation. Further, ion implantation for adjusting the threshold voltage is performed as necessary.

Next, a laminated insulating film 12 is formed on the semiconductor substrate (or P well) 11.
Specifically, for example, a silicon oxide film (first oxide film 12A) is formed by a high temperature thermal oxidation method.
Next, a silicon nitride film (nitride film 12B) is deposited on the first oxide film 12A by LP-CVD so as to have a final film thickness of 8 nm. This CVD is performed at a substrate temperature of 730 ° C. using a gas in which dichlorosilane (DCS) and ammonia are mixed, for example.
The surface of the formed silicon nitride film (nitride film 12B) is oxidized by a thermal oxidation method to form, for example, a 5 nm silicon oxide film (second oxide film 12C). At this time, for example, the inside of the furnace in the H ₂ O atmosphere is maintained at a temperature of 950 ° C., and thermal oxidation is performed in the furnace for about 40 minutes. As a result, deep carrier traps having a trap level (energy difference from the conduction band of the nitride film 12B) of 2.0 eV or less are formed at a density of about 1 to 2 × 10 ¹³ / cm ² . Further, a thermal silicon oxide film (second oxide film 12C) is formed to a thickness of 1.5 nm with respect to 1 nm of the nitride film 12B, and the underlying nitride film thickness decreases at this ratio, and the final film thickness of the nitride film 12B becomes 8 nm. .

A laminated film of a conductive film to be the gate electrode 13 (word line WL) and the offset insulating layer OF is laminated, and the laminated film is processed in the same pattern all together.
Subsequently, the DLDD regions 14S and 14D and the pocket region 15 are sequentially formed by an ion implantation method, and annealing is performed to activate the impurities.

  An insulating film is formed and the entire surface is etched (etched back). Thus, sidewall spacers 16S and 16D are formed on both sides of the word line WL and the offset insulating layer OF in the width direction. A self-aligned contact portion SAC that exposes the substrate surface is formed between the word lines. In this self-aligned contact portion SAC, the covering with the insulating film around the word line is achieved by the offset insulating layer OF and the side wall spacers 16S and 16D. Therefore, the exposed surface of the source region 17S or the drain region 17D There is an advantage that the area is uniform.

  The self-aligned contact portion SAC is filled with a conductive layer and separated at a predetermined interval. As a result, the source contact plug SC is formed on the source region 17S exposed by the self-aligned contact portion SAC, and at the same time, the bit contact plug BC is formed on the drain region 17D.

  Thereafter, the periphery of these plugs is filled with an interlayer insulating film, the bit line BL and the source line SL are formed on the interlayer insulating film, and then the upper layer wiring and the overcoat film formation through the interlayer insulating layer are performed as necessary. The nonvolatile memory cell array is completed through a pad opening process and the like.

As described above, in the fine NOR type cell array of this example, the contact formation with respect to the bit line BL or the source line SL is achieved by the formation of the self-aligned contact portion SAC and the simultaneous formation of the bit contact plug BC and the source contact plug SC. Is done.
At this time, the size of the contact surface of each plug in the column (COLUMN) direction is determined by the width of the self-aligned contact portion SAC, and the variation in the contact area is small. In addition, the bit contact plug BC or the source contact plug SC can be easily isolated from the word line. Further, the bit contact plug BC and the source contact plug SC, and the bit line and the source line are formed by patterning conductive layers in the same level.
For this reason, the wiring structure is very simple, the number of processes is small, and the structure is advantageous for keeping the manufacturing cost low.

  In addition, each memory transistor has a structure in which the bit contact plug BC and the source contact plug SC are directly connected to the bit line or the separated source line, respectively, so that the parasitic resistance is small and the read current is reduced. It can be enlarged and high-speed reading is possible.

  Next, the operation of the nonvolatile memory will be described.

  In the memory transistor 10 shown in FIG. 2, the nitride film 12B as the charge retention layer has a particularly high charge trap density near the interface with the second oxide film 12C. The threshold voltage of the memory transistor 10 is in a state where electrons are injected and trapped in the charge trap near the interface or in the bulk trap of the nitride film 12B and in a state where the trapped electrons are erased. Change. Therefore, data can be stored in the memory transistor 10 by making the change in the threshold voltage correspond to the binary state of the data.

  However, if a relative change in threshold voltage can be detected, binary or multi-valued stored data can be read. In the present invention, what state is a writing state and what state is an erasing state is a definitional problem. Therefore, in writing or erasing, it is optional to inject electrons or holes. Further, in writing or erasing, it is optional to extract the retained charge or inject a charge having a polarity opposite to the retained charge.

In the present invention, the charge injection method is also arbitrary.
In the present embodiment, data writing is performed by locally injecting high-energy electrons. In particular, this is a kind of hot electron (HE) injection method, which is a drain by impact ionization generated at a relatively low voltage. A method using an avalanche phenomenon is illustrated.
As another high energy charge injection method, a channel hot electron (CHE) injection method, another HE injection method, or a method using a band-to-band tunneling phenomenon can be adopted. is there.
In the erasing method in this embodiment, data is erased by injecting hot holes (HH) using a tunneling phenomenon between bands and electrically canceling part or all of retained electrons. Illustrate.
As another erasing method, a method of extracting charges by FN tunneling can be employed.

The charge injection method according to the present embodiment uses a plurality of memory transistors arranged in the column direction as a unit, and a non-selected word line connected to the non-selected memory transistors is connected between the gate and the drain. It is characterized in that the disturbance is prevented by applying a voltage in a direction that relaxes the voltage.
More specifically, the source / drain region functioning as the drain of the memory transistor to be operated with reference to the potential of the channel formation region (active region 11A) or the potential of the source / drain region 17S functioning as the source at this time. A voltage having the same polarity as the voltage applied to 17D may be applied to the unselected word line.

Preferably, one limit value (minimum value in this example) of the optimum range of the voltage applied to the unselected word line is the difference between the two threshold voltages (window width) that defines the storage state of the memory transistor. , Based on the limit value of the drain voltage range that determines whether or not to change according to the drain disturb characteristic of the memory transistor. Here, the “drain disturb characteristic” means that any one memory transistor in a column of memory transistors in which the sources and drains are commonly connected in a plurality of memory transistors arranged in a matrix in the memory cell array. This is a disturb characteristic when drain voltage stress is applied during the operation of other memory transistors.
More preferably, in the optimum range of the voltage, the other limit value (maximum value in this example) does not turn on the memory transistor according to the lower value of the two threshold voltages defining the storage state. It is prescribed on condition that.

FIG. 6 is a block diagram obtained by functionally rewriting the block diagram shown in FIG.
As shown in FIG. 6, the nonvolatile memory device of the present embodiment is roughly divided into a memory cell array (MCA) 1 and its peripheral circuit (PER.C) 9. As already described, the peripheral circuit 9 is a circuit other than the memory cell array 1 including the various decoders, buffers, selection circuits, I / O circuits, and the like shown in FIG. 1, and functions as an example of the “operation circuit” of the present invention. To do.

The peripheral circuit (operation circuit) 9 includes a non-selected word line bias circuit (BIAS) 9A and a read operation circuit (READ) 9B.
In the narrow sense, the “operation circuit” may be a charge injection operation, that is, a function of a circuit that selects a memory transistor and injects a charge into the selected memory transistor. In that case, the unselected word line bias circuit (BIAS) 9A and the read operation circuit (READ) 9B are provided separately from the operation circuit. However, in a normal memory peripheral circuit, a configuration for generating and supplying a bias is often unified or divided into a row direction and a column direction. Therefore, in FIG. It is included in the circuit.
Of these, the unselected word line bias circuit 9A is newly added in the present embodiment.

Hereinafter, an example of a charge injection method based on such a configuration will be described with reference to the drawings.
FIG. 7 is an equivalent circuit diagram of a part of the memory cell array showing the relationship between the voltage value during the write operation and the application target.

The write operation according to the present invention includes a first step of selecting a cell, a second step of setting an inhibit voltage, and a third step of actually performing a write operation.
In the first step, in the memory cell array shown in FIG. 7, the operation circuit 9 shown in FIG. 6 selects the memory transistor M21 to be written.
In the second step, a non-selected word line bias circuit 9A shown in FIG. 6 applies a predetermined in-bit voltage Vinh to non-selected word lines WL2 and WL3 other than the word line WL1 to which the selected memory transistor M21 is connected. To do.
In the third step, the operation circuit shown in FIG. 6 applies a predetermined write voltage Vgw to the selected word line WL1, and a predetermined write drain voltage is applied to the source / drain region (drain region 17D) functioning as its drain. Vdw is applied.

Hereinafter, this write operation will be described in more detail with reference to the specific applied voltage values shown in FIG. 8 and the voltage application timings shown in the timing charts of FIGS. 9A to 9E.
Here, since the drain avalanche mode is used, if the gate voltage at the time of writing is expressed as Vgw, the drain voltage is expressed as Vdw, and the lower threshold voltage among the two threshold voltages defining the data storage state is expressed as Vthl, Of the plurality of voltages supplied from the circuit to the memory transistor, it is desirable that the maximum voltage is 6 V or less, and any relationship of Vg ≦ Vd and Vg−Vthl ≦ Vd is satisfied. The “drain avalanche mode” is an operation mode in which an injection mode by a drain avalanche phenomenon by impact ionization is dominant rather than an injection mode by channel hot electrons (CHE). This is likely to occur under the above voltage relationship.

In this example, the write gate voltage Vgw is 5V and the write drain voltage Vdw is 5V or 4.5V so that the operation with a single power supply is possible. Hereinafter, a case where the write drain voltage is 5 V will be described.
At this time, 0 V is applied to the source line SL2 to which the selected memory transistor M21 (see FIG. 7) is connected. Similarly, 0 V is applied to the non-selected source lines SL1 and SL3 and the non-selected bit lines BL1 and BL3, or they are left open.

Regarding the application timing of these voltages, at time t1 shown in FIGS. 9A and 9B, first, the selected word line WL1 and the unselected word lines WL1 and WL3 are charged up to the inhibit voltage Vinh. .
Next, at time t2 shown in FIG. 9A, only the selected word line WL1 is boosted to the write gate voltage Vgw (= 5 V).
Thereafter, at time t3 shown in FIG. 9E, the potential of the bit line BL2 connected to the drain of the memory transistor M21 to be written is boosted to the write drain voltage Vdw (= 5 V), and then at time t4. The application of the write drain voltage Vdw is terminated.
During this write operation period, as shown in FIGS. 9C and 9D, the selected source line SL2, the unselected source lines SL1 and SL3, and the unselected bit lines BL1 and BL3 are held at 0V. To do.

2 and 3, by applying this bias voltage, in the memory transistor M21, a drain avalanche is formed mainly on the drain region 17D side by an electric field between the drain region 17D and the gate electrode 13 (word line WL1). Among the charges generated by the phenomenon, high-energy charges (electrons) having a polarity opposite to the gate voltage overcome the energy barrier of the first oxide film 12A and are injected into the drain side local portion of the nitride film 12B. Retained.
In the case of injecting electrons into the opposite source side local part, the write operation is executed again by switching the voltage relationship between the above and the source and drain. Alternatively, if the drain voltage Vdw is applied to the source region 17S at the same time as the write operation of the drain side local area according to the write data, 2-bit data can be simultaneously written.

  At this time, referring to FIG. 7, a voltage stress is applied to the non-selected memory transistors M22 and M23 in the same column as the memory transistor M21 so that weak writing is performed, but this is alleviated by the above-mentioned non-selected word line bias. (Disturbance prevention). There is an optimum range for the inhibit voltage Vinh effective for preventing the disturbance.

In the above write operation, as shown in FIG. 9E, the write time tp is determined by the application time of the write drain voltage Vdw defined by the time t3 and the time t4.
Although the method of defining the writing time is not essential, if the writing time tp is defined by the application time of the drain voltage as shown in FIG. 9E, unselected memory transistors to which the same drain voltage is supplied are disturbed. This is desirable because the time taken (hereinafter referred to as disturb time) is minimized.

The present inventor conducted an experiment for determining the optimum range of the inhibit voltage Vinh in devising the present invention.
The results of this experiment are shown below.

FIG. 10 is a graph showing the time transition of the threshold voltage Vth when the drain voltage Vdw is applied to the MONOS memory transistor in the written state where the threshold voltage Vth is around 6V.
In this experiment, six samples were prepared in which the drain voltage Vdw at the time of writing was changed in a 0.2 V step from 4.2 V to 5.2 V, and the same test was performed.

  As shown in FIG. 10, the initial threshold voltage Vth varies somewhat in the vicinity of about 6V. However, when the drain voltage stress application time is increased, the amount of decrease ΔVth with respect to the time of the threshold voltage Vth increases as the drain voltage Vdw increases. Was found to increase. This is because stored electrons in the written state are drawn out to the drain side, or hot holes are formed on the drain junction surface and injected into the nitride film 12B, which is the charge retention layer, and recombine with the electrons.

As a result of this experiment, when the write drain voltage Vdw increases, the Vth of the non-selected cell in the write state (Vth = about 6 V) in which the same voltage is applied to the drain decreases with time. It can be seen that disturbance occurs during writing.
In addition, it can be seen that the decrease amount ΔVth of the threshold voltage increases as the write drain voltage Vdw increases.

  In the present invention, from this viewpoint, it is desirable to define the appropriate range of the inhibit voltage Vinh applied to the unselected word lines as follows.

FIG. 11 shows the dependence of the threshold voltage decrease amount ΔVth on the write drain voltage Vdw when the disturb time td in the memory transistor in the write state is 1 second.
The disturb time td referred to here is the total of the time during which one memory transistor is disturbed (= (unit write time tp): see FIG. 9E) until data is written to the entire memory cell array. This disturb time is large in proportion to the size of the memory cell array, and increases particularly in proportion to the number of word lines.
The disturb time of 1 second assumed in FIG. 11 is a realistic value that can realize a cell array scale of 100 word lines or more when the write time tp for one memory transistor is several ms.

As shown in FIG. 11, it can be seen that the threshold voltage decrease amount ΔVth monotonously increases as the write drain voltage Vdw increases.
Further, when the write drain voltage Vdw is 4.2 V or less, there is almost no decrease in the threshold voltage in the write state.

Based on the above knowledge, in this example, in order to make the disturb voltage applied between the drain and gate of the non-selected memory transistor 4.2 V or less, the disturb voltage is relaxed on the non-selected word line (absolute value). The inhibit voltage Vinh is applied in the direction that is decreased by. The inhibit voltage Vinh in this example is a positive voltage having a value lower than this because the write drain voltage Vdw is 5V.
In the above example where the lower limit of the disturb voltage is 4.2V, when the operating voltage is Vgw = Vdw = 5V, the inhibit voltage Vinh applied to the unselected word line is 0.8V or more.
When the drain voltage Vdw is 6V, if an inhibit voltage Vinh of 1.8V or higher is applied to the unselected word line, 4.2V is effectively applied between the drain and the gate.
Thus, the lower limit value of the inhibit voltage Vinh is defined according to the write drain voltage Vdw.

  On the other hand, the upper limit value of the inhibit voltage Vinh is to maintain a state in which the memory transistor in the erased state is not turned on. For example, if the distribution lower limit value of the threshold voltage Vth in the erased state is 2.4 V, then, as a voltage margin, for example, 2 V lower by 0.4 V is used as the upper limit value of the inhibit voltage Vinh to be applied to the unselected word line. Can be set.

From the above, when Vgw = Vdw = 5V as the operating voltage, the appropriate range of the inhibit voltage Vinh in this example is 0.8V or more and 2V or less.
Note that when the drain voltage Vdw is 6V, the appropriate range of the inhibit voltage Vinh is narrower to 1.8V or more and 2V or less. Therefore, in this sense as well, it is desirable to satisfy the above-described voltage relationship: Vg ≦ Vd.

Up to this point, the data writing method has been described. However, reading can be performed by either a so-called forward read method or a reverse read method.
As for the erasing method, inter-band hot hole current erasing or tunnel electron drawing erasing can be used.

FIG. 12 is an equivalent circuit diagram of a part of the memory cell array showing the relationship between the voltage value during the erase operation and the application target. FIGS. 13A to 13D are timing charts showing voltage application timings during the erase operation.
Here, a case where the three memory transistors M11, M21 and M31 connected to the word line WL1 are erased at once is illustrated. Further, a method of injecting hot holes (HH) generated due to the band-to-band tunnel current into the drain side and source side local regions where electrons have been injected will be exemplified.

As shown in FIG. 12, the erase gate voltage (negative voltage: -Vge) is applied to the selected word line WL, the inhibit voltage Vinh (e) is applied to the unselected word lines WL2 and WL3, An erase drain voltage Vde (positive voltage) is applied to the bit line and all source lines.
Thus, in the hot hole injection mode using the band-to-band tunnel current, it is necessary to set the voltage between the gate and the drain close to 10 V (11 V in this example).
When erasing byte by byte, even if the memory transistor is connected to the selected word line WL, the source line and bit line of the memory transistor corresponding to the byte not to be erased are applied with 0V. Open.

Regarding the application timing of these voltages, at a time t1 shown in FIG. 13B, first, the unselected word lines WL2 and WL3 are charged to the inhibit voltage Vinh (e).
Next, at the time t2 shown in FIG. 13A, the erase gate voltage −Vge (= −5V) is applied to the selected word line WL1.
After that, at time t3 shown in FIGS. 13C and 13D, the potentials of all the bit lines BL1 to BL3 and all the source lines SL1 to SL3 of the memory transistor corresponding to the byte to be erased are erased. The voltage is boosted to the voltage Vde (= 6V), and then the application of the erase drain voltage Vde is finished at time t4.

  Referring to FIGS. 2 and 3, by this bias voltage application, in the memory transistors M11 to M31, a minority carrier (hole) accumulation layer is formed on the surface of the source region 17S and the drain region 17D, and an energy band is formed in that portion. As a result, a band-to-band tunneling current is generated. Of the pair of electrons and holes generated thereby, the holes are attracted to the gate electrode 13 and accelerated to become high energy charges (hot holes), which are injected into the laminated insulating film 12. For this reason, retained electrons are electrically offset by the hot holes, and data is erased.

In the above erase operation, as shown in FIG. 13C, the erase time te is determined by the application time of the erase drain voltage Vde defined by the time t3 and the time t4.
This method of defining the erase time is not essential, but if the erase time te is defined by the application time of the drain voltage as shown in FIG. 13C, non-selected memory transistors to which the same drain voltage is supplied are disturbed. This is desirable because the time it takes (erase disturb time) is minimized.
In order to prevent erase disturb, the erase inhibit voltage Vinh (e) applied to the unselected word lines WL2 and WL3 also has an optimum range. Since the derivation can be performed in the same manner as the above-described inhibit voltage Vinh at the time of writing, a description thereof is omitted here.

  According to the present embodiment, it is possible to effectively and easily realize the prevention of disturbance of a non-selected memory transistor suitable for a charge injection mode at a low voltage such as drain avalanche charge injection.

The memory transistor to which the present invention is applicable is not limited to the MONOS memory transistor capable of storing 1 bit / cell shown in FIG. The present invention can also be applied to a MONOS memory transistor capable of storing 2 bits / cell.
2 is not limited to the ONO (Oxide-Nitride-Oxide) film, and the structure of the nitride film bulk trap such as the NO (Nitride-Oxide) film is mainly discretized. When used as a trap, it is further divided into fine dots that are made of silicon or the like and made of nanocrystals, polysilicon, etc. that are insulated from each other with a particle size of the order of 10 nanometers (nm) or less. It may have other types of discretization traps such as a split floating gate.
Further, the memory cell array configuration is not limited to the one having the isolation source shown in FIG. 3, and can be widely applied to various cell type nonvolatile memories such as other NOR type and NAND type, for example. Other NOR types include cell configurations in which bit lines or source lines are hierarchized, for example, AND type, DINOR type, and the like.

  It does not matter whether a non-volatile memory is mixed with a logic circuit that realizes a function by utilizing the memory function. Moreover, the kind of function, the use to be used, and an application are not ask | required.

In general, general-purpose nonvolatile semiconductor memory devices that are currently mainstream often guarantee 100,000 rewrites. However, since the nonvolatile semiconductor memory device has been widely used as a recording medium for all rewritable data, the number of times of rewriting increases from several times to several tens times as long as it is limited to an appropriate application. Yes.
For example, the number of rewrites may be limited to protect the interests of the copyright holder. Alternatively, in the field of system LSIs, etc., some functions are electrically selected according to the customer's request, or a predetermined characteristic value (for example, supply voltage value) is changed according to the customer's request. Therefore, there is a case where a nonvolatile memory cell array capable of electrically rewriting data is embedded in a part of the IC. In these applications, the number of input data bits M or the maximum number of rewrites N is often determined in advance.

For example, applicable applications include analog trimming applications where the resistance is adjusted to change the supply voltage value. In such applications, it has been found that a maximum number of data rewrites of about 10 is sufficient. This logic embedded memory device has a memory block and a logic circuit block for setting a resistance value.
Even in such analog trimming applications and other applications, the above-described advantage can be obtained that the disturbance prevention of the non-selected memory transistor suitable for the charge injection mode at a low voltage is effective and can be easily realized.

It is a block diagram which shows schematic structure of the non-volatile memory device in this Embodiment. It is sectional drawing of a MONOS type | mold memory transistor. 2 is an equivalent circuit diagram of a NOR type memory cell array. FIG. It is a schematic plan view of a fine NOR type cell array that can be formed using a self-alignment technique. It is the perspective view seen from the cross section side along the AA 'line of FIG. It is the functional block diagram which functionally rewrote the block diagram shown in FIG. FIG. 4 is an equivalent circuit diagram of a part of a memory cell array showing a relationship between a voltage value during a write operation and an application target thereof. It is a graph which shows a specific applied voltage value. (A)-(E) is a timing chart which shows the voltage application timing at the time of write-in operation | movement. It is a graph which shows the time transition of the threshold voltage in the writing state, when the accelerated life test by high temperature holding | maintenance is performed with respect to the MONOS memory transistor. It is a graph which shows the write drain voltage dependence of the decrease amount of a threshold voltage when the disturb time in the memory transistor in a write state is 1 second. FIG. 5 is an equivalent circuit diagram of a part of a memory cell array showing a relationship between a voltage value during an erasing operation and an application target thereof. (A)-(D) is a timing chart which shows the voltage application timing at the time of erase operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 9 ... Operation circuit, 9A ... Unselected word line bias circuit, 9B ... Read operation circuit, 10 ... Memory transistor, 11 ... Semiconductor substrate or well, 11A ... Active region, 12 ... Multilayer insulation film, 12B ... First oxide film, 12C ... second oxide film, 13 ... gate electrode, 17S ... source region, 17D ... drain region, OF ... offset insulating layer, SW ... side wall spacer, BL1, etc. bit line, M11, etc. ... Memory transistor, SL1, etc .... Source line, WL1, etc .... Word line

Claims (16)

It consists of two source / drain regions formed on the semiconductor substrate and a plurality of insulating films stacked between the channel forming region and the gate electrode between the two source / drain regions, and serves as an internal discrete trap. A plurality of memory transistors each including a stacked insulating film capable of holding charge, and arranged in a matrix;
A plurality of memory transistors arranged in one direction as a common gate electrode, or a plurality of conductive layers electrically connecting the plurality of gate electrodes in units of the plurality of memory transistors arranged in the one direction. A word line,
An operation circuit that selects a memory transistor to be operated and injects high-energy charges into the local portion of the stacked insulating film in order to set or change the data storage state of the selected memory transistor;
At the time of charge injection by the operation circuit, the local source / drain region that performs charge injection to a non-selected memory transistor whose source / drain region is electrically connected to the source / drain region of the memory transistor to be operated. A non-selected word line bias circuit for applying a predetermined voltage via a non-selected word line in a direction to relax the voltage between the drain region and the gate electrode;
A non-volatile memory device. The operating circuit has a maximum voltage applied to the two source / drain regions and the gate electrode of 6 V or less and a gate voltage applied to the gate electrode when the high energy charge is injected. One of three voltage conditions: a drain voltage applied between the drain regions, a voltage difference between the lower threshold voltage of the two threshold voltages defining the data storage state and the gate voltage is the drain voltage or less. The nonvolatile memory device according to claim 1, wherein a plurality of voltages including the gate voltage and the drain voltage are supplied to the memory transistor so as to satisfy the requirements. The unselected word line bias circuit is applied to the source / drain region functioning as the drain of the memory transistor to be operated with reference to the potential of the channel formation region or the potential of the source / drain region functioning as the source. The non-volatile memory device according to claim 1, wherein the predetermined voltage having the same polarity as a voltage to be applied is applied to the non-selected word line. Among the plurality of memory transistors arranged in a matrix, the number of memory transistors whose sources and drains are commonly connected, and any one of the memory transistors is subjected to drain voltage stress during the operation of another memory transistor. When the non-selected word line bias circuit performs the non-selection based on the limit value of the drain voltage range that determines whether or not the difference between two threshold voltages defining the storage state of the one memory transistor changes or not The nonvolatile memory device according to claim 1, wherein one limit value of an appropriate range is defined for the predetermined voltage to be applied to the word line. A read operation circuit for setting a read gate voltage between the two threshold voltages and reading the storage state;
For the predetermined voltage applied to the non-selected word lines by the non-selected word line bias circuit, the other limit value of the appropriate range is the lower value of the two threshold voltages defining the memory state The non-volatile memory device according to claim 3, wherein the non-volatile memory device is defined according to. The operation circuit includes an operation mode in which charge is injected into the local part of the stacked insulating film of the selected memory transistor by drain avalanche charge injection,
2. The nonvolatile memory device according to claim 1, wherein the non-selected word line bias circuit applies the predetermined voltage to the non-selected word line in advance prior to at least the drain avalanche charge injection. The operation circuit selects the memory transistor to be written during the operation of injecting the charge, applies a gate voltage to the gate electrode of the selected memory transistor, and functions as a drain of the selected memory transistor. The nonvolatile memory device according to claim 2, wherein a drain voltage that satisfies any of the three voltage conditions is applied to the drain region. The laminated insulating film is
An insulating film on the channel formation region;
A nitride film or an oxynitride film on the insulating film;
The nonvolatile memory device according to claim 1, comprising: The laminated insulating film is
An insulating film on the channel formation region;
A small particle conductor formed as the charge trap on the insulating film and insulated from each other with a particle size of 10 nanometers or less;
The nonvolatile memory device according to claim 1, comprising: Consists of two source / drain regions formed on a semiconductor substrate, and a plurality of insulating films stacked between a channel formation region and a gate electrode between the two source / drain regions, and charges are dispersed internally. A plurality of memory transistors each having a stacked insulating film held in a trap are arranged in a matrix and formed as a gate electrode common to a plurality of memory transistors arranged in one direction, or a plurality of memory transistors arranged in one direction A charge injection method for a non-volatile memory having a plurality of word lines formed by a conductive layer electrically connecting a plurality of gate electrodes in units of memory transistors,
Selecting a memory transistor to be operated; and
A source / drain region and a gate on the local side of the stacked insulating film for injecting charge into a non-selected memory transistor whose source / drain region is electrically connected to the source / drain region of the memory transistor to be operated Applying a predetermined voltage via a non-selected word line in a direction to relax the voltage between the electrodes;
Setting or changing the storage state of data by injecting high energy charges into the local of the memory transistor to be operated; and
A method for injecting charges in a nonvolatile memory device comprising: The operating circuit has a maximum voltage applied to the two source / drain regions and the gate electrode of 6 V or less and a gate voltage applied to the gate electrode when the high energy charge is injected. One of three voltage conditions: a drain voltage applied between the drain regions, a voltage difference between the lower threshold voltage of the two threshold voltages defining the data storage state and the gate voltage is the drain voltage or less. The method of claim 10, wherein a plurality of voltages including the gate voltage and the drain voltage are supplied to the memory transistor to satisfy the requirement. In the step of applying the predetermined voltage to the non-selected memory transistor, it functions as the drain of the memory transistor to be operated with reference to the potential of the channel formation region or the potential of the source / drain region that functions as a source. The charge injection method for a nonvolatile memory device according to claim 10, wherein the predetermined voltage having the same polarity as a voltage applied to a source / drain region to be applied is applied to the non-selected word line. Among the plurality of memory transistors arranged in a matrix, the number of memory transistors whose sources and drains are commonly connected, and any one of the memory transistors is subjected to drain voltage stress during the operation of another memory transistor. Sometimes, the difference between two threshold voltages defining the storage state of the one memory transistor changes or does not change based on the limit value of the drain voltage range to be applied to the unselected word line The charge injection method for a nonvolatile memory device according to claim 10, wherein one limit value of an appropriate range of the predetermined voltage is defined. 11. The other limit value of the appropriate range of the predetermined voltage applied to the non-selected word line is defined according to the lower value of the two threshold voltages that define the storage state. A charge injection method for a nonvolatile memory device according to claim 1. An operation mode in which a charge is injected by drain avalanche charge injection into a local part of the stacked insulating film of the selected memory transistor;
11. The method of injecting charge into a non-volatile memory device according to claim 10, wherein the predetermined voltage is applied in advance to the non-selected word lines prior to the drain avalanche charge injection. Injecting the high energy charge comprises:
Applying a gate voltage to the gate electrode of the selected memory transistor;
And applying a drain voltage that satisfies any of the three voltage conditions to a source / drain region that functions as a drain of the selected memory transistor. Method.

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