JP2003068096A - 磁気抵抗固体記憶装置において用いるデータ記憶方法 - Google Patents

磁気抵抗固体記憶装置において用いるデータ記憶方法

Info

Publication number
JP2003068096A
JP2003068096A JP2002216149A JP2002216149A JP2003068096A JP 2003068096 A JP2003068096 A JP 2003068096A JP 2002216149 A JP2002216149 A JP 2002216149A JP 2002216149 A JP2002216149 A JP 2002216149A JP 2003068096 A JP2003068096 A JP 2003068096A
Authority
JP
Japan
Prior art keywords
bits
symbol
row
bit
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002216149A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003068096A5 (enExample
Inventor
James A Davis
ジェイムス・アンドリュー・デイビス
Jonathan Jedwab
ジョナサン・ジェドワーブ
Kenneth Graham Paterson
ケネス・グラハム・パターソン
Gadiel Seroussi
ガディエル・セルーシ
K Smith Kenneth
ケネス・ケイ・スミス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003068096A publication Critical patent/JP2003068096A/ja
Publication of JP2003068096A5 publication Critical patent/JP2003068096A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
JP2002216149A 2001-07-25 2002-07-25 磁気抵抗固体記憶装置において用いるデータ記憶方法 Pending JP2003068096A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/915,195 US6981196B2 (en) 2001-07-25 2001-07-25 Data storage method for use in a magnetoresistive solid-state storage device
US09/915195 2001-07-25

Publications (2)

Publication Number Publication Date
JP2003068096A true JP2003068096A (ja) 2003-03-07
JP2003068096A5 JP2003068096A5 (enExample) 2005-10-20

Family

ID=25435383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002216149A Pending JP2003068096A (ja) 2001-07-25 2002-07-25 磁気抵抗固体記憶装置において用いるデータ記憶方法

Country Status (3)

Country Link
US (2) US6981196B2 (enExample)
EP (1) EP1282040A3 (enExample)
JP (1) JP2003068096A (enExample)

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US7688617B2 (en) 2005-10-18 2010-03-30 Nec Corporation MRAM and operation method of the same
WO2011036817A1 (ja) * 2009-09-28 2011-03-31 株式会社 東芝 磁気メモリ
JP2012022726A (ja) * 2009-09-28 2012-02-02 Toshiba Corp 磁気メモリ
US8281221B2 (en) 2005-10-18 2012-10-02 Nec Corporation Operation method of MRAM including correcting data for single-bit error and multi-bit error
US8347175B2 (en) 2009-09-28 2013-01-01 Kabushiki Kaisha Toshiba Magnetic memory
US8510633B2 (en) 2007-04-17 2013-08-13 Nec Corporation Semiconductor storage device and method of operating the same

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US6779168B2 (en) * 2002-02-01 2004-08-17 Lsi Logic Corporation Magnetoresistive memory for a complex programmable logic device
US6973604B2 (en) 2002-03-08 2005-12-06 Hewlett-Packard Development Company, L.P. Allocation of sparing resources in a magnetoresistive solid-state storage device
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US7266732B2 (en) * 2003-12-22 2007-09-04 Samsung Electronics Co., Ltd. MRAM with controller
US20080080226A1 (en) * 2006-09-25 2008-04-03 Thomas Mikolajick Memory system and method of operating the memory system
US8181089B1 (en) * 2007-08-24 2012-05-15 Datadirect Networks, Inc. Method for auto-correction of errors in a solid-state memory system
US8627165B2 (en) 2008-03-24 2014-01-07 Micron Technology, Inc. Bitwise operations and apparatus in a multi-level system
US8195978B2 (en) * 2008-05-16 2012-06-05 Fusion-IO. Inc. Apparatus, system, and method for detecting and replacing failed data storage
US8321758B2 (en) * 2008-08-05 2012-11-27 Advanced Micro Devices, Inc. Data error correction device and methods thereof
US8438455B2 (en) * 2008-12-31 2013-05-07 Intel Corporation Error correction in a solid state disk
US8307258B2 (en) 2009-05-18 2012-11-06 Fusion-10, Inc Apparatus, system, and method for reconfiguring an array to operate with less storage elements
US8281227B2 (en) * 2009-05-18 2012-10-02 Fusion-10, Inc. Apparatus, system, and method to increase data integrity in a redundant storage system
US8463983B2 (en) 2009-09-15 2013-06-11 International Business Machines Corporation Container marker scheme for reducing write amplification in solid state devices
US8370714B2 (en) * 2010-01-08 2013-02-05 International Business Machines Corporation Reference cells for spin torque based memory device
US8539303B2 (en) * 2010-12-20 2013-09-17 Intel Corporation Low overhead error correcting code protection for stored information
JP2016126813A (ja) 2015-01-08 2016-07-11 マイクロン テクノロジー， インク． 半導体装置

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7688617B2 (en) 2005-10-18 2010-03-30 Nec Corporation MRAM and operation method of the same
US8281221B2 (en) 2005-10-18 2012-10-02 Nec Corporation Operation method of MRAM including correcting data for single-bit error and multi-bit error
US8510633B2 (en) 2007-04-17 2013-08-13 Nec Corporation Semiconductor storage device and method of operating the same
WO2011036817A1 (ja) * 2009-09-28 2011-03-31 株式会社 東芝 磁気メモリ
JP2012022726A (ja) * 2009-09-28 2012-02-02 Toshiba Corp 磁気メモリ
US8347175B2 (en) 2009-09-28 2013-01-01 Kabushiki Kaisha Toshiba Magnetic memory

Also Published As

Publication number Publication date
US6981196B2 (en) 2005-12-27
US20030023926A1 (en) 2003-01-30
EP1282040A2 (en) 2003-02-05
US7107507B2 (en) 2006-09-12
US20030023924A1 (en) 2003-01-30
EP1282040A3 (en) 2004-08-04

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