JP2003066904A - Display panel drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the variation in current. SOLUTION: Transistors POUT0 to POUTn constitute a current mirror circuit with one transistor connected to a current source Iorg to constitute a reference current source and other N-pieces transistors. Switching circuits SW0-SWN periodically switch over transistors constituting the reference current source, so that the outputs from other N-pieces transistors are derived as the drive output for a display panel. Since the time-division control (averaged by time) is performed for the current variation of all, N+1 pieces MOS transistors, the current variation can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel drive circuit, and more particularly to a drive circuit for a display device using a display panel composed of a self-luminous element such as an organic electroluminescence element.

[0002]

2. Description of the Related Art An organic electroluminescence (hereinafter referred to as EL) element is known as a self-luminous element for realizing a thin and low power consumption display device. FIG. 4 is a diagram showing a schematic configuration of such an EL element. As shown in the figure, the EL element has a transparent substrate 100 made of a glass plate or the like on which a transparent electrode 101 is formed.
At least one organic functional layer 102 including an electron transport layer, a light emitting layer, a hole transport layer, and the like, and a metal electrode 103 are laminated on top.

FIG. 5 is an equivalent circuit that electrically shows the characteristics of such an EL element. As shown in the figure, the EL element can be replaced by a capacitance component C and a diode characteristic component E coupled in parallel with the capacitance component.
Here, the positive electrode of the transparent electrode 101, the metal electrode 10
When a negative voltage is applied to the cathode of No. 3 and a direct current is applied between the transparent electrode and the metal electrode, electric charge is accumulated in the capacitance component C. At this time, when the barrier voltage or the emission threshold voltage peculiar to the EL element is exceeded, a current starts to flow from the electrode (the anode side of the diode component E) to the organic functional layer serving as the light emitting layer, and the organic functional layer has an intensity proportional to the current. The layer 102 emits light.

FIG. 6 is a diagram showing a schematic configuration of an EL display device for displaying an image using an EL display panel in which a plurality of EL elements are arranged in a matrix. In FIG. 1, an ELDP 10 serving as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n that carry the first display line to the nth display line, and an array that intersects with the cathode lines B _{1 to} B _n. is the m anode lines (transparent electrodes) a ₁ to a _m are formed. These cathode lines B ₁ ~
EL elements E _{11 to} E _nm having the above-described structure are formed at the respective intersections of B _n and the anode lines A 1 to Am.

Each of the EL elements E _{11 to} E _nm is
It is responsible for one pixel as the LDP 10. Emission control circuit 1, one screen (n rows, m columns) input image data for each pixel of ELDP10, that is, the EL element E ₁₁ to E _nm pixel data groups D ₁₁ corresponding to each of ~D _The values are converted into _nm , and these are sequentially supplied to the anode line drive circuit 2 for each row as shown in FIG. For example, the pixel data D ₁₁ to D _nm, a m number of data bits that specify whether to implement the light emitting to the EL element E ₁₁ to E _nm respectively belonging to the first display line of ELDP10, respectively , "Light emission" when the logic level is "1",
When the logic level is "0", it indicates "non-light emission".

Further, the emission control circuit 1 sequentially scans each of the first display line to the nth display line of the ELDP 10 in synchronization with the pixel data supply timing for each row as shown in FIG. The scanning line selection control signal to be supplied is supplied to the cathode line scanning circuit 3. First, the anode line drive circuit 2
From the m data bits in the pixel data group, all the data bits at the logic level "1" designating "light emission" are extracted. Next, the anode line belonging to "columns" corresponding to the data bits each and the extracted selected all from among the anode lines A ₁ to A _m, connects the constant current source only to the selected anode line, predetermined The pixel drive current i is supplied.

The cathode ray scanning circuit 3 includes the cathode rays B _{1 to} B _n.
Of the above, the cathode line corresponding to the display line indicated by the scanning line selection control signal is selectively selected to set this cathode line to the ground potential, and a predetermined high potential Vcc is applied to each of the other cathode lines. Apply. The high potential V
cc is set to be approximately the same value as the voltage across the EL element (voltage determined based on the amount of charge in the parasitic capacitance C) when the EL element is emitting light with a desired luminance.

At this time, a light emission drive current is provided between the "column" to which the constant current source is connected by the anode line drive circuit 2 and the display line set to the ground potential by the cathode line scanning circuit 3. The EL elements formed by flowing and crossing the display lines and the "columns" emit light according to the light emission drive current. On the other hand, since no current flows between the display line set to the high potential Vcc by the cathode line scanning circuit 3 and the "column" to which the constant current source is connected, the display line and the "column" are crossed. The EL element thus formed remains non-luminous.

[0009] The above described operation is pixel data groups D ₁₁ ~
_{D 1m, D 21 ~D 2m,} ..., D n1 when to D _{n m} is performed on the basis of each, on the screen of ELDP10, 1 field of emission pattern corresponding to the input image data, i.e. image Is displayed.

[0010]

As described above, the output of the anode line drive circuit is a current output, and a current mirror is used for the current output. If the output current varies, the brightness of the organic EL panel also varies.
Therefore, it is very important to suppress the current variation. However, when the current mirror is used, the output current varies due to the current variation generated in the current mirror.

Here, a conventional circuit configuration is shown in FIG. In the figure, N + 1 MOS (Metal Ox)
A current mirror constructed using an ideal semiconductor transistor is shown. As shown in the figure, the current mirror circuit includes a current source I _org and N + 1 MOS transistors P _OUT0 and P _OUT .
_OUT1 , ..., P _OUTN . Of the N + 1 MOS transistors, one MOS transistor P _OUT0 forms the reference current source of the current mirror together with the current source I _org . Then, output currents from the other N MOS transistors are derived as drive outputs of the display panel. In this example, the outputs from the other N MOS transistors P _{OUT1 to} P _OUTN are combined into one, and the combined output current I _out is derived as the drive output.

Here, N + 1 MOS transistors P
Assume that _{OUT0 to} P _OUTN are all the same size.
Then, the ratio of the current derived by the MOS transistor P _OUT0 and the current derived by the other N MOS transistors P _{OUT1 to} P _OUTN , that is, the current ratio is 1: N.
Becomes Therefore, the output current I _{out at} this time is I _out = N
X I _org .

Generally, the current variation ΔI depends on the size of the MOS transistor, and the current variation ΔI is large when the size of the MOS transistor is small. vice versa,
When the size of the MOS transistor is large, the current variation ΔI is small. In applications such as display panel driving, the size of the "N" side MOS transistor of the current ratio 1: N is much larger than the size of the "1" side MOS transistor. For example, N> 10. From this, the variation ΔI of the current is equal to the MO on the side of the current ratio “1”.
The current variation generated from the S transistor P _out becomes dominant.

It is also possible to reduce the current ratio of the current mirror. For example, 2: N / 2 or 3: N /
It is possible to set it to 3. In this way, the current variation ΔI is reduced. However, since there are as many channels as the number of anode lines, in that case, the current amount of the current source I _org must be increased. Then, there is a drawback that the power consumption of the IC chip increases.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and its object is a display panel drive circuit capable of reducing variations in current without increasing power consumption of an IC chip. Is to provide.

[0016]

According to a first aspect of the present invention, there is provided a display panel driving circuit, wherein a transistor forming a reference current source and N transistors (N is a natural number) forming a current mirror circuit together with the transistor. A display panel drive circuit comprising:
Among these transistors, a transistor forming a reference current source includes switching means for periodically switching, and the output from the other N transistors is derived as a drive output of the display panel.

A display panel drive circuit according to a second aspect of the present invention is the display panel drive circuit according to the first aspect, wherein the outputs from the other N transistors are combined into one and derived as a drive output of the display panel. Is characterized by. A display panel drive circuit according to a third aspect of the present invention is the display panel drive circuit according to the first or second aspect, wherein the display panel is composed of electroluminescent elements driven by the drive outputs.

In short, by periodically switching the transistors forming the reference current source, it is possible to reduce the variation in the current generated in the current mirror, and to eliminate the variation in the reference current among a plurality of IC chips. Therefore, uniform emission brightness can be obtained on the display panel.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. In each of the drawings referred to in the following description, the same parts as those in the other drawings are designated by the same reference numerals. FIG. 1 is a diagram showing a configuration of a main part in an embodiment of a display panel drive circuit according to the present invention. The figure shows a current mirror circuit composed of N + 1 MOS transistors.

As shown in the figure, the current mirror
-The circuit is the current source I_orgAnd N + 1 MOS transistors
Star P_OUT0, P_OUT1, ..., P_OUTNAnd the switching circuit
SW0, SW1, ..., SWN
It The switching circuits SW0, SW1, ..., SWN are
N + 1 MOS transistors P_OUT0, P_OUT1, ..., P
_OUTNOnly one of the current sources I_orgAnd electrical
Connect to. This current source I_orgOne MO connected with
S transistor is the current source I_orgWith the current mirror
Will be the reference current source. And the other N M
The output current from the OS transistor is
It is derived as the drive output of the module. In this example, the other N
MOS transistor P_OUT1~ P_OUTNOutput from one
Summarized, this summarized output current I_outDriven out
Derived as force.

Switching circuits SW0 and SW in FIG.
1, ..., SWN, the current source I _orgConnected to
○, the output current I_outConnect to the signal line to derive
The terminals that are connected are indicated by ●. Switching circuit
When SW0 is connected to the ○ side terminal, another switch
The switching circuits SW1 to SWN are connected to the ● side terminal. Sui
When the switching circuit SW1 is connected to the ○ side terminal,
Switching circuits SW1 and SW2-SWN are ● side terminals
Connected to. Similarly, a switch connected to the ○ side terminal
The switching circuit is sequentially switched. This switch is
This is done in synchronization with the network.

As described above, the switching circuits SW0 to SW
By controlling N, among N + 1 MOS transistors P _OUT0 , P _OUT1 , ..., P _OUTN , the transistor forming the reference current source is periodically switched. In other words, by switching the switching circuit, N + 1 MO
All the S transistors are sequentially assigned to the "1" side of the current ratio 1: N that is dominant in the current variation.
Since the switching control is performed in this manner and the time-division control (averaged over time) is performed with respect to the current variations of all N + 1 MOS transistors, the current variations can be suppressed.

Here, if the number of transistors N = 3 and the variation of the transistors is 1%, the variation of the current is about 1.4% in the conventional case, whereas the circuit of the present invention shows that Variation is about 0.01%,
The current variations are much smaller. FIG. 2 is a timing chart showing the switching timing of the switching circuits SW0 to SWN. In the same figure, a clock that makes a timing for switching the switching circuits, an on / off state of each switching circuit, and an output current I _out are shown. In the figure, it is shown that the switching circuit in the high level is in the ON state.

In the figure, when the switching circuit SW0 is in the ON state, the output current I _out becomes N × I _ref + ΔI ₀ . Similarly, the output current I _out is N × I _ref + ΔI ₁ when the switching circuit SW1 is on, and the output current I _out is N × I _ref + when the switching circuit SW2 is on.
[Delta] I _2, and the switching circuit SWN the output current I _out the on state becomes _N × I _ref + ΔI N. Similarly, the transistor forming the reference current source is periodically switched by the switching circuit.

As described above, the transistor forming the reference current source
By switching the switch periodically, the current variation
Can be reduced. Where switching
An example of the circuit configuration is shown in FIG. Shown in the same figure
The corresponding switching circuits SW0 to SWN correspond to each other.
MOS transistor P _OUT0~ P_OUTNOutput from
It is configured to include two analog switches to which the current is input.
Has been. The switching circuit SW0 is an analog switch.
C SW01 and SW02. this
The analog switches SW01 and SW02 are both
N-type MOS transistor having a common source and drain
And a P-type MOS transistor.
Then, these N-type MOS transistor and P-type MOS
Gate common to transistors is switching control terminal
Becomes Also, in the figure, the clock described above is input.
The counter 200 for power and the switching circuits SW0 to SW0
Output 200 of counter 200 provided corresponding to SWN
Inverters INV0 to INV that invert −0 to 200-N
And VN are provided. Inverters INV0-INV0
The INVN is, for example, a well-known CMOS (Complement
nary Metal Oxide Semiconductor
inductor) Inverter circuit.

N-type MOS transistor of analog switch SW01 and P-type MOS transistor of analog switch SW02
While the output of the counter 200 is directly input to the transistor, the P-type MO of the analog switch SW01 is input.
N type M of S transistor and analog switch SW02
The output of the counter 200 is logically inverted and input to the OS transistor by the inverter INV0. Therefore, the analog switch SW01 is turned on only when the output 200-0 of the counter 200 is at the high level, and the analog switch SW02 is turned on when the output 200-0 is at the low level.

Similarly, for the switching circuit SW1 including the analog switch SW11 and the analog switch SW12, the analog switch SW11 is turned on only when the output 200-1 of the counter 200 is at high level, and the analog switch SW12 is turned on when it is at low level. It becomes a state. The same applies to the other switching circuits. In the switching circuit SWN, the analog switch SWN1 is turned on only when the output 200-N of the counter 200 is at high level, and the analog switch SWN2 is turned on when it is at low level.

As shown in the figure, the output sides of the analog switches SW01, SW11, ..., SWN1 are connected to the above-mentioned current source I _org , and the output sides of the analog switches SW02, SW12 ,. _Are combined into one and derived as an output current I _out . In such a configuration, the counter 200 receives the clock in FIG. 2 as an input and sets only one of the outputs 200-1 to 200-N as a high level pulse. Then, the high-level output is sequentially shifted. By applying high-level pulses while sequentially shifting in this way, as shown in FIG. 2 described above, the transistor forming the reference current source among the N + 1 MOS transistors is periodically switched. As a result, all the N + 1 MOS transistors are sequentially assigned to the “1” side of the current ratio 1: N that is dominant in the current variation. In this way, the switching control is performed and the time-division control is performed for the current variations of all N + 1 MOS transistors, so that the current variations can be suppressed. Note that, because of the above-described configuration, it is possible to suppress current variations without increasing the amount of current of the current source I _org .

Therefore, according to this circuit, it is possible to reduce the current variation generated in the current mirror without increasing the power consumption of the IC chip. Therefore, for example, by controlling the switching of the switching circuit with a clock having a repetition frequency of 1000 Hz, it is possible to temporally average the currents supplied to the display panel composed of the organic EL elements. Therefore, uniform emission brightness can be obtained on the display panel.

[0030]

As described above, according to the present invention, it is possible to reduce the current variation generated in the current mirror by periodically switching the transistor that forms the reference current source, and to reduce the variation in current between a plurality of IC chips. Since it is possible to eliminate the variation in the reference current, there is an effect that uniform emission brightness can be obtained on the display panel.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a main part of a display panel drive circuit according to the present invention.

FIG. 2 is a timing chart showing switching timing of a switching circuit in the display panel driving circuit of FIG.

FIG. 3 is a diagram illustrating a configuration example of a switching circuit.

FIG. 4 is a diagram showing a schematic configuration of an EL element.

FIG. 5 is a diagram showing an equivalent circuit that electrically shows the characteristics of an EL element.

FIG. 6 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of EL elements are arranged in a matrix.

FIG. 7 is a diagram showing a supply timing of pixel data and a scanning line selection signal.

FIG. 8 is a diagram showing a conventional circuit.

[Explanation of symbols]

1 light emission control circuit 2 anode line drive circuit 3 cathode line scanning circuit 100 transparent substrate 101 transparent electrode 102 organic functional layer 103 metal electrode 200 counter INV0 to INVN inverter I _org current source I _out output current P _{OUT0 to} P _OUTN transistors SW0 to SWN switching Circuit SW01, SW02 SW11, SW12 SW11, SW12 Analog switch

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05B 33/14 H05B 33/14 AF term (reference) 3K007 AB02 AB17 BA06 DA01 DB03 EB00 GA04 5C080 AA06 BB05 DD05 DD28 EE28 JJ03 JJ04

Claims (3)

[Claims] 1. A transistor forming a reference current source, and N forming a current mirror circuit together with the transistor.
A display panel drive circuit comprising N (N is a natural number) transistors, the N + 1 transistors including switching means for periodically switching a transistor forming a reference current source, and N other transistors. The display panel drive circuit is characterized in that the output from the display panel is derived as a drive output of the display panel. 2. The display panel drive circuit according to claim 1, wherein outputs from the other N transistors are combined into one and are derived as a drive output of the display panel. 3. The display panel drive circuit according to claim 1, wherein the display panel is composed of electroluminescent elements driven by the drive output.