JP2003066888A - Electrooptic device and its driving method and driving circuit, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which has small deterioration in picture quality even when a noise signal is superposed on an image signal. SOLUTION: The image signal is sampled according to a sampling signal and supplied to a data line. The sampling signal is generated according to an enable signal EN. An enable signal generating circuit 210 is equipped with a delay circuit group 204 which delays a clock signal CLK, a selecting circuit 202, and an up/down counter 203. The selecting circuit 202 selects input signals C1 to C4 according to a selection control signal CLT generated by the counter 203 to generate the enable signal EN.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device which has improved image quality deterioration due to noise, a driving method and driving circuit therefor, and an electronic apparatus.

[0002]

2. Description of the Related Art A conventional electro-optical device, for example, an active matrix type liquid crystal display device includes a liquid crystal panel and an image processing circuit. A liquid crystal panel mainly includes an element substrate in which switching elements are provided on each of pixel electrodes arranged in a matrix, an opposite substrate on which a color filter or the like is formed, and a liquid crystal filled between the both substrates. Composed of. In such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element becomes conductive. In this conductive state, when an image signal is applied to the pixel electrode via the data line, predetermined charges are accumulated in the liquid crystal layer between the pixel electrode and the counter electrode (common electrode). Even if the switching element is turned off after charge accumulation, charge accumulation in the liquid crystal layer is maintained if the resistance of the liquid crystal layer is sufficiently high. In this way, by controlling the amount of charges accumulated by driving each switching element, the alignment state of the liquid crystal changes for each pixel, and it becomes possible to display predetermined information.

At this time, since it is sufficient to accumulate the charges in the liquid crystal layer of each pixel only in a part of the period, firstly, each scanning line is sequentially selected by the scanning line driving circuit, and secondly,
During the scanning line selection period, the data line driving circuit sequentially selects one or more data lines,
In addition, with the configuration in which the image signal is sampled and supplied to the selected data line, the time division multiplex drive in which the scanning line and the data line are shared by a plurality of pixels can be performed.

On the other hand, the image signal processing circuit subjects the input image signal to predetermined processing such as gamma correction and amplification / inversion to generate an image signal. Then, the image signal processing circuit and the liquid crystal panel are connected by a flexible cable or the like, and the image signal is supplied to the liquid crystal panel via the cable.

[0005]

The timing control for driving the liquid crystal display device is generally performed based on the timing signal obtained by digital processing. Since this timing signal is a digital signal, it contains high frequency components and is synchronized with the image signal. Therefore, since the rising edge and the falling edge of the timing signal include many high frequency components, a noise signal synchronized with the edge of the timing signal may be superimposed on the image signal. Since the timing signal is synchronized with the image signal as described above, the noise signal may appear as a vertical line on the display screen.

In such a case, there is a problem that the quality of display image quality is deteriorated. In particular, with the progress of miniaturization of liquid crystal display devices, it is necessary to mount circuit boards and flexible cables at a high density, and noise countermeasures have become a big problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a liquid crystal display device in which image quality deterioration is small even if a noise signal is superimposed on the image signal. .

[0008]

A method of driving an electro-optical device according to the present invention comprises a plurality of scanning lines, a plurality of data lines, a transistor connected to each scanning line and each data line, and the transistor. Assuming an electro-optical device having a pixel electrode connected to each of the data lines, the scanning lines are sequentially selected, and the data lines are grouped into a plurality of data lines in a period in which the scanning lines are selected. Image signals corresponding to the respective blocks are simultaneously supplied on the basis of the sampling signals, which are sequentially executed for each block, and the phase of the sampling signals corresponding to the respective blocks is changed with reference to the timing when the level of the image signals changes. Is characterized by.

According to the present invention, even if noise is superimposed in synchronization with the image signal, the phase of the sampling signal can be changed, so that noise sampling can be reduced. As a result, noise in the displayed image can be made inconspicuous, and the image quality can be significantly improved.

In the driving method of the electro-optical device described above, a start pulse that becomes active at the start of the horizontal scanning period is shifted according to a clock signal to generate a plurality of shift pulses having different active periods.
It is preferable that the pulse width of each shift pulse is limited based on the enable signal having a pulse width narrower than the pulse width of each shift pulse to generate each sampling signal corresponding to each block. Further, it is preferable that a plurality of pulses that are synchronized with the clock signal and have different phases are generated, and one of the plurality of pulses is selected to generate the enable signal. According to the present invention, one of the plurality of pulses is selected to generate the enable signal, so that the phase of the sampling signal can be changed with respect to the image signal.

In addition, the step of selecting the plurality of pulses may be to select the plurality of pulses according to a predetermined order, or to select the plurality of pulses at random. It may be.

Next, the drive circuit of the electro-optical device according to the present invention comprises a plurality of scanning lines, a plurality of data lines, a transistor connected to each scanning line and each data line, and a transistor connected to the transistor. A scanning line drive circuit for sequentially selecting the scanning lines and a plurality of the data lines in a period in which the scanning lines are selected. Sampling circuit that simultaneously supplies the image signal corresponding to each data line for each block based on the sampling signal, and when each timing when the level of the image signal changes is the reference timing, the sampling signal of the sampling signal is changed from the reference timing. And a data line driving circuit that generates the sampling signal so as to change the time until the start of the active period. That.

According to the present invention, even if noise is superimposed in synchronization with the image signal, the time from the reference timing to the start of the active period of the sampling signal can be automatically changed. Can be reduced. As a result, noise in the displayed image can be made inconspicuous, and the image quality can be significantly improved.

Here, the data line drive circuit shifts a start pulse that becomes active at the start of a horizontal scanning period according to a clock signal to generate a plurality of shift pulses having different active periods, and a shift register.
And a logic circuit that limits the pulse width of each shift pulse and generates each sampling signal corresponding to each block based on an enable signal having a pulse width narrower than the pulse width of each shift pulse. . According to the present invention, the active period of the sampling signal is controlled based on the enable signal.

More specifically, a pulse generation circuit that generates a plurality of pulses that are synchronized with the clock signal and have different phases, and one of the plurality of pulses is selected to generate the enable signal. It is desirable to include an enable signal generation circuit having a selection circuit. According to the present invention, one of the plurality of pulses is selected to generate the enable signal, so that the phase of the sampling signal can be changed with respect to the image signal.

The drive circuit of the electro-optical device described above further includes a counter for counting the clock signal,
It is preferable that the selection circuit selects one of the plurality of pulses and generates the enable signal based on a count result of the counter. Here, the maximum value that can be counted by the counter may match the number of pulses having different active periods to be selected. Further, the counter may be a ring counter or an up / down counter.

Further, in the drive circuit of the electro-optical device described above, a random signal generation circuit for generating a random signal is provided, and the selection circuit selects one of the plurality of pulses based on the count result of the counter. May be selected to generate the enable signal. In this case, the phase of the sampling signal will change randomly.

In the drive circuit of the electro-optical device described above, a counter that counts the clock signal and is reset by a horizontal start pulse that indicates the start of a horizontal scanning period, and a horizontal counter that counts the horizontal start pulse. A count circuit that adds the count result of the counter and a count result of the horizontal counter, and the selection circuit selects one of the plurality of pulses based on the addition result of the adder circuit. It is desirable to generate the enable signal. According to the present invention, the phase of the sampling signal corresponding to a certain block is different in the adjacent horizontal scanning periods, so that it becomes possible to make the noise of the vertical line inconspicuous.

In the drive circuit of the electro-optical device described above, a counter that counts the clock signal and is reset by a field start pulse indicating the start of a field period, and a field counter that counts the field start pulse An adder circuit for adding the count result of the counter and the count result of the field counter is provided, and the selection circuit selects one of the plurality of pulses based on the addition result of the adder circuit, It is desirable to generate an enable signal. According to the present invention, the phase of the sampling signal corresponding to a certain block is different in adjacent field periods, so that noise can be made inconspicuous.

Next, the electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, transistors connected to the scanning lines and the data lines, and pixels connected to the transistors. An electro-optical panel having electrodes,
A scanning line drive circuit for sequentially selecting the scanning lines, and an image signal corresponding to each data line for each block in which the plurality of data lines are grouped based on a sampling signal in a period in which the scanning line is selected. The sampling circuit that supplies simultaneously and the sampling signal is generated so as to change the time from the reference timing to the start of the active period of the sampling signal when each timing when the level of the image signal changes is set as the reference timing. And a data line driving circuit. According to the present invention, even when noise is superimposed in synchronization with the image signal, the time from the reference timing to the start of the active period of the sampling signal can be automatically changed, so that noise can be sampled. It can be reduced. As a result, noise in the displayed image can be made inconspicuous, and the image quality can be significantly improved.

An electronic apparatus according to the present invention is characterized by including the above-mentioned electro-optical device and displaying an image. For example, a video projector, a portable personal computer, a pager, a mobile phone, a television set. ,
A viewfinder type or a monitor direct-view type video camera, a car navigation device, a PDA, or the like is applicable.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. <1. Overall Configuration of Electro-Optical Device> First, the electro-optical device according to the embodiment will be described by taking a liquid crystal display device as an example. FIG. 1 is a block diagram showing the electrical configuration of the liquid crystal display device. As shown in this figure, the liquid crystal display device includes a liquid crystal panel 100 and a timing generator 2.
00 and an image signal processing circuit 300. Of these, the timing generator 200 uses the input image signal V
Timing signals used in each unit in synchronization with the ID and image signals VID1 to VID6 (described later as necessary)
Is output. In addition, the image signal processing circuit 300
When the image signal VID of one system is input, the S / P conversion circuit 302 in the inside of the S / P converter circuit 302 inputs the image signal VID1 of six phases.
.. to VID6 after serial-parallel conversion and output. Here, the reason for serial-parallel conversion of the image signal into 6 phases is that the sampling circuit described later
This is because the application time of the image signal to the source region of each TFT functioning as a switching element is lengthened to sufficiently secure the sample & hold time and the charge / discharge time.
Further, the levels of the image signals VID1 to VID6 change every ½ cycle of the clock signal CLX, as shown in FIGS.

On the other hand, the amplification / inversion circuit 304 inverts the serial-to-parallel converted image signals that need to be inverted, and then appropriately amplifies them to obtain the image signal V.
ID1 to VID6 are supplied in parallel to the liquid crystal panel 100. Regarding whether to invert or not, generally, the application method of the data signal is polarity inversion on a scanning line basis, polarity inversion on a data line basis, polarity inversion on a pixel basis, or pixel basis on a pixel basis. Is determined depending on whether the polarity is inverted, and the inversion period is set to one horizontal scanning period or dot clock period, or one vertical scanning period. The polarity reversal in the present embodiment means that the voltage level is alternately inverted between the positive polarity and the negative polarity with reference to the amplitude center potential of the image signal.

<2. Configuration of Liquid Crystal Panel> Next, the electrical configuration of the liquid crystal panel 100 will be described. LCD panel 1
As will be described later, 00 has a structure in which an element substrate and a counter substrate are attached with their electrode formation surfaces facing each other. Of these, in the element substrate, a plurality of scanning lines 112 are arranged in parallel along the X direction in the drawing, and a plurality of data lines are arranged in parallel along the Y direction orthogonal to the scanning lines 112. 114 is formed. Then, at each intersection of the scanning line 112 and the data line 114, the TFT
While the gate electrode of 116 is connected to the scanning line 112,
The source electrode of the TFT 116 is connected to the data line 114, and the drain electrode of the TFT 116 is the pixel electrode 1.
It is connected to 18. Each pixel has a pixel electrode 1
18 and a common electrode formed on a counter substrate, which will be described later, and a liquid crystal sandwiched between these electrodes. As a result, a matrix is formed corresponding to each intersection of the scanning line 112 and the data line 114. It will be arranged. In addition to this, a storage capacitor (not shown) may be formed in parallel for each pixel with respect to the liquid crystal sandwiched between the pixel electrode 118 and the common electrode electrically.

The drive circuit 120 is composed of a data line drive circuit 130, a sampling circuit 140 and a scanning line drive circuit 150, and is formed on the peripheral surface of the display area on the opposing surface of the element substrate as described later. It is a thing. Since the active elements of these circuits can be formed by a combination of p-channel type TFTs and n-channel type TFTs, as will be described later, a manufacturing process common to the TFTs 116 for switching pixels (for example, the process temperature is about The formation at 1000 ° C.) is advantageous in terms of integration, manufacturing cost, device uniformity, and the like.

Here, the data line drive circuit 130 of the drive circuit 120 has a shift register and outputs the sampling signals S1 to Sm based on the clock signal CLX from the timing generator 200 and its inverted clock signal CLXINV. It is to output sequentially.

The sampling circuit 140 has six data lines 114 as one group, and the data lines 11 belonging to these groups.
4, the image signals VID1 to VID6 are sampled and supplied according to the sampling signals S1 to Sm. Specifically, the sampling circuit 14
At 0, a switch 141 composed of a TFT is provided for each data line 1
14 is provided at one end of each switch 141, and the source electrode of each switch 141 is connected to a signal line to which any of the image signals VID1 to VID6 is supplied.
One drain electrode is connected to one data line 114. Further, the gate electrode of each switch 141 connected to the data line 114 belonging to each group is connected to any of the signal lines to which the sampling signals S1 to Sm are supplied corresponding to the group. As described above, in the present embodiment, since the image signals VID1 to VID6 are supplied simultaneously, they are sampled at the same time by the sampling signal S1. The image signals VID1 to VID
When 6 is supplied at the timing of being sequentially shifted, it is sequentially sampled by the sampling signals S1, S2, ..., Sm.

The scanning line driving circuit 150 has a shift register, and sends a scanning signal to each scanning line 112 based on the clock signal CLY from the timing generator 200, its inverted clock signal CLYINV, the start pulse DY, and the like. It is to output sequentially. The start pulse DY
Are active for a predetermined time at the beginning of each field period.

<3. Data Line Drive Circuit> Next, the data line drive circuit 130 according to the present embodiment will be described. FIG. 2 is a circuit diagram showing the configuration of the data line driving circuit 130. The shift register 1350 is formed by cascading m + 1 (m is a natural number) stages of unit circuits R1 to Rm, and a start pulse DX supplied at the beginning of a horizontal scanning period is supplied in accordance with a clock signal CLX and an inverted clock signal CLXINV. The unit circuit in the previous stage (left side) is sequentially shifted and output to the unit circuit in the subsequent stage (right side). The start pulse D
X becomes active for a predetermined time at the start of each horizontal scanning period.

Of these unit circuits R1 to Rm + 1,
When the clock signal CLX is at the H level (the inverted clock signal C
A clocked inverter 1352 that inverts an input signal when LXINV is at L level, and a clocked inverter 1
Inverter 1354 that re-inverts the inverted signal by 352
And a clocked inverter 1356 that inverts the input signal when the clock signal CLX is at the L level (when the inverted clock signal CLYINV is at the H level).

On the other hand, among the unit circuits R1 to Rm + 1,
The unit circuits R2, R4, ..., Rm in the even stages basically have the same configuration as the unit circuits R1, R3 ,.
When the clock signal CLX is at L level, the input signal is inverted, and the clocked inverter 1356 causes the clock signal C to be inverted.
The difference is that the input signal is inverted when LX is at H level.

Next, referring to FIG. 2, the NAND circuit 137 is provided.
6, the inverter 1378, and the AND circuit 1379 are provided corresponding to the second stage to the (m + 1) th stage of the shift register 1350, respectively, and are configured in a complementary type by combining a p-channel TFT and an n-channel TFT. Has been done. Of these, in FIG.
The n-th (i = 2, ..., N) NAND circuit 1376 is
In the shift register 1350, the logical product of the output signal of the unit circuit located at the i-1th stage and the output signal of the unit circuit located at the i-th stage is inverted. In addition, the inverter 1378 at each stage has a corresponding NAND circuit 1378.
Invert the output signal of. Further, the AND circuit 1379
Is the logical product of the output signal of the corresponding inverter 1378 and the enable signal EN, and the sampling signals S1, S
2, ..., Sm are output.

Next, FIG. 3 is a timing chart showing the operation of the data line drive circuit 130. First, at the timing t11, the start pulse DX is started at the beginning of the horizontal scanning period.
Is input and the clock signal CLX rises (when the inverted clock signal CLXINV falls). Then, in the shift register 1350, the clocked inverter 1352 in the first-stage unit circuit R1 is
Since the H level of the start pulse DX is inverted and the inverter 1354 in the unit circuit R1 of the first stage also inverts the inversion result of the clocked inverter 1352, the output signal A from the unit circuit R1 of the first stage is It becomes H level.

Next, at the timing t12, during the period when the start pulse DX is input, the clock signal CLX
When (the inverted clock signal CLXINV rises), the clocked inverter 1356 in the first-stage unit circuit R1 inversely feeds back the H-level output signal A to the inverter 1354, so that the output signal A becomes H-level. Will be maintained. In addition, the unit circuit R of the second stage
The clocked inverter 1352 in FIG. 2 inverts the H level of the output signal A from the first-stage unit circuit R1,
Similarly, the inverter 13 in the second-stage unit circuit R2
Since 56 inverts the inversion result of the same clocked inverter 1352, the output signal B of the second-stage unit circuit R2 becomes H level.

Then, at the timing t13, the input of the start pulse DX is completed, and the clock signal CL is restarted.
When X rises (the inverted clock signal CLXINV falls), the clocked inverter 1352 in the first-stage unit circuit R1 takes in the L level of the start pulse DX, so that the output signal A of the unit circuit R1 becomes L. It becomes a level. On the other hand, the clocked inverter 1356 in the second-stage unit circuit R2 inverts the H-level output signal B back to the inverter 1354, so that the output signal B is maintained at the H-level. The clocked inverter 1352 in the unit circuit R3 in the third stage inverts the H level of the output signal B from the unit circuit R2 in the second stage, and the inverter 13 in the unit circuit R2 in the second stage also.
54 inverts the inversion result of the same clocked inverter 1552, so that the output signal C from the unit circuit R3 of the third stage becomes H level.

As a result of repeating the same operation thereafter, the first input start pulse DX is sequentially shifted by a half cycle of the clock signal CLX and its inverted clock signal CLXINV, and the unit circuit R1 to Rm + 1 outputs the output signal A.
It will be output as 1, A2, A3, ..., Am + 1. Then, the output signals A1, A2, A3, ..., Am +
The NAND circuit 1376 calculates the inversion of the logical product of the adjacent output signals, and the NAND circuit 1376 is further inverted by the inverters 1378. As a result, the signals B1, B2, B3, ... Bm are output from each inverter 1378.

The enable signal EN corresponds to each signal B.
Bm is active (H level) during a part of the period in which 1, B2, B3, ..., Bm are active (H level). Therefore, when each AND circuit 1379 calculates the logical product of the enable signal EN and the signals B1, B2, B3, ..., Bm, the sampling signals S1, S2, S3, ..., Which are limited to the pulse width W of the enable signal EN, Sm is obtained.

As shown in the figure, the enable signal EN is
The phase changes with respect to the clock signal CLX. For example,
The edge E1 of the clock signal CLK coincides with the edge E1 ′ of the enable signal, but the phase difference such as the time ΔT1 between the edges E2 and E2 ′ and the time ΔT2 between the edges E3 and E3 ′. There is. Therefore, the phases of the sampling signals S1, S2, S3, ..., Sm also change with respect to the clock signal CLX.
Further, the clock signal CLX is the image signals VID1 to VID.
6 and clock signal CLX as shown in the figure.
The levels of the image signals VID1 to VID6 change in synchronization with the rising edge and the falling edge of. Therefore, the sampling signals S1 and S1 are set based on the timing when the levels of the image signals VID1 to VID6 change.
It can be said that the phases of 2, S3, ..., Sm are changed.

<4. Timing Generator> Next, the enable signal generation circuit 210 which is a main part of the timing generator 200 will be described. FIG. 4 is a block diagram showing the configuration of the enable signal generation circuit 210.
FIG. 5 is a timing chart thereof. As shown in FIG. 4, the enable signal generation circuit 210 includes a trigger flip-flop 201, a selection circuit 202, an up / down counter 203, and a delay circuit group 204.

First, the reference clock signal CLK is supplied to the clock terminal of the trigger type flip-flop 201 from other components of the timing generator 200. The duty ratio of the reference clock signal CLK is 50%, and its cycle is 1 of the clock signal CLX.
/ 2. Therefore, the trigger type flip-flop 2
01 is obtained by dividing the reference clock signal CLK by 1/2.
To generate a clock signal CLX.

Next, the delay circuit group 204 is constituted by connecting three delay circuits 204a to 204c in cascade. Each of the delay circuits 204a to 204c can be configured by connecting an even number of inverters in multiple stages, for example. The delay time of each of the delay circuits 204a to 204c is TD. Further, the delay time TD is set so that TD = TX / 8, where TX is the time corresponding to one cycle of the clock signal CLX.

Next, the selection circuit 202 receives the input signals C1 to C4 (see FIG. 5) based on the 2-bit selection control signal CTL.
One of the above) is selected and output as the enable signal EN. The selection control signal CTL is generated by the up / down counter 203 and indicates its count value. Here, the up / down counter 203 counts the clock signal CLX. The count value is (00) → (01) → (1
When it reaches the maximum value such as 0) → (11), it starts counting down, and the count value is (11) → (10) →
When the minimum value is reached, such as (01) → (00),
It is supposed to start counting up.

In the above configuration, for example, if the value of the selection control signal CTL is (10) in the period T1 shown in FIG. 5, the selection circuit 202 selects the input signal C3, and the selection control is performed in the next period T2. The value of the signal CTL is (11)
Then, the selection circuit 202 selects the input signal C4.
As a result, the edge E10 'of the enable signal EN is
The edge E of the enable signal EN is delayed by 2TD with respect to the edge E10 of the clock signal CLK.
11 'is delayed by 3TD with respect to the edge E11 of the clock signal CLK. That is, according to the enable signal generation circuit 210, it is possible to sequentially change the phase of the enable signal EN with respect to the clock signal CLX. Further, the sampling signals S1, S2, ...
Since Sm is generated based on the enable signal EN,
The phases of the sampling signals S1, S2, ..., Sm with respect to the clock signal CLX are sequentially changed.

<5. Operation of Liquid Crystal Display Device> Next, an operation example of the liquid crystal display device will be described. FIG. 6 is a timing chart showing the operation of the liquid crystal display device. In this example, it is assumed that the noise N synchronized with the clock signal CLX jumps into the cable connecting the image signal processing circuit 300 and the liquid crystal panel 100, and the noise N is superimposed on the image signal VID1.

As shown in FIG. 6, noise N is superimposed on the image signal VID1. The noise N is generated, for example, due to the rising edge of the timing signal generated inside the timing generator 200. Here, in the data line drive circuit 130, the inverter 137 is used without limiting the pulse width using the enable signal EN.
8 output signals B1 to Bm to sampling signals S1 to S
If it is output as m, the image signal VID1 on which the noise N is superimposed is sampled by the sampling circuit 140, and the noise N is supplied to the data line 114 corresponding to the image signal VID1. Since the number of phase expansions in this example is 6,
In this case, the noise N is displayed every 6 vertical lines.

On the other hand, in the present embodiment, the enable signals EN are used to limit the pulse widths of the signals B1 to Bm to generate the sampling signals S1 to Sm. Then, as shown in FIG. 6, the phase of the enable signal EN is
It changes with respect to the clock signal CLX. On the other hand, since the phase of the image signal VID1 is synchronized with the clock signal CLX, the phase of the enable signal EN sequentially changes with respect to the image signal VID1. Therefore, the phases of the sampling signals S1 to Sm can be sequentially changed with respect to the image signal VID1.

Since the phase of the noise N is fixed with respect to the clock signal CLX, when the image signal VID1 is sampled using the sampling signals S1 to Sm, the noise N may or may not be sampled. . In the example shown in FIG. 6, the noise N is sampled in the period T10, but the periods T11 to T14 are sampled.
Then, the noise N is not sampled. Therefore, the image signal VID1 supplied to the data line 114 is equivalently VID1 ′ shown in FIG. As a result, the noise N is reduced.

If the generation timing of the noise N is known, the phase of the enable signal EN is fixed and the noise N is fixed.
It is also possible not to sample. However, the noise N is synchronized with the clock signal CLX, but at what timing the noise N is changed to the image signal VID.
It is difficult to predict whether to superimpose on 1 to VID6 because it is determined by the layout of the wiring and the arrangement of each circuit board and the liquid crystal panel. In the present embodiment, the phase of the enable signal EN is set to the clock signal CLX or the image signal VI.
The reason for sequentially changing D1 to VID6 is that the phase of the noise N is unknown. When the phase of the enable signal EN is sequentially changed, the noise N may be sampled. However, since the waveform of the noise N is a pulse shape, the noise N is often not sampled. Therefore, according to the present embodiment, the image quality deterioration due to the noise N can be improved.

<6. Configuration Example of Liquid Crystal Panel> Next, the overall configuration of the liquid crystal panel 100 having the above-described electrical configuration will be described with reference to FIGS. 7 and 8. Here, FIG.
8 is a perspective view showing a configuration of the liquid crystal panel 100, and FIG.
FIG. 8 is a sectional view taken along line ZZ ′ in FIG. 7.

As shown in these figures, the liquid crystal panel 100 includes an element substrate 101 such as glass or semiconductor on which a pixel electrode 118 and the like are formed, and a transparent counter substrate such as glass on which a common electrode 108 and the like is formed. 102 and spacer 10
The sealing material 10104 in which 3 is mixed maintains a constant gap, and the electrodes are bonded so that their electrode forming surfaces face each other, and the liquid crystal 1 as an electro-optical material is placed in this gap.
05 is enclosed. The sealing material 10
Although 4 is formed along the periphery of the counter substrate 102, a part thereof is opened for enclosing the liquid crystal 105.
Therefore, after the liquid crystal 105 is filled, the opening is sealed by the sealing material 106.

Here, the sampling circuit 140 and the data line driving circuit 130 described above are formed on the opposite surface of the element substrate 101 and on one outer side of the sealing material 104, and the data line 114 extending in the Y direction is formed. Is configured to drive. Further, a plurality of connection electrodes 107 are formed on one side of the timing generator 20.
0 and various signals from the image signal processing circuit 300 are input. Further, two scanning line driving circuits 150 are formed on the two sides adjacent to this one side so that the scanning lines 112 extending in the X direction are driven from both sides. If the delay of the scanning signal supplied to the scanning line 112 does not pose a problem, the scanning line driving circuit 150 may be formed on only one side. In addition, in order to reduce the load of writing the image signal to the data line 114, the element substrate 101 is provided with a precharge circuit that precharges each data line 114 to a predetermined potential at a timing preceding the image signal. May be.

On the other hand, the common electrode 108 of the counter substrate 102.
Is one of the four corners in the portion bonded to the element substrate 101.
By the conductive material provided in at least one place,
Electrical connection with the element substrate 101 is achieved. In addition, depending on the use of the liquid crystal panel 100, the counter substrate 102 may be, for example, firstly in a stripe shape or a mosaic shape,
A color filter arranged in a triangle shape or the like is provided, secondly, a metal material such as chromium or nickel, or a black matrix such as resin black in which carbon or titanium is dispersed in a photoresist is provided, and thirdly. A backlight for irradiating the liquid crystal panel 100 with light is provided. Particularly in the case of color light modulation, the black matrix is not formed and the black matrix is not formed.
02.

In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are provided with an alignment film or the like which is rubbed in a predetermined direction, and a polarizing plate (corresponding to the alignment direction) is provided on each back surface thereof. (Not shown) are provided respectively. However, if the polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-mentioned alignment film, the polarizing plate, etc. are not required, and as a result, the light utilization efficiency is increased, and thus high brightness and It is advantageous in terms of low power consumption.

Instead of forming part or all of the peripheral circuits such as the drive circuit 120 on the element substrate 101, for example, a drive IC chip mounted on a film by using the TAB (Tape Automated Bonding) technique is used. , Element substrate 1
01 may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position,
The driving IC chip itself may be electrically and mechanically connected to a predetermined position of the element substrate 101 via an anisotropic conductive film by using COG (Chip On Grass) technology.

<7. Modifications> The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example. (1) In the above-described embodiment, the selection circuit 202 is based on the count result of the up / down counter 203.
The input signals C1 to C4 are selected, but the input signals C1 to C4 may be randomly selected. In this case, a random signal generation circuit may be used instead of the up / down counter 203.

(2) Instead of the enable signal generating circuit 210 in the above embodiment, the enable signal generating circuit 211 shown in FIG. 9 may be used to configure the liquid crystal display device. The enable signal generation circuit 211 is different from the enable signal generation circuit 210 in that the up / down counter 203 is reset by the start pulse DX, and the start pulse DX is counted by the horizontal counter 205, and the count result and the up / down counter 203. This is the point where the selection control signal CTL is generated by adding the count result of 1 by the adding circuit 206.

The start pulse DX is a pulse which becomes active at the start of the horizontal scanning period. The horizontal counter 205 is a 2-bit ring counter. Since the input signals C1 to C4 in the selection circuit 202 are selected based on the addition result of the addition circuit 206, the count result of the horizontal counter 205 acts as an offset value in the selection order. That is, if the input signal C1 is selected at the start of a certain horizontal scanning period, the input signal C2 is selected at the start of the next horizontal scanning period.

Focusing on a certain pixel, adjacent pixels are sampled by sampling signals of different phases. As a result, the noise N can be further dispersed within one screen, and the image quality can be significantly improved.

(3) Instead of the enable signal generating circuit 210 in the above embodiment, the enable signal generating circuit 212 shown in FIG. 10 may be used to configure the liquid crystal display device. The enable signal generation circuit 212 is different from the enable signal generation circuit 210 in that the up / down counter 203 is reset by the start pulse DY, and the start pulse DY is counted by the field counter 207, and the count result and the up / down counter 203. The count control result is added by the adder circuit 206 to select the control signal CTL.
Is the point that generated.

The start pulse DY is a pulse which becomes active at the start of the field period. The field counter 207 is a 2-bit ring counter. Selection circuit 2
The input signals C1 to C4 in 02 are selected by the adder circuit 2
Since it is performed based on the addition result of 06, the count result of the field counter 207 acts as an offset value of the selection order. That is, if the input signal C1 is selected at the start of a certain field period, the input signal C2 is selected at the start of the next field period.

Focusing on a certain pixel, image signals sampled with sampling signals of different phases are supplied to adjacent fields in the pixel. This allows
The noise N can be further dispersed between the screens, and the image quality can be significantly improved.

<8. Electronic Device> Next, a case where the liquid crystal display device described above is applied to various electronic devices will be described. <Part 1: Projector> First, a projector using this liquid crystal panel as a light valve will be described.
FIG. 11 is a plan view showing a configuration example of the projector.
As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. This lamp unit 11
The projection light emitted from 02 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in a light guide 1104, and a liquid crystal panel 1110R as a light valve corresponding to each primary color. 1110B and 1110G.

The liquid crystal panels 1110R, 1110B and 1110G have the same structure as the liquid crystal panel 100 described above, and are driven by R, G and B primary color signals supplied from an image signal processing circuit (not shown). Is. Then, the light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted by 90 degrees, while the G light goes straight. Therefore, as a result of combining the images of each color,
A color image is projected on a screen or the like via the projection lens 1114. The liquid crystal panel 1110
Light corresponding to each of the primary colors of R, G, and B is incident on R, 1110B, and 1110G by the dichroic mirror 1108, so there is no need to provide a color filter.

<Part 2: Mobile Computer> Next, an example in which the liquid crystal display device is applied to a mobile personal computer will be described. FIG. 12 is a perspective view showing the configuration of this personal computer.
In the figure, a computer 1200 has a keyboard 12
Body part 1204 provided with 02 and the liquid crystal display unit 12
And 06. This liquid crystal display unit 12
06 is configured by adding a backlight to the back surface of the liquid crystal panel 100 described above.

<Part 3: Mobile Phone> Further, an example in which the liquid crystal display device is applied to a mobile phone will be described. FIG. 13 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1302 has a plurality of operation buttons 130.
In addition to 2, the liquid crystal panel 100 of the reflection type is provided. In this reflection type liquid crystal panel 100, a front light is provided on the front surface thereof as needed. In addition to the electronic devices described with reference to FIGS. 11 to 13, a liquid crystal television, a viewfinder type, a monitor direct-viewing type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work piece, and the like. Examples include stations, videophones, POS terminals, devices equipped with a touch panel, and the like. Needless to say, it can be applied to these various electronic devices.

[0066]

As described above, according to the present invention, noise can be reduced and the quality of the displayed image can be greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a data line driving circuit in the same device.

FIG. 3 is a timing chart showing waveforms of respective parts of the data line driving circuit.

FIG. 4 is a block diagram showing a configuration of an enable signal generation circuit of the device.

FIG. 5 is a timing chart showing a waveform of each part of the enable signal generation circuit.

FIG. 6 is a timing chart for explaining an operation example of the liquid crystal display device.

FIG. 7 is a perspective view showing a structure of a liquid crystal panel used in the device.

FIG. 8 is a partial cross-sectional view for explaining the structure of the liquid crystal panel.

FIG. 9 is a block diagram showing a configuration of an enable signal generation circuit of the same device according to a modified example.

FIG. 10 is a block diagram showing a configuration of an enable signal generation circuit of the same device according to a modified example.

FIG. 11 is a cross-sectional view showing a configuration of a projector as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 12 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 13 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

[Explanation of symbols]

100 ... Liquid crystal panel 112 ... Scan line 114 ... Data line 116 ... TFT (transistor) 130 ... Data line drive circuit 140 ... Sampling circuit 150 ... Scan line drive circuit 202 ... Selection circuit 203 ... Up-down counter (counter) 204 ... Delay circuit group (pulse generation circuit) 205 ... Horizontal counter 206 ... Adder circuit 207 ... Field counter 210-212 ... Enable signal generation circuit 1350 ... Shift register 1379 ... AND circuit EN: Enable signal S1 to Sm ... Sampling signal

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H093 NA16 NA43 NB23 NC16 NC22                       NC44 ND40                 5C006 AA01 AC21 AF71 BB16 BC03                       BC12 BC16 BC20 BC23 BF03                       BF06 BF07 BF11 BF22 BF24                       BF28 EC11 FA16 FA22                 5C080 AA10 BB05 DD05 EE29 FF11                       JJ02 JJ03 JJ04 JJ06

Claims (14)

[Claims] 1. A method of driving an electro-optical device having a plurality of scanning lines, a plurality of data lines, a transistor connected to each scanning line and each data line, and a pixel electrode connected to the transistor. The scanning lines are sequentially selected, and in the period in which the scanning lines are selected, image signals corresponding to each data line are simultaneously generated based on a sampling signal for each block in which the plurality of data lines are collected. A method of driving an electro-optical device, characterized in that the phase is supplied and sequentially executed for each block, and the phase of the sampling signal corresponding to each block is changed with reference to the timing when the level of the image signal changes. 2. A enable pulse having a pulse width narrower than the pulse width of each shift pulse is generated by shifting a start pulse that becomes active at the start of a horizontal scanning period according to a clock signal to generate a plurality of shift pulses having different active periods. The method of driving an electro-optical device according to claim 1, wherein the pulse width of each shift pulse is limited based on a signal to generate each sampling signal corresponding to each block. 3. A plurality of pulses that are synchronized with the clock signal and have different phases are generated, and one of the plurality of pulses is selected to generate the enable signal. A method for driving the electro-optical device according to the item 1. 4. The method of driving an electro-optical device according to claim 3, wherein the step of selecting the plurality of pulses includes selecting the plurality of pulses according to a predetermined order. 5. The method of driving an electro-optical device according to claim 3, wherein the step of selecting the plurality of pulses randomly selects the plurality of pulses. 6. A drive circuit for an electro-optical device having a plurality of scanning lines, a plurality of data lines, a transistor connected to each scanning line and each data line, and a pixel electrode connected to the transistor. A scanning line driving circuit for sequentially selecting the scanning lines, and sampling an image signal corresponding to each data line for each block in which the plurality of data lines are grouped in a period in which the scanning lines are selected. A sampling circuit that supplies simultaneously based on a signal, and the sampling so as to change the time from the reference timing to the start of the active period of the sampling signal when each timing when the level of the image signal changes is set as the reference timing. A drive circuit for an electro-optical device, comprising: a data line drive circuit that generates a signal. 7. The data line drive circuit includes a shift register that generates a plurality of shift pulses having different active periods by shifting a start pulse that becomes active at the start of a horizontal scanning period according to a clock signal, and each shift pulse. And a logic circuit that limits the pulse width of each shift pulse to generate each sampling signal corresponding to each block based on an enable signal having a pulse width narrower than the pulse width of the block. 6. The drive circuit for the electro-optical device according to item 6. 8. A pulse generation circuit that generates a plurality of pulses that are synchronized with the clock signal and have different phases, and a selection circuit that selects one of the plurality of pulses to generate the enable signal. The drive circuit of the electro-optical device according to claim 7, further comprising an enable signal generation circuit having the enable signal generation circuit. 9. A counter for counting the clock signal is provided, wherein the selection circuit selects one of the plurality of pulses based on a count result of the counter to generate the enable signal. The drive circuit of the electro-optical device according to claim 8. 10. A random signal generation circuit for generating a random signal is provided, wherein the selection circuit selects one of the plurality of pulses based on a count result of the counter to generate the enable signal. The drive circuit for the electro-optical device according to claim 8. 11. A counter that counts the clock signal and is reset by a horizontal start pulse that indicates the start of a horizontal scanning period, a horizontal counter that counts the horizontal start pulse, a count result of the counter, and the horizontal counter. And an adder circuit for adding the count result of the, the selection circuit, based on the addition result of the adder circuit,
9. The drive circuit of the electro-optical device according to claim 8, wherein one of the plurality of pulses is selected to generate the enable signal. 12. A counter which counts the clock signal and is reset by a field start pulse indicating the start of a field period, a field counter which counts the field start pulse, a count result of the counter and the field counter. An adding circuit for adding the count results, wherein the selection circuit is based on the addition result of the adding circuit,
9. The drive circuit of the electro-optical device according to claim 8, wherein one of the plurality of pulses is selected to generate the enable signal. 13. A plurality of scanning lines, a plurality of data lines,
An electro-optical panel having a transistor connected to each scanning line and each data line, and a pixel electrode connected to the transistor, a scanning line driving circuit that sequentially selects the scanning line, and the scanning line is selected A sampling circuit that simultaneously supplies an image signal corresponding to each data line based on a sampling signal for each block in which the data lines are grouped into a plurality of lines, and each time point when the level of the image signal changes. An electro-optical device comprising: a data line driving circuit that generates the sampling signal so that a time from the reference timing to the start of an active period of the sampling signal is changed when the reference timing is set. 14. An electronic apparatus comprising the electro-optical device according to claim 13 and displaying an image.