JP3752960B2 - ELECTRO-OPTICAL PANEL DATA LINE DRIVING METHOD, DATA LINE DRIVE DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE - Google Patents

Description

ここで、ｎ＝２ｊであり、ｊ番目のサンプリングパルスＳＲｊに着目すると、Ｘクロック信号ＸＣＫを基準としたとき、Ｘクロック信号ＸＣＫjの遅延時間ＴCKjは、ＴCKj＝（Ｔ０＋Ｔn+1）／２となる。これは、Ｘクロック信号供給線２１１の寄生容量および配線抵抗は、その長さに比例するからである。一方、各ラッチ回路ＵＬ0〜ＵＬn+1の遅延時間は若干のバラツキがあるものの概ね等しく、また、各バッファ回路ＵＢ0〜ＵＢn+1の遅延時間も同様に若干のバラツキがあるものの概ね等しい。したがって、平均化信号Ｓｈに対応する時間Ｔｈは、Ｘクロック信号ＸＣＫを基準としたときのサンプリングパルスＳＲｊの遅れ時間Ｔｊと等しい。
【００４８】
次に、可変遅延遅延回路４７０の構成を図４を参照しつつ説明する。図４は可変遅延回路４７０の構成を示すブロック図である。可変遅延回路４７０は、ラッチ回路４７１，４７２とＰＬＬ回路４８０とから構成されている。
【００４９】
ラッチ回路４７１，４７２は、４ビットのデータをクロック信号の立ち上がりエッジと立ち下がりエッジの両方でラッチするように構成されている。また、ＰＬＬ回路４８０は、Ｘクロック信号ＸＣＫと平均化信号Ｓｈに基づいて、Ｘクロック信号ＸＣＫに対して時間Ｔｊ（＝Ｔｈ）だけ遅延された遅延Ｘクロック信号ＸＣＫ’を生成するように構成されている。
【００５０】
このＰＬＬ回路４８０は、位相比較回路４８１、ローパスフィルタ４８２、加減算回路４８３、および電圧制御発振器４８４を備えている。位相比較回路４８１は、電圧制御発振器４８４の出力信号たる遅延Ｘクロック信号ＸＣＫ’とＸクロック信号ＸＣＫとの位相を比較して位相差信号４８１Ｓを出力する。位相差信号４８１はローパスフィルタ４８２によって高周波成分が除去され、加減算回路４８３の負入力端子に供給される。ローパスフィルタ４８２の出力信号Ｓｘは、Ｘクロック信号ＸＣＫを基準としたとき、遅延Ｘクロック信号ＸＣＫ’の遅れ時間Ｔｘを示している。
【００５１】
加減算回路４８３の第１正入力端子には平均化信号Ｓｈが供給され、その第２正入力端子にはオフセット電圧Ｖａが供給される。ここで、オフセット電圧Ｖａは、図示せぬ定電圧源より供給され、Ｘクロック信号ＸＣＫの１／４周期に相当する電圧である。以下、Ｘクロック信号ＸＣＫの１／４周期に相当する時間をＴｃで表すことにする。
【００５２】
加減算回路４８３の出力信号はＳｈ＋Ｖａ−Ｓｘとなり、これが誤差信号Ｓｇとして電圧制御発振器４８４に供給される。その出力信号たる遅延Ｘクロック信号ＸＣＫ’は、位相比較回路４８１にフィードバックされているから、誤差信号Ｓｇが「０」となるようにＰＬＬ回路４８０は動作する。ここで、ＳｈはＴｊに、ＶａはＴｃに、ＳｘはＴｘに各々対応している。したがって、Ｘクロック信号ＸＣＫに対する遅延Ｘクロック信号ＸＣＫ’の遅延時間Ｔｘは、Ｘクロック信号ＸＣＫに対するサンプリングパルスＳｊの遅延時間ＴｊおよびＸクロック信号ＸＣＫの１／４周期時間Ｔｃの合計と等しくなる。
【００５３】
これにより、入力画像データＤinは、Ｔｊ＋Ｔｃだけ遅延され画像データＤが生成される。
【００５４】
＜１−６．第１実施形態の動作＞
次に、第１実施形態に係る液晶装置の動作を説明する。図５は、データ線駆動回路とその周辺回路の動作を示すタイミングチャートである。Ｘクロック信号ＸＣＫがデータ線駆動回路２００に入力されると、Ｘクロック信号ＸＣＫはＸクロック信号供給線２１１を介して、Ｘシフトレジスタ２１０の各ラッチ回路ＵＬ0〜ＵＬn+1に供給される。
【００５５】
Ｘクロック信号供給線２１１には寄生容量等が付随しているので、図５に示すように、Ｘクロック信号ＸＣＫに対してＸクロック信号ＸＣＫ0は時間ＴCK0だけ遅れ、また、Ｘクロック信号ＸＣＫに対してＸクロック信号ＸＣＫn+1は時間ＴCKn+1だけ遅れる。
【００５６】
さらに、図５に示すように、サンプリングパルスＳＲ０は、Ｘクロック信号ＸＣＫ0に対して、ラッチ回路ＵＬ0の遅延時間ＴUL0とバッファ回路ＵＢ0の遅延時間ＴUB0だけ遅れる。また、サンプリングパルスＳＲn+1も同様に、Ｘクロック信号ＸＣＫn+1に対して、ラッチ回路ＵＬn+1の遅延時間ＴUln+1とバッファ回路ＵＢn+1の遅延時間ＴUbn+1だけ遅れる。
【００５７】
サンプリングパルスＳＲ０、ＳＲn+1は、画像データＤを実際にサンプリングするためには用いられず、Ｘクロック信号ＸＣＫに対してｊ番目のサンプリングパルスＳＲｊがどれだけ遅延しているかを推定するために用いられる。したがって、ラッチ回路ＵＬ0,ＵＬn+1およびバッファ回路ＵＢ0，ＵＢn+1は、この推定を行うためのダミー回路として作用する。
【００５８】
サンプリングパルスＳＲ０、ＳＲn+1が画像処理回路４００に供給されると、その制御部ＣＴＬのアンド回路４１０，４２０は、図５に示す出力信号４１０Ｓ，４２０Ｓを各々生成する。この図から明らかなように、サンプリングパルスＳＲ０に対応するＸクロック信号ＸＣＫの１周期Ｔａに占める出力信号４１０Ｓのハイレベル期間（遅延時間Ｔ０）の割合、およびサンプリングパルスＳＲn+1に対応するＸクロック信号ＸＣＫの１周期Ｔｂに占める出力信号４２０Ｓのハイレベル期間（遅延時間Ｔn+1）の割合は、他の期間と比べて相違している。
【００５９】
このため、ローパスフィルタ４３０，４４０によって、出力信号４１０Ｓ，４２０Ｓを積分すると、遅延時間Ｔ０，Ｔn+1に応じた電圧を得ることができる。ローパスフィルタ４３０，４４０の出力信号は、加算器４５０によって加算され、さらに電圧分割回路４６０によって１／２に分圧されるので、平均化信号Ｓｈの電圧は、遅延時間Ｔ０，Ｔn+1の平均値に応じたものとなる。換言すれば、平均化信号Ｓｈの電圧は、画像表示領域Ａの中で中央に位置するｊ番目のデータ線６ａに対応するサンプリングパルスＳＲｊの遅延時間Ｔｊに対応したものとなる。
【００６０】
上述した図４に示す可変遅延回路４７０では、この平均化信号Ｓｈの電圧にオフセット電圧Ｖａを加算したしたものを目標値として、ＰＬＬ回路４８０を動作させている。このため、遅延Ｘクロック信号ＸＣＫ’は、Ｘクロック信号ＸＣＫに対してＴｃ＋Ｔｊだけ遅延したものとなる。したがって、可変遅延回路４７０は、画像データＤをＸクロック信号ＸＣＫに対してＴｃ＋Ｔｊだけ遅延させることができる。
【００６１】
図６は、画像データとデータ線駆動回路の各種信号の関係を示すタイミングチャートである。ただし、図に示す画像データＤにおいて、第１番目の添字はフィールド番号を示し、第２番目の添字は水平走査方向の順番を示している。
【００６２】
この図に示すように、遅延Ｘクロック信号ＸＣＫ’は、Ｘクロック信号ＸＣＫに対してＴｃ＋Ｔｊだけ遅延している。一方、サンプリングパルスＳＲｊは、Ｘクロック信号ＸＣＫに対してＴｊだけ遅延しているので、サンプリングパルスＳｒｊの立ち下がりエッジは、画像データＤ１ｊの中央で発生する。
【００６３】
図２に示すように、サンプリング部２４０はスイッチ回路ＳＷ１〜ＳＷｎによって構成されており、第１ラッチ部２５０に取り込まれる画像データＤは、各スイッチ回路ＳＷ１〜ＳＷｎがオン状態からオフ状態に切り替わるタイミングで確定する。したがって、サンプリングパルスＳＲｊの立ち下がりエッジで第１ラッチ部２５０に取り込まれるデータが確定する。上述したようにサンプリングパルスＳＲｊの立ち下がりエッジは画像データＤ１ｊの中央で発生し、しかもサンプリングパルスＳＲｊは、画像表示領域Ａの中で中央に位置するｊ番目のデータ線６ａに対応するものである。したがって、サンプリングパルスＳＲ１〜ＳＲｎと画像データＤとの関係を最適な状態にすることができる。このため、図５に示すようにサンプリングパルスＳＲ１，ＳＲｎの立ち下がりエッジを、対応する画像データＤ１１，Ｄ１ｎの中で発生させることが可能となる。
【００６４】
このようにして、第１ラッチ部２５０に取り込まれた画像データＤが、点順次画像データＤａ１〜Ｄａｎとして第２ラッチ部２６０に出力されると、第２ラッチ部２６０は、図６に示すラッチパルスＬＡＴによって、各画像データＤａ１〜Ｄａｎをラッチして、同図に示す線順次画像データＤｂ１、Ｄｂ２、…、Ｄｂｎを生成する。これらの線順次画像データＤｂ１、Ｄｂ２、…、Ｄｂｎは、Ｄ／Ａ変換部２７０によってデータ線信号Ｘ１、Ｘ２、…、Ｘｎに変換され、各データ線６ａに供給される。
【００６５】
一方、走査線３ａには、線順次で順次アクティブとなる走査信号Ｙ１、Ｙ２、…、Ｙｍが供給されるので、各データ線信号Ｘ１、Ｘ２、…、Ｘｎが各走査信号Ｙ１、Ｙ２、…、Ｙｍに同期して１行毎に画素に取り込まれ、液晶に電圧が印加される。これを１垂直走査期間行うことによって、１枚の画像が表示されるのである。
【００６６】
このように本実施形態にあっては、Ｘ転送開始パルスＤＸをＸクロック信号ＸＣＫ等に従って順次転送することによって、データ線６ａの総数ｎよりも２個多い数のサンプリングパルスＳＲ０〜ＳＲn+1をＸシフトレジスタ２１０およびバッファ２３０（シフト手段）によって生成し、最初のサンプリングパルスＳＲ０と最後のサンプリングパルスＳＲn+1に基づいて、ｊ番目のサンプリングパルスＳＲｊの遅延時間Ｔｊを検知し、これに基づいて入力画像データＤinを遅延して画像データＤを生成するようにした。このため、Ｘクロック信号ＸＣＫを各ラッチ回路ＵＬ0〜ＵＬｎへ供給する際に遅延があったとしても、各サンプリングパルスＳＲ１〜ＳＲｎによって画像データＤを確実にラッチすることができる。
【００６７】
さらに、ラッチ回路ＵＬ0〜ＵＬｎやバッファ回路ＵＢ０〜ＵＢｎは、ＴＦＴによって構成される。ＴＦＴの動作速度は温度によって変化するため、ラッチ回路ＵＬ0〜ＵＬｎおよびバッファ回路ＵＢ０〜ＵＢｎの伝搬遅延時間は、環境の温度によって変化する。したがって、Ｘクロック信号ＸＣＫに対する各サンプリングパルスＳＲ０〜ＳＲn+1の遅延時間は、温度によって変化することになる。本実施形態によれば、温度変化の影響を受けるサンプリングパルスＳＲ０，ＳＲn+1に基づいて画像データＤの遅延時間が決定されるため、環境温度が動的に変化しても、画像データＤと各サンプリングパルスＳＲ１〜ＳＲｎとの位相関係を常に最適に維持できる。
【００６８】
＜２．第２実施形態＞
＜２−１．液晶装置の全体構成＞
次に、本発明の第２実施形態に係る液晶装置について説明する。図７は、第２実施形態に係る液晶装置の全体構成を示すブロック図である。この図に示すように、第２実施形態の液晶装置は、画像処理回路４００の替わり画像処理回路４００’を用いる点、画像データＤの替わりに画像信号ＶＩＤを液晶パネルＡＡに供給する点、およびデータ線駆動回路２００の替わりにデータ線駆動回路２００’を用いる点を除いて、第１実施形態の液晶装置と同一である。
以下、相違点について説明する。
【００６９】
＜２−２．データ線駆動回路＞
図８は、第２実施形態で用いるデータ線駆動回路の構成を示すブロック図である。この図に示すようにデータ線駆動回路２００’は、Ｘシフトレジスタ２１０、レベルシフタ２２０、バッファ２３０、およびサンプリング部２４０’から構成される。
【００７０】
このデータ線駆動回路２００’では、Ｘシフトレジスタ２１０とバッファ２３０との間にレベルシフタ２２０が設けられており、この点において、図２に示す第１実施形態のデータ線駆動回路２００と異なる。レベルシフタ２２０は、ｎ＋２個のレベルシフト回路ＵＬＳ0〜ＵＬＳn+1を備えており、Ｘシフトレジスタ２１０の各出力信号ｓｒ０〜ｓｒn+1にレベルシフトを施し、信号ｓｒ０'〜ｓｒn+1'として出力する。
【００７１】
レベルシフタ２２０を設けたのは、第２実施形態のサンプリング部２４０’でサンプリングする信号が画像信号ＶＩＤであり、サンプリングされた画像信号ＶＩＤをデータ線信号Ｘ１〜Ｘｎとして各データ線６ａに供給するからである。すなわち、第１実施形態では、サンプリング部２４０のサンプリングの対象が画像データＤであるため、そのスイッチ回路ＳＷ１〜ＳＷｎを小振幅で動作させればよいが、第２実施形態のサンプリング部２４０’は大振幅の画像信号ＶＩＤを各スイッチ素子ＳＷ１’〜ＳＷｎ’でサンプリングする必要がある。大振幅のサンプリングパルスＳＲ１〜ＳＲｎを用いてスイッチ素子ＳＷ１’〜ＳＷｎ’を制御する必要があるからである。
【００７２】
＜２−３．画像処理回路＞
次に、画像処理回路４００’について説明する。第２実施形態の画像処理回路４００’は、可変遅延回路４７０の替わりに可変遅延回路４７０’を用いる点を除いて、第１実施形態の画像処理回路４００と同一である。すなわち、第２実施形態の画像処理回路４００’においては、制御部ＣＴＬを備えており、そこで平均化信号Ｓｈを生成するまでの構成は、第１実施形態と同様である。
【００７３】
図９は、第２実施形態の可変遅延回路４７０’の構成を示すブロック図である。可変遅延回路４７０’が、図４に示す第１実施形態の可変遅延回路４７０と相違するのは、ラッチ回路４７２の替わりにＤ／Ａ変換器４７３を用いた点と、加減算回路４８３の入力からオフセット電圧Ｖａを除いた点である。なお、Ｄ／Ａ変換器４７３は遅延Ｘクロック信号Ｘ’の立ち上がりエッジおよび立ち下がりエッジの両方に同期してＤＡ変換を行うように構成されている。
【００７４】
まず、ラッチ回路４７２の替わりにＤ／Ａ変換器４７３を用いたのは、第２実施形態の液晶パネルＡＡは画像情報をアナログ信号で入力するからである。
【００７５】
次に、加減算回路４８３の入力からオフセット電圧Ｖａを除いたのは、以下の理由による。第１実施形態にあっては、各サンプリングパルスＳＲ１〜ＳＲｎの立ち下がりエッジのタイミングで各データ線６ａに供給する画像データＤが確定する。このため、オフセット電圧Ｖａを用いて、画像データＤと遅延Ｘクロック信号ＸＣＫ’の位相を１／４クロック周期時間Ｔｃだけ固定量としてずらす必要があった。これに対して、第２実施形態にあっては、各サンプリングパルスＳＲ１〜ＳＲｎがアクティブ（ハイレベル）となる期間において、データ線６ａに画像信号ＶＩＤが供給される。仮に、対応する画像信号ＶＩＤがアクティブとなる期間とサンプリングパルスＳＲ１〜ＳＲｎがアクティブとなる期間が一致しなければ、その不一致期間において隣接するデータ線６ａに供給すべき画像信号ＶＩＤが当該データ線６ａに混入することになる。このため、本実施形態にあっては、画像表示領域Ａの中央に位置するｊ番目のデータ線６ａに対応するサンプリングパルスＳＲｊと画像信号ＶＩＤのアクティブ期間を一致させるために、オフセット電圧Ｖａを除いたのである。
【００７６】
図９に示す可変遅延回路４７０’にあっては、加加減算回路４８３によって平均化信号Ｓｈからローパスフィルタの出力信号Ｓｘを減算したものが、誤差信号Ｓｇとして電圧制御発振器４８４に供給され、その出力信号たる遅延Ｘクロック信号ＸＣＫ’が位相比較回路４８１にフィードバックされる。ＰＬＬ回路４８０は誤差信号Ｓｇが「０」となるように動作するから、出力信号Ｓｘの電圧値は平均化信号Ｓｈの電圧値と等しくなる。ここで、平均化信号Ｓｈの電圧値は、第１実施形態で説明したように、Ｘクロック信号ＸＣＫに対するサンプリングパルスＳＲｊの遅延時間Ｔｊ（＝（Ｔ０＋Ｔn+1）／２）に対応するものであるから、Ｘクロック信号ＸＣＫに対する遅延Ｘクロック信号ＸＣＫ’の遅延時間をＴｊと一致させることができる。この結果、サンプリングパルスＳＲｊのアクティブ期間は、対応する画像信号ＶＩＤのアクティブ期間と一致する。
【００７７】
＜１−６．第２実施形態の動作＞
次に、第２実施形態に係る液晶装置の動作を説明する。図１０は、画像信号とデータ線駆動回路の各種信号の関係を示すタイミングチャートである。ただし、図に示す画像信号ＶＩＤにおいて、添字は水平走査方向の順番を示している。
【００７８】
この図に示すように、Ｘクロック信号ＸＣＫに対して、遅延Ｘクロック信号ＸＣＫ’はＴｊだけ遅延しており、また、サンプリングパルスＳＲｊも同様にＴｊだけ遅延している。このため、サンプリングパルスＳｒｊがアクティブ（ハイレベル）になると、画像信号ＶＩＤｊがｊ番目のデータ線６ａに供給される。一方、サンプリングパルスＳＲ１は画像信号ＶＩＤ１に対して進んでおり、サンプリングパルスＳＲｎの位相は画像信号ＶＩＤｎに対して遅れている。すなわち、サンプリングパルスＳＲｊを中心として、それ以前のサンプリングパルスは位相が進んでおり、それ以降のサンプリングパルスは位相が遅れることになる。このため、各サンプリングパルスＳＲ１〜ＳＲｎと画像信号ＶＩＤ１〜ＶＩＤｎにおいて、アクティブ期間が不一致となる期間においては、隣接するデータ線６ａに供給すべき画像信号ＶＩＤが当該データ線６ａに混入することになる。不一致期間の長さが長いと、本来表示すべき画像に時間的にずれた画像が薄く表示されるゴーストと呼ばれる現象が現れる。
【００７９】
しかしながら、不一致期間の長さは画面の中央で短く、画面の左右端にいく程大きくなるように分散されている。したがって、この液晶装置によれば画面の右端で不一致期間が長くなりゴーストが目立つといったことがなくなる。くわえて、人が表示画面を見る時、通常は、画面の中央を注視し、画面の左右端をさほど注視しない。このため、上述したように不一致期間を画面の中央で最小となるように調整することにより、人が画質劣化をあまり感じなくなるといった利点がある。
【００８０】
＜３．液晶パネルの構成例＞
次に、上述した第１実施形態および第２実施形態で説明した液晶パネルＡＡの全体構成について図１１および図１２を参照して説明する。ここで、図１１は、液晶パネルＡＡの構成を示す斜視図であり、図１２は、図１１におけるＺ−Ｚ’線断面図である。
【００８１】
これらの図に示されるように、液晶パネルＡＡは、画素電極９ａ等が形成されたガラスや半導体等の素子基板１０１と、共通電極１０８等が形成されたガラス等の透明な対向基板１０２とを、スペーサ１０３が混入されたシール材１０４によって一定の間隙を保って、互いに電極形成面が対向するように貼り合わせるとともに、この間隙に電気光学材料としての液晶１０５を封入した構造となっている。なお、シール材１０４は、対向基板１０２の基板周辺に沿って形成されるが、液晶１０５を封入するために一部が開口している。このため、液晶１０５の封入後に、その開口部分が封止材１０６によって封止されている。
【００８２】
ここで、素子基板１０１の対向面であって、シール材１０４の外側一辺においては、上述したデータ線駆動回路２００が形成されて、Ｙ方向に延在するデータ線１１４を駆動する構成となっている。さらに、この一辺には複数の接続電極１０７が形成されて、タイミング発生回路３００および画像信号処理回路４００からの各種信号を入力する構成となっている。くわえて、この接続電極１０７を介してサンプリングパルスＳＲ０，ＳＲn+1が出力される。
【００８３】
また、この一辺に隣接する２辺には、２個の走査線駆動回路１００が形成されて、Ｘ方向に延在する走査線３ａをそれぞれ両側から駆動する構成となっている。なお、走査線１１２に供給される走査信号の遅延が問題にならないのであれば、走査線駆動回路１００を片側１個だけに形成する構成でも良い。
【００８４】
一方、対向基板１０２の共通電極１０８は、素子基板１０１との貼合部分における４隅のうち、少なくとも１箇所において設けられた導通材によって、素子基板１０１との電気的導通が図られている。ほかに、対向基板１０２には、液晶パネルＡＡの用途に応じて、例えば、第１に、ストライプ状や、モザイク状、トライアングル状等に配列したカラーフィルタが設けられ、第２に、例えば、クロムやニッケルなどの金属材料や、カーボンやチタンなどをフォトレジストに分散した樹脂ブラックなどのブラックマトリクスが設けられ、第３に、液晶パネル１００に光を照射するバックライトが設けられる。特に色光変調の用途の場合には、カラーフィルタは形成されずにブラックマトリクスが対向基板１０２に設けられる。
【００８５】
くわえて、素子基板１０１および対向基板１０２の対向面には、それぞれ所定の方向にラビング処理された配向膜などが設けられる一方、その各背面側には配向方向に応じた偏光板（図示省略）がそれぞれ設けられる。ただし、液晶１０５として、高分子中に微小粒として分散させた高分子分散型液晶を用いれば、前述の配向膜、偏光板等が不要となる結果、光利用効率が高まるので、高輝度化や低消費電力化などの点において有利である。
【００８６】
なお、走査線駆動回路１００およびデータ線駆動回路２００の周辺回路の一部または全部を、素子基板１０１に形成する替わりに、例えば、ＴＡＢ（Tape Automated Bonding）技術を用いてフィルムに実装された駆動用ＩＣチップを、素子基板１０１の所定位置に設けられる異方性導電フィルムを介して電気的および機械的に接続する構成としても良いし、駆動用ＩＣチップ自体を、ＣＯＧ（Chip On Grass）技術を用いて、素子基板１０１の所定位置に異方性導電フィルムを介して電気的および機械的に接続する構成としても良い。
【００８７】
＜４．液晶装置の応用例＞
次に、第１実施形態および第２実施形態で説明した液晶装置を各種の電子機器に適用される場合について説明する。
【００８８】
＜その１：プロジェクタ＞
まず、この液晶装置をライトバルブとして用いたプロジェクタについて説明する。図１３は、プロジェクタの構成例を示す平面図である。
【００８９】
この図に示されるように、プロジェクタ１１００内部には、ハロゲンランプ等の白色光源からなるランプユニット１１０２が設けられている。このランプユニット１１０２から射出された投射光は、ライトガイド１１０４内に配置された４枚のミラー１１０６および２枚のダイクロイックミラー１１０８によってＲＧＢの３原色に分離され、各原色に対応するライトバルブとしての液晶パネル１１１０Ｒ、１１１０Ｂおよび１１１０Ｇに入射される。
【００９０】
液晶パネル１１１０Ｒ、１１１０Ｂおよび１１１０Ｇの構成は、上述した液晶パネルＡＡと同等であり、画像信号処理回路（図示省略）から供給されるＲ、Ｇ、Ｂの原色画像情報（画像データ、画像信号）でそれぞれ駆動されるものである。そして、これらの液晶パネルによって変調された光は、ダイクロイックプリズム１１１２に３方向から入射される。このダイクロイックプリズム１１１２においては、ＲおよびＢの光が９０度に屈折する一方、Ｇの光が直進する。したがって、各色の画像が合成される結果、投射レンズ１１１４を介して、スクリーン等にカラー画像が投写されることとなる。
【００９１】
ここで、各液晶パネル１１１０Ｒ、１１１０Ｂおよび１１１０Ｇによる表示像について着目すると、液晶パネル１１１０Ｇによる表示像は、液晶パネル１１１０Ｒ、１１１０Ｂによる表示像に対して左右反転することが必要となる。
【００９２】
なお、液晶パネル１１１０Ｒ、１１１０Ｂおよび１１１０Ｇには、ダイクロイックミラー１１０８によって、Ｒ、Ｇ、Ｂの各原色に対応する光が入射するので、カラーフィルタを設ける必要はない。
【００９３】
＜その２：モバイル型コンピュータ＞
次に、上述した液晶装置を、モバイル型のパーソナルコンピュータに適用した例について説明する。図１４は、このパーソナルコンピュータの構成を示す斜視図である。図において、コンピュータ１２００は、キーボード１２０２を備えた本体部１２０４と、液晶表示ユニット１２０６とから構成されている。この液晶表示ユニット１２０６は、先に述べた液晶パネル１００５の背面にバックライトを付加することにより構成されている。
【００９４】
＜その３：携帯電話＞
さらに、上述した液晶装置を、携帯電話に適用した例について説明する。図１５は、この携帯電話の構成を示す斜視図である。図において、携帯電話１３００は、複数の操作ボタン１３０２とともに、反射型の液晶パネル１００５を備えるものである。この反射型の液晶パネル１００にあっては、必要に応じてその前面にフロントライトが設けられる。
【００９５】
なお、図１３〜図１５を参照して説明した電子機器の他にも、液晶テレビや、ビューファインダ型、モニタ直視型のビデオテープレコーダ、カーナビゲーション装置、ページャ、電子手帳、電卓、ワードプロセッサ、ワークステーション、テレビ電話、POS端末、タッチパネルを備えた装置等などが挙げられる。そして、これらの各種電子機器に適用可能なのは言うまでもない。
【００９６】
＜５．変形例＞
（１）上述した各実施形態および応用例において、画像処理回路４００、４００’の全部あるいは一部を液晶パネルＡＡに内蔵してもよい。この場合には、画像処理回路４００、４００’を構成する能動素子としてＴＦＴを用い、これを走査線駆動回路１００やデータ線駆動回路２００に用いるＴＦＴと同一の半導体プロセスで素子基板１０１上に形成すればよい。
【００９７】
（２）上述した各実施形態にあっては、画像処理回路４００、４００’とデータ線駆動回路２００を別個なものとして説明したが、これらを合わせてデータ線駆動装置として捉えてもよいことは勿論である。
【００９８】
（３）上述した第１実施形態にあっては、オフセット電圧Ｖａを画像データ供給線の遅延を見込んだものとしてもよい。また、第２実施形態においても同様に画像信号供給線の遅延を見込んだオフセット電圧Ｖａを加減回路に供給するようにしてもよい。
【００９９】
（４）上述した各実施形態では、入力画像データＤinは１色に対応するものとして説明したが、ＲＧＢの３原色に対応するものであっても良い。この場合には、例えば、Ｘ方向にＲ、Ｇ、Ｂの順に画素を繰り返して配置し、ＲＧＢの画素の組に対して、１個のサンプリング信号を生成するようにしてもよい。また、データ線の駆動周波数を下げるために複数のデータ線を１ブロックとし、各ブロック毎にサンプリングパルスを生成するようにしてもよい。これらの場合にサンプリングパルスは、実際に画像信号のサンプリング用いられる数より２個多く生成すればよい。そして、最初のサンプリングパルスと最後のサンプリングパルスを画像処理回路にフィードバックして中央のサンプリングパルスの遅延時間を算出し、これに基づいて入力画像データＤｉｎを遅延して画像データＤを生成すればよい。
【０１００】
【発明の効果】
以上説明したように本発明よれば、各サンプリング信号のうち時間的に中央のタイミングで発生するサンプリング信号の遅延時間を検知し、検知された遅延時間に基づいて、入力画像情報を遅延して遅延画像情報を生成するから、遅延画像情報と時間的に中央のタイミングで発生するサンプリング信号の位相を自動的に合わせることが可能となる。
【図面の簡単な説明】
【図１】 本発明の第１実施形態に係る液晶装置の全体構成を示すブロック図である。
【図２】 同実施形態に用いるデータ線駆動回路２００のブロック図である。
【図３】 同実施形態に用いる画像処理回路４００のブロック図である。
【図４】 同画像処理回路４００に用いる可変遅延回路４７０のブロック図である。
【図５】 データ線駆動回路とその周辺回路の動作を示すタイミングチャートである。
【図６】 画像データとデータ線駆動回路の各種信号の関係を示すタイミングチャートである。
【図７】 第２実施形態に係る液晶装置の全体構成を示すブロック図である。
【図８】 第２実施形態で用いるデータ線駆動回路の構成を示すブロック図である。
【図９】 第２実施形態の可変遅延回路４７０’の構成を示すブロック図である。
【図１０】 画像信号とデータ線駆動回路の各種信号の関係を示すタイミングチャートである。
【図１１】 液晶パネルＡＡの構成を示す斜視図である。
【図１２】 図１１におけるＺ−Ｚ’線断面図である。
【図１３】 液晶装置を適用した電子機器の一例たるプロジェクタの構成を示す断面図である。
【図１４】 液晶装置を適用した電子機器の一例たるパーソナルコンピュータの構成を示す斜視図である。
【図１５】 液晶装置を適用した電子機器の一例たる携帯電話の構成を示す斜視図である。
【符号の説明】
ＡＡ……液晶パネル（電気光学パネル）
３ａ……走査線
６ａ……データ線
９ａ……画素電極
５０……ＴＦＴ（スイッチング素子）
２００……データ線駆動回路
２１０……Ｘシフトレジスタ（シフト手段）
２２０……レベルシフタ（シフト手段）
２３０……バッファ（シフト手段）
２４０……サンプリング部（サンプリング手段）
２５０……第１ラッチ部
２６０……第２ラッチ部
２７０……Ｄ／Ａ変換部（Ｄ／Ａ変換手段）
４００……画像処理回路
ＣＴＬ……制御部（検知手段、平均化信号生成手段）
４７０、４７０’……可変遅延回路（遅延手段）
Ｄin……入力画像データ（入力画像情報）
Ｄ……画像データ（遅延画像情報）
ＶＩＤ……画像信号（遅延画像情報）
ＤＸ……Ｘ転送開始パルス（開始パルス）
Ｘ１〜Ｘｎ……データ線信号
ＳＲ０〜ＳＲn+1……サンプリングパルス（サンプリング信号）
ＸＣＫ……Ｘクロック信号（入力クロック信号）
Ｓｈ……平均化信号[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data line driving method of an electro-optical panel, a data line driving device, an electro-optical device using the same, and an electronic apparatus.
[0002]
[Prior art]
A conventional electro-optical device, for example, an active matrix liquid crystal display device mainly includes an element substrate in which switching elements are provided on each of the pixel electrodes arranged in a matrix, and a counter substrate on which a color filter or the like is formed. And a liquid crystal filled between these two substrates. In such a configuration, when a scanning signal is applied to the switching element via the scanning line, the switching element becomes conductive. In this conductive state, when an image signal is applied to the pixel electrode via the data line, a predetermined charge is accumulated in the liquid crystal layer between the pixel electrode and the counter electrode (common electrode). Even if the switching element is turned off after the charge accumulation, if the resistance of the liquid crystal layer is sufficiently high, the charge accumulation in the liquid crystal layer is maintained. In this way, by controlling the amount of charge accumulated by driving each switching element, the alignment state of the liquid crystal changes for each pixel, and it becomes possible to display predetermined information.
[0003]
At this time, the charge can be accumulated in the liquid crystal layer of each pixel for a certain period. First, each scanning line is sequentially selected by the scanning line driving circuit, and second, the scanning line is selected. In the period, the data line driving circuit generates a sampling signal for sequentially selecting one or a plurality of data lines, and thirdly, each switch provided between each data line and the image signal supply line, By controlling based on the sampling signal, a configuration in which an image signal is supplied to each data line enables time-division multiplex driving in which the scanning line and the data line are shared by a plurality of pixels.
[0004]
[Problems to be solved by the invention]
By the way, in the driving method described above, it is premised that the phase of the sampling signal and the phase of the image signal match. In general, a data line driving circuit includes a shift register and a clock signal supply line and is formed on an element substrate, and the shift register is configured by connecting latch circuits in multiple stages and is supplied from one end thereof. The sampling signal is generated by sequentially transferring the transfer start pulse based on the clock signal.
[0005]
However, the clock signal supply line is accompanied by the input capacitance of each latch circuit and the parasitic capacitance of the wiring itself, and further has wiring resistance. Therefore, the clock signal supply line equivalently constitutes a ladder-type low-pass filter. Therefore, if the transfer start pulse is input to the leftmost latch circuit and sequentially transferred in the right direction, the clock signal supplied to the rightmost latch circuit with respect to the clock signal supplied to the leftmost latch circuit The signal is delayed by a time determined by the low-pass filter characteristics.
[0006]
Therefore, in the conventional data line driving circuit, a phase difference occurs between the sampling signal and the image signal due to the delay time of the clock signal. For this reason, there has been a problem that the image signal cannot be sampled at a desired timing and supplied to the data line, and the quality of the display image is deteriorated. As described above, when the scanning direction of the data line is from left to right, the image signal and the sampling signal are particularly misaligned at the right end of the screen. There was a problem of being an image.
[0007]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a data line driving method and apparatus capable of reducing a time difference between a sampling signal and an image signal, and the data line driving apparatus. And an electronic apparatus using the electro-optical device as a display unit.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a data line driving method of the present invention includes a plurality of scanning lines, a plurality of data lines, a switching element disposed corresponding to an intersection of the scanning lines and the data lines, Used in an electro-optical panel having a pixel electrode connected to a switching element, sequentially transferring start pulses in accordance with an input clock signal, and each sampling signal having a number two more than the number of signals actually used for sampling And an averaged signal indicating an average value of a first delay time corresponding to the first sampling signal and a second delay time corresponding to the last sampling signal, with the input clock signal as a reference, Based on the average signal, the input image information is delayed to generate delayed image information, and the first and last sampling signals of the sampling signals are divided. The delay image information is sampled based on the sampled signal, the data line signal for driving each data line is generated based on the sampled delay image information, and the data line signal is supplied to the corresponding data line. It is characterized by doing.
[0009]
According to the present invention, the start pulse is sequentially transferred according to the input clock signal to generate each of the sampling signals that is two more than the total number of the data lines, and corresponds to the first sampling signal based on the input clock signal. An average signal indicating an average value of the first delay time and the second delay time corresponding to the last sampling signal is generated. For this reason, the delay time can be indirectly detected without directly using the sampling signal generated at the temporally central timing among the sampling signals. As a result, malfunctions such as an image signal to be supplied to a data line adjacent to a certain data line due to a timing shift between the sampling signal and the input image information, or a data line adjacent to the data line. It is possible to eliminate the inconvenience that the image signal to be supplied is mixed and to greatly improve the quality of the display screen.
[0010]
Here, the step of generating each sampling signal, the step of sampling the delayed image information, and the step of generating the data line signal and supplying the data line signal to each data line are the same substrate as the substrate on which the switching element is formed. It is preferable that the step of generating the average signal and the step of generating the delay image information are performed on a substrate different from the substrate. In this case, since the generation of the averaged signal and the generation of the delayed image information are performed outside the electro-optical panel, the quality of the display screen can be improved without changing the configuration of the electro-optical panel so much.
[0011]
Next, the data line driving device according to the present invention includes a plurality of scanning lines, a plurality of data lines, a switching element arranged corresponding to the intersection of the scanning line and the data line, and a connection to the switching element. Assuming that the pixel electrode is used in an electro-optical panel, a start pulse is sequentially transferred in accordance with an input clock signal, and a shift that generates two sampling signals more than the number of signals actually used for sampling And an averaged signal for generating an averaged signal indicating an average value of a first delay time corresponding to the first sampling signal and a second delay time corresponding to the last sampling signal with reference to the input clock signal Generating means, delay means for delaying input image information to generate delayed image information based on the averaged signal, and among the sampling signals Based on the sampling signal excluding the first and last sampling signals, sampling means for sampling the delayed image information, and generating data line signals for driving each data line based on the sampled delayed image information, Data line signal generating means for supplying each data line signal to the corresponding data line.
[0012]
According to the present invention, the shift means sequentially transfers the start pulse in accordance with the input clock signal to generate each of the sampling signals that is two more than the total number of the data lines, and the averaged signal generation means includes the input clock signal Is used as a reference, an averaged signal indicating the average value of the first delay time corresponding to the first sampling signal and the second delay time corresponding to the last sampling signal is generated. For this reason, the delay time can be indirectly detected without directly using the sampling signal generated at the temporally central timing among the sampling signals. If the sampling signal is routed by wiring, noise may be superimposed on it, or the slew rate of the signal waveform may be reduced, affecting the sampling. Since the delay time is indirectly detected based on the sampling signal, image quality degradation accompanying the detection of the delay time does not occur in principle.
[0013]
Here, the data line driving device is provided with the shift unit, the sampling unit, and the data line signal generation unit on the same substrate as the substrate on which the switching element is formed, and a substrate different from the substrate. It is preferable that the averaged signal generating means and the delay means are provided above. In this case, since the detection of the delay time and the generation of the delay image information are performed outside the electro-optical panel, the quality of the display screen can be improved without changing the configuration of the electro-optical panel so much.
[0016]
In the data line driving device of the present invention, the averaged signal generating means outputs a pulse indicating a phase difference between them based on the input clock signal and the first sampling signal. A first integration circuit that integrates an output pulse of the first logic circuit, and a second logic circuit that outputs a pulse indicating a phase difference between the input clock signal and the last sampling signal based on the input clock signal and the last sampling signal A second integration circuit that integrates the output pulse of the second logic circuit; and an average value of the output signal of the first integration circuit and the output signal of the second integration circuit is calculated and output as the average signal It is preferable to provide an averaging circuit.
[0017]
Further, if the delayed image information is image data in a digital signal format, the data line signal generating means latches the image data supplied from the sampling means and converts it into dot sequential image data. Means, second latch means for latching the dot sequential image data for each horizontal scanning period and converting it into line sequential image data, and D / A converting the line sequential image data to generate the data line signal. And D / A conversion means for supplying each data line signal to the corresponding data line. According to the present invention, since the data line signal is generated based on the line sequential image data, a voltage corresponding to the gradation value of the image data can be constantly applied to each data line.
[0018]
In this case, the delay means determines a timing at which a sampling signal generated at a central timing in time among the sampling signals is switched from active to inactive, a period in which image data corresponding to the sampling signal is active. Preferably, the image data is generated by delaying the input image information based on the averaged signal so as to be generated at the center of the image. The image data at the timing when the active period of the sampling signal ends is taken into the first latch means. According to the present invention, the timing at which the sampling signal switches from active to inactive is the image corresponding to the sampling signal. Since the data can be generated in the middle of the active period, the time margin can be maximized.
[0019]
In addition, if the delayed image information is an image signal in an analog signal format, the data line signal generation means preferably supplies the image signal supplied from the sampling means to each data line.
[0020]
In this case, the delay means performs the averaging so that an active period of a sampling signal generated at a central timing in time among the sampling signals coincides with an active period of an image signal corresponding to the sampling signal. Preferably, the image signal is generated by delaying the input image information based on the signal. According to the present invention, the active period of the sampling signal generated at the central timing in time among the sampling signals can be matched with the active period of the corresponding image signal. Since there is almost no deterioration, the image quality when viewed as a whole screen can be improved.
[0021]
Next, in the electro-optical device of the present invention, a plurality of scanning lines, a plurality of data lines, a switching element arranged corresponding to the intersection of the scanning line and the data line, and the switching element An electro-optical panel having a pixel electrode connected to the data line, the data line driving device described above, and a scanning line driving device for driving each scanning line. According to the present invention, it is possible to improve image quality degradation caused by a time difference between a sampling signal and input image information.
Next, the electronic apparatus of the present invention is characterized by using this electro-optical device as a display unit. For example, a viewfinder, a mobile phone, a notebook computer, a video projector, etc. used for a video camera are used. Applicable.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0023]
<1. First Embodiment>
<1-1. Overall configuration of liquid crystal device>
First, a liquid crystal device using liquid crystal as an electro-optic material will be described as an example of the electro-optic device according to the present invention. The main part of the liquid crystal device is that an element substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element and a counter substrate are opposed to each other with an electrode formation surface facing each other, and a certain gap is maintained. And a liquid crystal panel AA in which liquid crystal is sandwiched between the gaps.
[0024]
FIG. 1 is a block diagram showing the overall configuration of the liquid crystal device according to the present embodiment. This liquid crystal device includes a liquid crystal panel AA and an external processing circuit. On the element substrate of the liquid crystal panel AA, an image display area A, a scanning line driving circuit 100, and a data line driving circuit 200 are formed. The liquid crystal device includes a timing generation circuit 300 and an image processing circuit 400 as external processing circuits.
[0025]
The input image data Din supplied to the liquid crystal device is in a 4-bit parallel format. In this example, in order to simplify the following description, the input image data Din is described as corresponding to one color, but the present invention is not limited to this and corresponds to the three primary colors of RGB. Of course, it may be.
[0026]
Here, the timing generation circuit 300 generates a Y clock signal YCK, an X clock signal XCK, a Y transfer start pulse DY, an X transfer start pulse DX, a latch pulse LAT, and the like in synchronization with the input image data Din. Are supplied to the scanning line driving circuit 100 and the data line driving circuit 200, respectively. The image processing circuit 400 includes a variable delay circuit as will be described later, and generates the image data D by delaying the input image data Din.
[0027]
<1-2. Image display area>
In the image display area A, as shown in FIG. 1, m scanning lines 3a are formed in parallel along the X direction, while n data lines 6a are formed along the Y direction. They are arranged in parallel. In the vicinity of the intersection of the scanning line 3a and the data line 6a, the gate of the TFT 50 is connected to the scanning line 3a, the source of the TFT 50 is connected to the data line 6a, and the drain of the TFT 50 is connected to the pixel electrode 9a. It is connected. Each pixel includes a pixel electrode 9a, a counter electrode formed on the counter substrate, and a liquid crystal sandwiched between the two electrodes. As a result, they are arranged in a matrix corresponding to each intersection of the scanning line 3a and the data line 6a.
[0028]
Further, scanning signals Y1, Y2,..., Ym are applied to each scanning line 3a to which the gate of the TFT 50 is connected in a pulse-sequential manner. For this reason, when a scanning signal is supplied to a certain scanning line 3a, the TFT 50 connected to the scanning line is turned on. Therefore, the data line signals X1, X2,..., Xn supplied from the data line 6a at a predetermined timing. Are sequentially written in the corresponding pixels and then held for a predetermined period.
[0029]
Here, since the orientation and order of liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, in the normally white mode, the amount of light passing through the liquid crystal is limited as the applied voltage increases, whereas in the normally black mode, the amount of light that is transmitted is reduced as the applied voltage increases. Then, light having contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display is possible. Note that the image display area A in this example is configured to operate in a normally white mode.
[0030]
In order to prevent the held image signal from leaking, a storage capacitor 51 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, since the voltage of the pixel electrode 9a is held by the storage capacitor 51 for a time that is three orders of magnitude longer than the time when the source voltage is applied, the holding characteristics are improved, and as a result, a high contrast ratio is realized. Become.
[0031]
<1-3. Scan Line Drive Circuit>
Next, the scanning line driving circuit 100 includes a Y shift register, a level shifter, and the like. The Y shift register shifts the Y transfer start pulse DY that becomes active at the start of the vertical scanning period in the Y direction using the Y clock YCK that is inverted every horizontal scanning period. The level shifter level-shifts the sequentially shifted signals to generate scanning signals Y1, Y2,. The scanning signals Y1, Y2,..., Ym are supplied in a pulse-sequential manner to the scanning line 3a. The scanning signals Y1, Y2,..., Ym are signals that are active during a predetermined period in one horizontal scanning period.
[0032]
<1-4. Data line drive circuit>
Next, the data line driving circuit 200 will be described. FIG. 2 is a block diagram of the data line driving circuit 200. As shown in FIG. 2, the data line driving circuit 200 includes an X shift register 210, a buffer 230, a sampling unit 240, a first latch unit 250, a second latch unit 260, and a D / A conversion circuit 270.
[0033]
The X shift register 210 includes an X clock signal supply line 211 that supplies an X clock signal XCK, an inverted X clock signal supply line 212 that supplies an inverted X clock signal XCKINV, and n + 2 latch circuits UL0 to ULn + 1. Yes. The X shift register 210 sequentially shifts the X transfer start pulse DX in accordance with the X clock signal XCK and the inverted X clock signal XCKINV to generate output signals sr0 to srn + 1. Each of the output signals sr0 to srn + 1 is a signal that becomes sequentially and exclusively active every half period of the X clock signal XCK.
[0034]
Here, the X clock signal XCK supplied to the latch circuits UL0 to ULn + 1 is represented by XCK0 to XCKn + 1, and the inverted X clock signal XCKINV is represented by XCKINV0 to XCKINVn + 1. Since the X clock signal supply line 211 and the inverted X clock signal supply line 212 are accompanied by parasitic capacitances such as input capacitances of the latch circuits UL0 to ULn + 1 and resistances of the wirings themselves, these supply lines are An equivalent ladder-type low-pass filter is formed. Therefore, the X clock signals XCK0 to XCKn + 1 and the inverted X clock signals XCKINV0 to XCKINVn + 1 are delayed with respect to the X clock signal XCK and the inverted X clock signal XCKINV.
[0035]
Next, the buffer 230 includes n + 2 buffer circuits UB0 to UBn + 1, and the output signals sr0, sr1, sr2,. , Output as sampling pulses SR0, SR1, SR2,..., SRn, SRn + 1.
[0036]
Next, the sampling unit 240 includes n switch circuits SW1 to SWn. The switch circuits SW1, SW2,..., SWn are controlled to be turned on / off by sampling pulses SR1, SR2,. When the sampling pulses SR1, SR2,..., SRn are active (high level) by the sampling unit 240, the image data D is sampled and supplied to the first latch unit 250. That is, n sampling pulses SR1, SR2,..., SRn are actually used for sampling. In other words, the X shift register 210 and the buffer 230 generate the sampling pulses SR0 to SRn + 1 that are two more than the number of signals actually used for sampling. This is because the image processing circuit 400 described later generates the image data D by delaying the input image data Din based on the sampling pulses SR0 and SRn + 1.
[0037]
Since the image data D of the present embodiment is in a 4-bit parallel format as described above, each switch circuit SW1, SW2,..., SWn is composed of four switch elements.
[0038]
Next, the first latch unit 250 includes n latch circuits (not shown) and latches image data D supplied via the switch unit 250. As a result, the image data D is converted into dot sequential image data Da1 to Dan. The second latch unit 260 is configured to latch the dot sequential image data Da1 to Dan using a latch pulse LAT. Here, the latch pulse LAT is a signal that becomes active every horizontal scanning period. Therefore, the second sequential latch unit 260 converts the dot sequential image data Da1 to Dan into line sequential image data Db1 to Dbn.
[0039]
Next, the D / A converter 270 is composed of n D / A converters (not shown), converts the line-sequential image data Db1 to Dbn from digital signals to analog signals, and converts them into data line signals. X1 to Xn are output to n data lines 6a, respectively.
[0040]
Any type of D / A converter may be used. For example, in addition to the decoder type, resistance division type, and capacitance division type, the internal capacitance of the D / A converter and the parasitic capacitance of the data line 6a A type that repeats charging and discharging a number of times according to the gradation values of the line sequential image data Db1 to Dbn can be applied.
[0041]
As described above, the X clock signal supply line 211 and the inverted X clock signal supply line 212 equivalently constitute a ladder-type low-pass filter, so that the X clock signals XCK0 to XCKn + 1 and the inverted X clock signal XCKINV0 to XCKINVn + 1 is delayed with respect to the X clock signal XCK and the inverted X clock signal XCKINV. For this reason, a phase difference occurs between the image data D and the sampling pulses SR1 to SRn, and the amount of the phase difference increases as the sampling pulse number advances.
[0042]
Here, with reference to the X clock signal XCK, the delay time of the sampling pulse SR0 is “T0”, the delay time of the X clock signal XCK0 is “TCK0”, the delay time of the latch circuit UL0 is “TULO”, and the buffer circuit UB0. The delay time of the sampling circuit SRn + 1 is “Tn + 1”, the delay time of the X clock signal XCKn + 1 is “TCKn + 1”, and the delay time of the latch circuit ULn + 1 is “ If TULn + 1 "and the delay time of the buffer circuit UBn + 1 are" TUbn + 1 "," T0 "and" Tn + 1 "are given by the following equations (1) and (2).
T0 = TCK0 + TULO + TUB0 (1)
Tn + 1 = TCKn + 1 + TULn + 1 + TUBn + 1 (2)
[0043]
<1-5. Image processing circuit>
Next, the configuration of the image processing circuit 400 will be described. FIG. 3 is a block diagram illustrating a configuration of the image processing circuit 400 according to the first embodiment. As shown in this figure, the image processing circuit 400 includes a variable delay circuit 470 and a control unit CTL that controls the variable delay circuit 470.
[0044]
The variable delay circuit 470 generates the image data D by delaying the input image data Din based on the average signal Sh generated by the control unit CTL.
[0045]
The control unit CTL includes inverters 409 and 419, AND circuits 410 and 420, low-pass filters 430 and 440, an adder 450, and a voltage dividing circuit 460. The AND circuit 410 calculates a logical product of the X clock signal XCK and the sampling pulse SR0 inverted by the inverter 409, and outputs it as a signal 410S, while the AND circuit 420 samples the X clock signal XCK and the sampling pulse inverted by the inverter 420. The logical product with the pulse SRn + 1 is calculated and output as a signal 420S.
[0046]
Since the sampling pulses SR0 and SRn + 1 are signals in one horizontal scanning cycle, the time difference between the X clock signal XCK and the sampling pulses SR0 and SRn + 1 is obtained by averaging the voltages of the signals 410S and 420S in one horizontal scanning cycle. (Phase difference) can be obtained. Both the low-pass filters 430 and 440 have the same configuration, and their cutoff frequencies are set to be lower than the horizontal scanning frequency. Therefore, the voltages of the output signals of the low-pass filters 430 and 440 indicate the delay times T0 and Tn + 1 represented by the above-described equations (1) and (2).
[0047]
Adder 450 adds the output signals of low-pass filters 430 and 440. The voltage dividing circuit 460 divides the output signal voltage of the adder 450 by half to generate an averaged signal Sh. This averaged signal Sh corresponds to Th = (T0 + Tn + 1) / 2. Th is given by the following equation (3).

Here, n = 2j, and focusing on the jth sampling pulse SRj, when the X clock signal XCK is used as a reference, the delay time TCKj of the X clock signal XCKj is TCKj = (T0 + Tn + 1) / 2. . This is because the parasitic capacitance and wiring resistance of the X clock signal supply line 211 are proportional to the length thereof. On the other hand, the delay times of the latch circuits UL0 to ULn + 1 are approximately equal with some variation, and the delay times of the buffer circuits UB0 to UBn + 1 are approximately equal with some variation as well. Therefore, the time Th corresponding to the averaged signal Sh is equal to the delay time Tj of the sampling pulse SRj when the X clock signal XCK is used as a reference.
[0048]
Next, the configuration of the variable delay delay circuit 470 will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the variable delay circuit 470. The variable delay circuit 470 includes latch circuits 471 and 472 and a PLL circuit 480.
[0049]
The latch circuits 471 and 472 are configured to latch 4-bit data at both the rising edge and falling edge of the clock signal. Further, the PLL circuit 480 is configured to generate a delayed X clock signal XCK ′ delayed by a time Tj (= Th) with respect to the X clock signal XCK based on the X clock signal XCK and the averaged signal Sh. ing.
[0050]
The PLL circuit 480 includes a phase comparison circuit 481, a low-pass filter 482, an addition / subtraction circuit 483, and a voltage controlled oscillator 484. The phase comparison circuit 481 compares the phases of the delayed X clock signal XCK ′, which is an output signal of the voltage controlled oscillator 484, and the X clock signal XCK, and outputs a phase difference signal 481S. A high-frequency component is removed from the phase difference signal 481 by the low-pass filter 482 and supplied to the negative input terminal of the addition / subtraction circuit 483. The output signal Sx of the low-pass filter 482 indicates the delay time Tx of the delayed X clock signal XCK ′ when the X clock signal XCK is used as a reference.
[0051]
The averaging signal Sh is supplied to the first positive input terminal of the addition / subtraction circuit 483, and the offset voltage Va is supplied to the second positive input terminal. Here, the offset voltage Va is supplied from a constant voltage source (not shown) and is a voltage corresponding to a quarter cycle of the X clock signal XCK. Hereinafter, a time corresponding to a quarter cycle of the X clock signal XCK is represented by Tc.
[0052]
The output signal of the addition / subtraction circuit 483 becomes Sh + Va−Sx, which is supplied to the voltage controlled oscillator 484 as the error signal Sg. Since the delayed X clock signal XCK ′, which is the output signal, is fed back to the phase comparison circuit 481, the PLL circuit 480 operates so that the error signal Sg becomes “0”. Here, Sh corresponds to Tj, Va corresponds to Tc, and Sx corresponds to Tx. Therefore, the delay time Tx of the delayed X clock signal XCK ′ with respect to the X clock signal XCK is equal to the sum of the delay time Tj of the sampling pulse Sj with respect to the X clock signal XCK and the ¼ period time Tc of the X clock signal XCK.
[0053]
Thereby, the input image data Din is delayed by Tj + Tc, and the image data D is generated.
[0054]
<1-6. Operation of First Embodiment>
Next, the operation of the liquid crystal device according to the first embodiment will be described. FIG. 5 is a timing chart showing the operation of the data line driving circuit and its peripheral circuits. When the X clock signal XCK is input to the data line driving circuit 200, the X clock signal XCK is supplied to the latch circuits UL0 to ULn + 1 of the X shift register 210 via the X clock signal supply line 211.
[0055]
Since the X clock signal supply line 211 is accompanied by a parasitic capacitance or the like, as shown in FIG. 5, the X clock signal XCK0 is delayed by a time TCK0 with respect to the X clock signal XCK, and is also relative to the X clock signal XCK. Thus, the X clock signal XCKn + 1 is delayed by time TCKn + 1.
[0056]
Further, as shown in FIG. 5, the sampling pulse SR0 is delayed from the X clock signal XCK0 by the delay time TUL0 of the latch circuit UL0 and the delay time TUB0 of the buffer circuit UB0. Similarly, the sampling pulse SRn + 1 is delayed from the X clock signal XCKn + 1 by the delay time TUln + 1 of the latch circuit ULn + 1 and the delay time TUbn + 1 of the buffer circuit UBn + 1.
[0057]
The sampling pulses SR0 and SRn + 1 are not used to actually sample the image data D, but are used to estimate how much the jth sampling pulse SRj is delayed with respect to the X clock signal XCK. It is done. Therefore, the latch circuits UL0 and ULn + 1 and the buffer circuits UB0 and UBn + 1 function as dummy circuits for performing this estimation.
[0058]
When the sampling pulses SR0 and SRn + 1 are supplied to the image processing circuit 400, the AND circuits 410 and 420 of the control unit CTL generate output signals 410S and 420S shown in FIG. As is apparent from this figure, the ratio of the high level period (delay time T0) of the output signal 410S to one cycle Ta of the X clock signal XCK corresponding to the sampling pulse SR0 and the X clock corresponding to the sampling pulse SRn + 1. The ratio of the high level period (delay time Tn + 1) of the output signal 420S to one cycle Tb of the signal XCK is different from other periods.
[0059]
Therefore, when the output signals 410S and 420S are integrated by the low-pass filters 430 and 440, voltages corresponding to the delay times T0 and Tn + 1 can be obtained. Since the output signals of the low-pass filters 430 and 440 are added by the adder 450 and further divided by ½ by the voltage dividing circuit 460, the voltage of the average signal Sh is the average of the delay times T0 and Tn + 1. It depends on the value. In other words, the voltage of the average signal Sh corresponds to the delay time Tj of the sampling pulse SRj corresponding to the jth data line 6a located in the center in the image display area A.
[0060]
In the variable delay circuit 470 shown in FIG. 4 described above, the PLL circuit 480 is operated with a target value obtained by adding the offset voltage Va to the voltage of the average signal Sh. Therefore, the delayed X clock signal XCK ′ is delayed by Tc + Tj with respect to the X clock signal XCK. Therefore, the variable delay circuit 470 can delay the image data D by Tc + Tj with respect to the X clock signal XCK.
[0061]
FIG. 6 is a timing chart showing the relationship between image data and various signals of the data line driving circuit. However, in the image data D shown in the figure, the first subscript indicates the field number, and the second subscript indicates the order in the horizontal scanning direction.
[0062]
As shown in this figure, the delayed X clock signal XCK ′ is delayed by Tc + Tj with respect to the X clock signal XCK. On the other hand, since the sampling pulse SRj is delayed by Tj with respect to the X clock signal XCK, the falling edge of the sampling pulse Srj occurs at the center of the image data D1j.
[0063]
As shown in FIG. 2, the sampling unit 240 includes switch circuits SW1 to SWn, and the image data D captured by the first latch unit 250 is the timing at which the switch circuits SW1 to SWn are switched from the on state to the off state. Confirm with. Therefore, data taken into the first latch unit 250 is determined at the falling edge of the sampling pulse SRj. As described above, the falling edge of the sampling pulse SRj occurs at the center of the image data D1j, and the sampling pulse SRj corresponds to the jth data line 6a located at the center in the image display area A. . Therefore, the relationship between the sampling pulses SR1 to SRn and the image data D can be brought into an optimum state. Therefore, as shown in FIG. 5, the falling edges of the sampling pulses SR1 and SRn can be generated in the corresponding image data D11 and D1n.
[0064]
In this way, when the image data D captured by the first latch unit 250 is output to the second latch unit 260 as the dot sequential image data Da1 to Dan, the second latch unit 260 performs the latch shown in FIG. The image data Da1 to Dan are latched by the pulse LAT, and line sequential image data Db1, Db2,..., Dbn shown in FIG. The line sequential image data Db1, Db2,..., Dbn are converted into data line signals X1, X2,..., Xn by the D / A converter 270 and supplied to the data lines 6a.
[0065]
On the other hand, scanning signals Y1, Y2,..., Ym that are sequentially active in a line sequential manner are supplied to the scanning line 3a, so that the data line signals X1, X2,. , Ym are taken into the pixels for each row and a voltage is applied to the liquid crystal. By performing this for one vertical scanning period, one image is displayed.
[0066]
As described above, in the present embodiment, the X transfer start pulse DX is sequentially transferred according to the X clock signal XCK and the like, so that the number of sampling pulses SR0 to SRn + 1 which is two more than the total number n of the data lines 6a is obtained. The delay time Tj of the jth sampling pulse SRj is detected based on the first sampling pulse SR0 and the last sampling pulse SRn + 1, which are generated by the X shift register 210 and the buffer 230 (shift means), and based on this The input image data Din is delayed to generate the image data D. For this reason, even if there is a delay in supplying the X clock signal XCK to the latch circuits UL0 to ULn, the image data D can be reliably latched by the sampling pulses SR1 to SRn.
[0067]
Further, the latch circuits UL0 to ULn and the buffer circuits UB0 to UBn are constituted by TFTs. Since the operating speed of the TFT changes depending on the temperature, the propagation delay times of the latch circuits UL0 to ULn and the buffer circuits UB0 to UBn change depending on the environmental temperature. Therefore, the delay time of each sampling pulse SR0 to SRn + 1 with respect to the X clock signal XCK varies with temperature. According to the present embodiment, since the delay time of the image data D is determined based on the sampling pulses SR0 and SRn + 1 affected by the temperature change, even if the environmental temperature changes dynamically, the image data D The phase relationship with each of the sampling pulses SR1 to SRn can always be maintained optimally.
[0068]
<2. Second Embodiment>
<2-1. Overall configuration of liquid crystal device>
Next, a liquid crystal device according to a second embodiment of the invention will be described. FIG. 7 is a block diagram showing the overall configuration of the liquid crystal device according to the second embodiment. As shown in this figure, the liquid crystal device of the second embodiment uses an image processing circuit 400 ′ instead of the image processing circuit 400, supplies an image signal VID to the liquid crystal panel AA instead of the image data D, and The liquid crystal device is the same as that of the first embodiment except that a data line driving circuit 200 ′ is used instead of the data line driving circuit 200.
Hereinafter, differences will be described.
[0069]
<2-2. Data line drive circuit>
FIG. 8 is a block diagram showing a configuration of a data line driving circuit used in the second embodiment. As shown in this figure, the data line driving circuit 200 ′ includes an X shift register 210, a level shifter 220, a buffer 230, and a sampling unit 240 ′.
[0070]
In this data line driving circuit 200 ′, a level shifter 220 is provided between the X shift register 210 and the buffer 230, and this is different from the data line driving circuit 200 of the first embodiment shown in FIG. The level shifter 220 includes n + 2 level shift circuits ULS0 to ULSn + 1, performs level shift on the output signals sr0 to srn + 1 of the X shift register 210, and outputs them as signals sr0 'to srn + 1'. .
[0071]
The level shifter 220 is provided because the signal sampled by the sampling unit 240 ′ of the second embodiment is the image signal VID, and the sampled image signal VID is supplied to each data line 6a as the data line signals X1 to Xn. It is. That is, in the first embodiment, since the sampling target of the sampling unit 240 is the image data D, the switch circuits SW1 to SWn may be operated with a small amplitude, but the sampling unit 240 ′ of the second embodiment It is necessary to sample the large-amplitude image signal VID by the switch elements SW1 ′ to SWn ′. This is because it is necessary to control the switch elements SW1 ′ to SWn ′ using the large amplitude sampling pulses SR1 to SRn.
[0072]
<2-3. Image processing circuit>
Next, the image processing circuit 400 ′ will be described. The image processing circuit 400 ′ of the second embodiment is the same as the image processing circuit 400 of the first embodiment, except that a variable delay circuit 470 ′ is used instead of the variable delay circuit 470. That is, the image processing circuit 400 ′ of the second embodiment includes a control unit CTL, and the configuration until the average signal Sh is generated is the same as that of the first embodiment.
[0073]
FIG. 9 is a block diagram showing the configuration of the variable delay circuit 470 ′ of the second embodiment. The variable delay circuit 470 ′ is different from the variable delay circuit 470 of the first embodiment shown in FIG. 4 in that a D / A converter 473 is used in place of the latch circuit 472 and from the input of the addition / subtraction circuit 483. This is a point excluding the offset voltage Va. The D / A converter 473 is configured to perform DA conversion in synchronization with both the rising edge and falling edge of the delayed X clock signal X ′.
[0074]
First, the D / A converter 473 is used instead of the latch circuit 472 because the liquid crystal panel AA of the second embodiment inputs image information as an analog signal.
[0075]
Next, the reason why the offset voltage Va is removed from the input of the addition / subtraction circuit 483 is as follows. In the first embodiment, the image data D to be supplied to each data line 6a is determined at the timing of the falling edge of each sampling pulse SR1 to SRn. For this reason, it is necessary to shift the phases of the image data D and the delayed X clock signal XCK ′ as a fixed amount by the 1/4 clock cycle time Tc using the offset voltage Va. On the other hand, in the second embodiment, the image signal VID is supplied to the data line 6a during the period in which the sampling pulses SR1 to SRn are active (high level). If the period in which the corresponding image signal VID is active does not match the period in which the sampling pulses SR1 to SRn are active, the image signal VID to be supplied to the adjacent data line 6a in the mismatch period is the data line 6a. Will be mixed. For this reason, in the present embodiment, the offset voltage Va is excluded in order to make the sampling pulse SRj corresponding to the jth data line 6a located in the center of the image display area A coincide with the active period of the image signal VID. It was.
[0076]
In the variable delay circuit 470 ′ shown in FIG. 9, the signal obtained by subtracting the output signal Sx of the low-pass filter from the average signal Sh by the addition / subtraction circuit 483 is supplied to the voltage controlled oscillator 484 as the error signal Sg, and its output A delayed X clock signal XCK ′ as a signal is fed back to the phase comparison circuit 481. Since the PLL circuit 480 operates so that the error signal Sg becomes “0”, the voltage value of the output signal Sx becomes equal to the voltage value of the average signal Sh. Here, the voltage value of the averaged signal Sh corresponds to the delay time Tj (= (T0 + Tn + 1) / 2) of the sampling pulse SRj with respect to the X clock signal XCK, as described in the first embodiment. Therefore, the delay time of the delayed X clock signal XCK ′ with respect to the X clock signal XCK can be made to coincide with Tj. As a result, the active period of the sampling pulse SRj coincides with the active period of the corresponding image signal VID.
[0077]
<1-6. Operation of Second Embodiment>
Next, the operation of the liquid crystal device according to the second embodiment will be described. FIG. 10 is a timing chart showing the relationship between the image signal and various signals of the data line driving circuit. However, in the image signal VID shown in the figure, the subscripts indicate the order in the horizontal scanning direction.
[0078]
As shown in this figure, the delayed X clock signal XCK ′ is delayed by Tj with respect to the X clock signal XCK, and the sampling pulse SRj is similarly delayed by Tj. Therefore, when the sampling pulse Srj becomes active (high level), the image signal VIDj is supplied to the j-th data line 6a. On the other hand, the sampling pulse SR1 is advanced with respect to the image signal VID1, and the phase of the sampling pulse SRn is delayed with respect to the image signal VIDn. That is, with the sampling pulse SRj as the center, the previous sampling pulse is advanced in phase, and the subsequent sampling pulses are delayed in phase. For this reason, in the sampling pulses SR1 to SRn and the image signals VID1 to VIDn, the image signal VID to be supplied to the adjacent data line 6a is mixed into the data line 6a in a period in which the active period does not match. . When the length of the mismatch period is long, a phenomenon called ghost appears in which an image shifted in time to an image to be originally displayed is thinly displayed.
[0079]
However, the length of the mismatch period is short at the center of the screen and is distributed so as to increase toward the left and right edges of the screen. Therefore, according to this liquid crystal device, the inconsistency period becomes longer at the right end of the screen and the ghost does not stand out. In addition, when a person looks at the display screen, he / she usually looks at the center of the screen and does not pay much attention to the left and right edges of the screen. For this reason, as described above, there is an advantage that a person does not feel image quality deterioration so much by adjusting the mismatch period to be the minimum at the center of the screen.
[0080]
<3. Example of LCD panel configuration>
Next, the overall configuration of the liquid crystal panel AA described in the first embodiment and the second embodiment will be described with reference to FIGS. 11 and 12. Here, FIG. 11 is a perspective view showing the configuration of the liquid crystal panel AA, and FIG. 12 is a sectional view taken along the line ZZ ′ in FIG.
[0081]
As shown in these figures, the liquid crystal panel AA includes an element substrate 101 such as glass or semiconductor on which pixel electrodes 9a are formed, and a transparent counter substrate 102 such as glass on which common electrodes 108 are formed. In addition, the sealing material 104 mixed with the spacer 103 is bonded so that the electrode forming surfaces face each other while maintaining a certain gap, and the liquid crystal 105 as an electro-optic material is sealed in the gap. Note that the sealant 104 is formed along the periphery of the counter substrate 102, but a part thereof is opened to enclose the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed, the opening is sealed with the sealing material 106.
[0082]
Here, on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104, the data line driving circuit 200 described above is formed to drive the data lines 114 extending in the Y direction. Yes. Further, a plurality of connection electrodes 107 are formed on one side, and various signals from the timing generation circuit 300 and the image signal processing circuit 400 are input. In addition, sampling pulses SR0 and SRn + 1 are output through the connection electrode 107.
[0083]
Further, two scanning line driving circuits 100 are formed on two sides adjacent to the one side, and the scanning line 3a extending in the X direction is driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line 112 does not cause a problem, the scanning line driving circuit 100 may be formed on only one side.
[0084]
On the other hand, the common electrode 108 of the counter substrate 102 is electrically connected to the element substrate 101 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 101. In addition, the counter substrate 102 is provided with, for example, a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel AA. A black matrix such as resin black in which carbon, titanium, or the like is dispersed in a photoresist is provided, and third, a backlight for irradiating the liquid crystal panel 100 with light is provided. Particularly in the case of color light modulation, a black matrix is provided on the counter substrate 102 without forming a color filter.
[0085]
In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film or the like that is rubbed in a predetermined direction, and a polarizing plate (not shown) corresponding to the alignment direction on each back side. Are provided respectively. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizing plate, and the like are not required. As a result, the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.
[0086]
In addition, instead of forming part or all of the peripheral circuits of the scanning line driving circuit 100 and the data line driving circuit 200 on the element substrate 101, driving mounted on a film using, for example, a TAB (Tape Automated Bonding) technique. The IC chip may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position of the element substrate 101, or the driving IC chip itself may be COG (Chip On Grass) technology. It is good also as a structure electrically and mechanically connected to the predetermined position of the element substrate 101 via an anisotropic conductive film.
[0087]
<4. Application examples of liquid crystal devices>
Next, the case where the liquid crystal device described in the first embodiment and the second embodiment is applied to various electronic devices will be described.
[0088]
<Part 1: Projector>
First, a projector using this liquid crystal device as a light valve will be described. FIG. 13 is a plan view showing a configuration example of the projector.
[0089]
As shown in this figure, a lamp unit 1102 made of a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.
[0090]
The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the above-described liquid crystal panel AA, and R, G, and B primary color image information (image data and image signals) supplied from an image signal processing circuit (not shown). Each is driven. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.
[0091]
Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.
[0092]
Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.
[0093]
<Part 2: Mobile computer>
Next, an example in which the above-described liquid crystal device is applied to a mobile personal computer will be described. FIG. 14 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1005 described above.
[0094]
<Part 3: Mobile phone>
Further, an example in which the above-described liquid crystal device is applied to a mobile phone will be described. FIG. 15 is a perspective view showing the configuration of this mobile phone. In the figure, a cellular phone 1300 includes a reflective liquid crystal panel 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal panel 100, a front light is provided on the front surface thereof as necessary.
[0095]
In addition to the electronic devices described with reference to FIGS. 13 to 15, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, videophones, POS terminals, devices with touch panels, etc. Needless to say, the present invention can be applied to these various electronic devices.
[0096]
<5. Modification>
(1) In each of the above-described embodiments and application examples, all or part of the image processing circuits 400 and 400 ′ may be built in the liquid crystal panel AA. In this case, a TFT is used as an active element constituting the image processing circuits 400 and 400 ′, and this is formed on the element substrate 101 by the same semiconductor process as the TFT used for the scanning line driving circuit 100 and the data line driving circuit 200. do it.
[0097]
(2) In each of the above-described embodiments, the image processing circuits 400 and 400 ′ and the data line driving circuit 200 have been described as separate ones. However, these may be combined to be regarded as a data line driving device. Of course.
[0098]
(3) In the first embodiment described above, the offset voltage Va may be a value that allows for the delay of the image data supply line. Similarly, in the second embodiment, an offset voltage Va that allows for delay of the image signal supply line may be supplied to the adjusting circuit.
[0099]
(4) In each of the above-described embodiments, the input image data Din is described as corresponding to one color, but may be corresponding to the three primary colors of RGB. In this case, for example, pixels may be repeatedly arranged in the order of R, G, and B in the X direction, and one sampling signal may be generated for a set of RGB pixels. Further, in order to lower the drive frequency of the data line, a plurality of data lines may be made into one block, and a sampling pulse may be generated for each block. In these cases, it is sufficient to generate two more sampling pulses than the number actually used for sampling the image signal. Then, the delay time of the central sampling pulse is calculated by feeding back the first sampling pulse and the last sampling pulse to the image processing circuit, and based on this, the input image data Din is delayed to generate the image data D. .
[0100]
【The invention's effect】
As described above, according to the present invention, the delay time of the sampling signal generated at the central timing in time among the sampling signals is detected, and the input image information is delayed by delay based on the detected delay time. Since the image information is generated, it is possible to automatically match the phase of the delayed image information and the sampling signal generated at the temporally central timing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal device according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a data line driving circuit 200 used in the embodiment.
FIG. 3 is a block diagram of an image processing circuit 400 used in the embodiment.
4 is a block diagram of a variable delay circuit 470 used in the image processing circuit 400. FIG.
FIG. 5 is a timing chart showing operations of the data line driving circuit and its peripheral circuits.
FIG. 6 is a timing chart showing the relationship between image data and various signals of a data line driving circuit.
FIG. 7 is a block diagram illustrating an overall configuration of a liquid crystal device according to a second embodiment.
FIG. 8 is a block diagram showing a configuration of a data line driving circuit used in the second embodiment.
FIG. 9 is a block diagram showing a configuration of a variable delay circuit 470 ′ of the second embodiment.
FIG. 10 is a timing chart showing a relationship between an image signal and various signals of a data line driving circuit.
FIG. 11 is a perspective view showing a configuration of a liquid crystal panel AA.
12 is a cross-sectional view taken along the line ZZ ′ in FIG.
FIG. 13 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which a liquid crystal device is applied.
FIG. 14 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which a liquid crystal device is applied.
FIG. 15 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which a liquid crystal device is applied.
[Explanation of symbols]
AA: Liquid crystal panel (electro-optic panel)
3a: Scanning line
6a: Data line
9a: Pixel electrode
50 …… TFT (switching element)
200: Data line driving circuit
210 ... X shift register (shift means)
220 …… Level shifter (shift means)
230 …… Buffer (shift means)
240 …… Sampling unit (sampling means)
250 …… First latch section
260 …… Second latch part
270 ... D / A converter (D / A converter)
400 …… Image processing circuit
CTL: Control unit (detection means, averaged signal generation means)
470, 470 '... variable delay circuit (delay means)
Din …… Input image data (input image information)
D …… Image data (delayed image information)
VID: Image signal (delayed image information)
DX ... X transfer start pulse (start pulse)
X1 to Xn: Data line signal
SR0 to SRn + 1 …… Sampling pulse (sampling signal)
XCK: X clock signal (input clock signal)
Sh …… Average signal

Claims (11)

Data of an electro-optical panel having a plurality of scanning lines, a plurality of data lines, a switching element arranged corresponding to the intersection of the scanning line and the data line, and a pixel electrode connected to the switching element A line driving method,
The start pulse is sequentially transferred according to the input clock signal,
Generate two more sampling signals than the number of signals actually used for sampling,
Generating an average signal indicating an average value of a first delay time corresponding to the first sampling signal and a second delay time corresponding to the last sampling signal, with the input clock signal as a reference;
Based on the averaged signal, delay input image information to generate delayed image information,
Based on the sampling signal excluding the first and last sampling signals of each sampling signal, the delayed image information is sampled,
A data line driving method for an electro-optical panel, wherein a data line signal for driving each data line is generated based on the sampled delayed image information, and each data line signal is supplied to the corresponding data line. The step of generating each sampling signal, the step of sampling the delayed image information, and the step of generating and supplying the data line signal to each data line are performed on the same substrate as the substrate on which the switching element is formed. ,
The method for driving a data line of an electro-optical panel according to claim 1, wherein the step of generating the average signal and the step of generating the delayed image information are performed on a substrate different from the substrate. Data of an electro-optical panel having a plurality of scanning lines, a plurality of data lines, a switching element arranged corresponding to the intersection of the scanning line and the data line, and a pixel electrode connected to the switching element A line drive device,
Shift means for sequentially transferring start pulses in accordance with an input clock signal and generating each sampling signal having a number two more than the number of signals actually used for sampling;
Averaged signal generating means for generating an averaged signal indicating an average value of the first delay time corresponding to the first sampling signal and the second delay time corresponding to the last sampling signal with the input clock signal as a reference; ,
Delay means for delaying input image information and generating delayed image information based on the averaged signal;
Sampling means for sampling the delayed image information based on a sampling signal excluding the first and last sampling signals among the sampling signals;
A data line signal generating means for generating a data line signal for driving each data line based on the sampled delayed image information and for supplying each data line signal to the corresponding data line; Data line driving device for optical panel. While providing the shift means, the sampling means, and the data line signal generation means on the same substrate as the substrate on which the switching element is formed,
4. The data line driving device for an electro-optical panel according to claim 3, wherein the averaged signal generating unit and the delay unit are provided on a substrate different from the substrate. The averaged signal generating means includes
A first logic circuit for outputting a pulse indicating a phase difference between the input clock signal and the first sampling signal;
A first integrating circuit for integrating the output pulses of the first logic circuit;
A second logic circuit for outputting a pulse indicating a phase difference between the input clock signal and the last sampling signal;
A second integrating circuit for integrating the output pulses of the second logic circuit;
The electric circuit according to claim 3, further comprising: an averaging circuit that calculates an average value of the output signal of the first integration circuit and the output signal of the second integration circuit and outputs the average value as the average signal. Data line driving device for optical panel. The delayed image information is image data in a digital signal format,
The data line signal generating means includes:
First latch means for latching image data supplied from the sampling means and converting the image data into dot sequential image data;
Second latch means for latching the dot sequential image data for each horizontal scanning period and converting it into line sequential image data;
The D / A conversion means for D / A converting the line sequential image data to generate the data line signal and supplying each data line signal to a corresponding data line. A data line driving device of the electro-optical panel described.   The delay means generates a timing at which a sampling signal generated at a central timing in time among the sampling signals switches from active to inactive at the center of a period in which image data corresponding to the sampling signal is active. The data line driving device for an electro-optical panel according to claim 6, wherein the image data is generated by delaying the input image information based on the averaged signal.   4. The delay image information is an image signal in an analog signal format, and the data line signal generation unit supplies the image signal supplied from the sampling unit to each data line. A data line driving device of the electro-optical panel described.   The delay means is based on the averaged signal so that an active period of a sampling signal generated at a central timing in time among the sampling signals coincides with an active period of an image signal corresponding to the sampling signal. 9. The data line driving device for an electro-optical panel according to claim 8, wherein the input image information is delayed to generate the image signal. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, a switching element disposed corresponding to an intersection of the scanning line and the data line, and a pixel electrode connected to the switching element;
A data line driving device according to any one of claims 3 to 9,
An electro-optical device comprising: a scanning line driving device that drives each of the scanning lines.   An electronic apparatus comprising the electro-optical device according to claim 10 as a display unit.

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