JP2003051575A - Method for forming half etched surface - Google Patents

Method for forming half etched surface

Info

Publication number
JP2003051575A
JP2003051575A JP2001239055A JP2001239055A JP2003051575A JP 2003051575 A JP2003051575 A JP 2003051575A JP 2001239055 A JP2001239055 A JP 2001239055A JP 2001239055 A JP2001239055 A JP 2001239055A JP 2003051575 A JP2003051575 A JP 2003051575A
Authority
JP
Japan
Prior art keywords
etched
lead
half etched
lead frame
punch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001239055A
Other languages
Japanese (ja)
Inventor
Yasunari Shimizu
康也 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP2001239055A priority Critical patent/JP2003051575A/en
Publication of JP2003051575A publication Critical patent/JP2003051575A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a novel method for inexpensively manufacturing a lead frame having no roundness in a sectional shape of half etched surface with high productivity. SOLUTION: The method for forming a half etched surface comprises the steps of press forming a half etched lead distal end by pressing to flatten the surface of the lead distal end, providing two or more holes having a relation of a high positional accuracy to a half etched part in the lead frame before pressing, positioning the lead by using the holes, and flattening the object half etched part with a punch to flatten the half etched part. In this case, the metal die has at least two or more pins for positioning a metal plate in the mold, and the punch assembled to match the pattern shape of the half etched part.

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、ハーフエッチ構造
を持つリードフレームやCSP製造工程の部材として使
われるハーフエッチング加工の施された金属材料等の表
面処理方法に関する。 【0002】 【従来の技術】図.1に示す様なインナーリード先端部
にハーフエッチ処理されたリードフレームがある。こう
したリードフレームは半導体装置の小型化がもたらした
ものであり、ハーフエッチ処理されたインナーリード先
端部と半導体素子とをワイヤーボンディングし、樹脂封
止することにより得られる半導体装置そのものの厚みを
減少させようとする目的と、板厚を薄くする事によるエ
ッチング特性を上げ、ファインピッチな製品を加工する
目的がある。 【0003】ところで、こうしたリードフレームを製造
する場合、インナーリード部を作成した後にインナーリ
ード先端部をハーフエッチングすると、インナーリード
先端部のハーフエッチング面が丸みを帯びざるを得な
い。また、インナーリード部の作成とハーフエッチング
を同時に行っても丸みを帯びる。この丸みが甚だしい場
合にはボンディングしたワイヤーとインナーリードとの
接合強度とが低くなり、信頼性の低い半導体装置しか得
られないと言う問題がある。 【0004】こうした問題を解決する手段として、最初
にハーフエッチ部分作成し、ハーフエッチング面にレジ
スト層を設け、ハーフエッチング面と反対の面からエッ
チングしてリード部を形成することが検討されている。
しかし、この方法では、最初のハーフエッチング部分を
再度レジストでカバーし、反対面よりエッチングすると
いう工程が増加するため、生産性が悪く、経済性に大き
な問題を残すものとなっている。 【0005】 【発明が解決しようとする課題】本発明は、ハーフエッ
チ面の断面形状に丸みを有しないリードフレームを生産
性良く、かつ安価に製造しうる新規な方法の提供を課題
とする。 【0006】 【課題を解決するための手段】上記課題を解決する本発
明は、ハーフエッチされたリード先端部をプレス金型に
よりプレス成形してリード先端部表面を平坦にするもの
であり、該プレス成形をする前にハーフエッチ部分との
間に高位置精度の関係にある2個以上の孔をリードフレ
ームに設けておき、これらの孔を用いて位置決めし、目
的のハーフエッチ部分をパンチで押し潰して平坦にする
ものであり、用いるプレス金型が、金型内に金属板の位
置決めとなる少なくとも2本以上のピンと、ハーフエッ
チ部分のパターン形状に合わせて組み込まれたパンチと
を具備しているものであることを特徴とするハーフエッ
チング面の成形方法である。 【0007】 【発明の実施の形態】本発明では、予めそのハーフエッ
チ部分との間に高位置精度の関係にある2個以上の孔を
エッチングやプレス加工で施しておき、その孔に金型の
ピンを通すことで位置決めを行ってから、目的のハーフ
エッチ部分をパンチで押し潰すことで、目的の所に平坦
な部分を作り出す。ここで、金属板の孔とハーフエッチ
部分の位置関係は、金型内のピンとパンチの位置関係と
同じ設計にすることで、目的の部分のみをパンチで押し
潰すことが可能となっている。 【0008】以下、図2を用いて説明する。ハーフエッ
チ構造を持ったリールまたはシート状に加工されたリー
ドフレーム1は金型3内に搬送され、リードフレーム1
のハーフエッチ部分2との間に高位置精度の関係にある
2個以上の孔4に金型3内のパイロットピン5を入れる
ことにより位置決めされる。金型3内には、リードフレ
ーム1の孔4とハーフエッチ部分2との位置と同じ関係
にあるパイロットピン5とパンチ6とがあり、パイロッ
トピン5で位置決め固定されたリードフレーム1はパン
チ6により目的のハーフエッチ部分2のみが押し潰され
る構造となっている。パンチ6はスプリング7、あるい
は下死点調整治具(図示せず。)などにより押し潰す強
さを調節できるようになっており、リードフレームの材
質や厚みなどを考慮して、必要な平坦度を確保すること
ができる。 【0009】また、図3に示すようなエレクトロフォー
ミングに用いられるハーフエッチ部分についての平坦化
に対しても本発明は有効であり、パンチ形状を合わせる
ことにより簡単にハーフエッチング部の平坦化ができ
る。 【0010】 【実施例】次に実施例を用いて本発明をさらに説明す
る。 (実施例1)素材金属として銅合金を用い、IC組み立て
時にワイヤーボンディングされるリード先端部分が、そ
の板厚の半分がハーフエッチングされており、ハーフエ
ッチング面が丸みを帯びている図1に示したようなリー
ドフレーを用いて試験を行った。上記リードフレームを
図2のような金型を有するプレス機に装入し、ハーフエ
ッチング面のみを押しつぶした。この前後のリード先端
部の断面を高精度な測長機で測定して求めた。この結果
を図4に示した。図4から解るように、ボンディング信
頼性を確保できる平坦な面が得られている。 【0011】 【発明の効果】本発明は前述のように、ハーフエッチン
グされ丸みを帯びたリード先端部を、リードフレームの
位置決め用の孔とハーフエッチ部分との位置と同じ関係
にある位置決めピンとパンチとを具備した金型を用いて
押し潰すことにより、2回エッチングなどの複雑な処理
を行うことなく、簡単、かつ安価にインナーリード先端
部の平坦性を向上させることができる。また、エレクト
ロフォーミングに用いられるハーフエッチ部分の平坦化
にも本発明は適用できる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment of a lead frame having a half-etch structure or a metal material subjected to a half-etching process used as a member in a CSP manufacturing process. About the method. [0002] FIG. As shown in FIG. 1, there is a lead frame which has been half-etched at the tip of the inner lead. Such a lead frame is the result of the miniaturization of the semiconductor device, and reduces the thickness of the semiconductor device itself obtained by wire-bonding the tip of the half-etched inner lead to the semiconductor element and sealing it with resin. The purpose is to increase the etching characteristics by reducing the thickness of the sheet, and to process a fine-pitch product. When manufacturing such a lead frame, if the tip of the inner lead is half-etched after the inner lead is formed, the half-etched surface of the tip of the inner lead must be rounded. Even if the inner lead portion is formed and half-etched at the same time, the inner lead portion is rounded. If the roundness is excessive, the bonding strength between the bonded wire and the inner lead becomes low, and there is a problem that only a semiconductor device with low reliability can be obtained. As means for solving such a problem, it has been studied to first form a half-etched portion, provide a resist layer on a half-etched surface, and form a lead portion by etching from a surface opposite to the half-etched surface. .
However, in this method, the number of steps of covering the first half-etched portion with the resist again and etching from the opposite surface is increased, so that the productivity is poor, and a major problem remains in economic efficiency. SUMMARY OF THE INVENTION An object of the present invention is to provide a novel method capable of manufacturing a lead frame having a rounded half-etched surface with no roundness with good productivity and at low cost. In order to solve the above-mentioned problems, the present invention is to press-mold a half-etched lead tip using a press die to flatten the surface of the lead tip. Before press forming, two or more holes that have a high positional accuracy relationship with the half-etched part are provided in the lead frame, positioning is performed using these holes, and the target half-etched part is punched. A press die to be crushed and flattened, the press die to be used is provided with at least two or more pins for positioning a metal plate in the die, and a punch incorporated according to a pattern shape of a half-etched portion. A method for forming a half-etched surface. In the present invention, two or more holes having a high positional accuracy with respect to a half-etched portion are formed in advance by etching or press working, and a die is formed in the hole. Then, the desired half-etched portion is crushed with a punch, and a flat portion is created at the desired location. Here, the positional relationship between the hole of the metal plate and the half-etched portion is designed to be the same as the positional relationship between the pin in the mold and the punch, so that only the target portion can be crushed by the punch. Hereinafter, description will be made with reference to FIG. A lead frame 1 processed into a reel or a sheet having a half-etch structure is conveyed into a mold 3 and the lead frame 1
The positioning is performed by inserting the pilot pin 5 in the mold 3 into two or more holes 4 having a high positional accuracy relationship with the half-etched portion 2 of FIG. The die 3 includes a pilot pin 5 and a punch 6 having the same relationship as the positions of the hole 4 of the lead frame 1 and the half-etched portion 2, and the lead frame 1 positioned and fixed by the pilot pin 5 has a punch 6 Thus, only the target half-etched portion 2 is crushed. The punch 6 can be adjusted in its crushing strength by a spring 7 or a bottom dead center adjusting jig (not shown), and the required flatness is determined in consideration of the material and thickness of the lead frame. Can be secured. The present invention is also effective for flattening a half-etched portion used for electroforming as shown in FIG. 3, and the half-etched portion can be easily flattened by adjusting the punch shape. . Next, the present invention will be further described with reference to examples. (Embodiment 1) FIG. 1 shows that a copper alloy is used as a material metal, and a lead end portion to be wire-bonded at the time of assembling an IC is half-etched in half of the plate thickness and a half-etched surface is rounded. The test was performed using such a lead frame. The lead frame was placed in a press having a mold as shown in FIG. 2, and only the half-etched surface was crushed. The cross-sections of the front and rear ends of the lead were measured by a high-precision length measuring machine. The result is shown in FIG. As can be seen from FIG. 4, a flat surface that can ensure bonding reliability is obtained. According to the present invention, as described above, a half-etched and rounded lead tip is provided with a positioning pin and a punch having the same relation as the positions of the positioning hole of the lead frame and the half-etched portion. The flatness of the tip of the inner lead can be easily and inexpensively improved without performing complicated processing such as etching twice by crushing using a mold having the above. The present invention is also applicable to flattening a half-etched portion used for electroforming.

【図面の簡単な説明】 【図1】ワイヤーボンディングされる部分にのみハーフ
エッチが施されているリードフレームとその断面形状を
示した図である。 【図2】本発明に用いる金型とその作動状況を示した図
である。 【図3】エレクトロフォーミングに使われる、ハーフエ
ッチが施された鋳型となる金属板を示した図である。 【図4】ハーフエッチされた面のパンチ加工前後のプロ
ファイル測定結果を示した図である。 【符号の説明】 1――リードフレーム 2――リード先端ハーフエッチ部 3――金型 4――孔 5――パイロットピン 6――パンチ 7――スプリング
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a lead frame in which a half-etch is applied only to a portion to be wire-bonded and a cross-sectional shape thereof. FIG. 2 is a view showing a mold used in the present invention and an operation state thereof. FIG. 3 is a diagram showing a metal plate serving as a half-etched mold used for electroforming. FIG. 4 is a diagram showing profile measurement results before and after punching of a half-etched surface. [Description of Signs] 1—Lead frame 2—Lead tip half-etched part 3—Mold 4—Hole 5—Pilot pin 6—Punch 7—Spring

Claims (1)

【特許請求の範囲】 【請求項1】ハーフエッチされたリード先端部をプレス
金型によりプレス成形してリード先端部表面を平坦にす
るものであり、該プレス成形をする前にハーフエッチ部
分との間に高位置精度の関係にある2個以上の孔をリー
ドフレームに設けておき、これらの孔を用いて位置決め
し、目的のハーフエッチ部分をパンチで押し潰して平坦
にするものであり、用いるプレス金型が、金型内に金属
板の位置決めとなる少なくとも2本以上のピンと、ハー
フエッチ部分のパターン形状に合わせて組み込まれたパ
ンチとを具備しているものであることを特徴とするハー
フエッチング面の成型方法。
Claims: 1. A half-etched lead tip is press-formed by a press die to flatten the surface of the lead tip, and the half-etched part is formed before the press-forming. In the lead frame, two or more holes having a high positional accuracy relationship are provided in the lead frame, positioning is performed using these holes, and the target half-etched portion is flattened by crushing with a punch. The press die to be used is provided with at least two or more pins for positioning the metal plate in the die, and a punch incorporated according to the pattern shape of the half-etched portion. Molding method for half-etched surface.
JP2001239055A 2001-08-07 2001-08-07 Method for forming half etched surface Pending JP2003051575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001239055A JP2003051575A (en) 2001-08-07 2001-08-07 Method for forming half etched surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001239055A JP2003051575A (en) 2001-08-07 2001-08-07 Method for forming half etched surface

Publications (1)

Publication Number Publication Date
JP2003051575A true JP2003051575A (en) 2003-02-21

Family

ID=19069871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001239055A Pending JP2003051575A (en) 2001-08-07 2001-08-07 Method for forming half etched surface

Country Status (1)

Country Link
JP (1) JP2003051575A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017017086A (en) * 2015-06-29 2017-01-19 Shマテリアル株式会社 Lead frame for mounting semiconductor device and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6248053A (en) * 1985-08-28 1987-03-02 Nec Corp Manufacture of lead frame for semiconductor device
JPH0832012A (en) * 1994-07-12 1996-02-02 Toppan Printing Co Ltd Lead frame and its manufacture
JPH08316392A (en) * 1995-05-16 1996-11-29 Dainippon Printing Co Ltd Lead frame and manufacture thereof
JPH0964260A (en) * 1995-08-30 1997-03-07 Hitachi Ltd Cutting molding die
JPH0982867A (en) * 1995-09-12 1997-03-28 Rohm Co Ltd Lead terminal forming device of electronic part

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6248053A (en) * 1985-08-28 1987-03-02 Nec Corp Manufacture of lead frame for semiconductor device
JPH0832012A (en) * 1994-07-12 1996-02-02 Toppan Printing Co Ltd Lead frame and its manufacture
JPH08316392A (en) * 1995-05-16 1996-11-29 Dainippon Printing Co Ltd Lead frame and manufacture thereof
JPH0964260A (en) * 1995-08-30 1997-03-07 Hitachi Ltd Cutting molding die
JPH0982867A (en) * 1995-09-12 1997-03-28 Rohm Co Ltd Lead terminal forming device of electronic part

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017017086A (en) * 2015-06-29 2017-01-19 Shマテリアル株式会社 Lead frame for mounting semiconductor device and method of manufacturing the same

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