JP2003046879A - Signal transmission circuit, solid-state imaging device, camera and liquid crystal display unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip area by reducing the number of pulses supplied from the outside, in a signal transmission circuit which is used in an MOS type solid-state imaging device and a liquid crystal display unit. SOLUTION: This signal transmission circuit is provided with a plurality of input parts 62, 63 corresponding to one shift register 61 from among a plurality of shift registers for supplying voltage pulses necessary for a light sensitive region. One start pulse VST1 is supplied in common to the input parts. A plurality of driving pulses V1 and V2 different in timing are supplied to the input parts 62 and 63, respectively. The one shift register 61 is made to start at different timing by each timing of a plurality of the driving pulses to the start pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit which can be used in a liquid crystal display or a shift register for driving a MOS type solid-state image pickup device and can be driven at a low voltage.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a configuration example of a conventional MOS image sensor. In FIG. 9, the photosensitive region 5 is configured by two-dimensionally arranging the unit pixels including the photodiode 1, the transfer transistor 2, the reset transistor 3, and the amplification transistor 4. 6 is a normal drive vertical shift register (S / R1) for selecting pixels in the column direction, 7 is a vertical shift register for electronic shutter (S / R2), 8 is a horizontal shift register for selecting pixels in the row direction, and 9 is , Normal drive vertical shift register 6,
This is a timing pulse generation circuit that supplies necessary pulses to the vertical shift register 7 for electronic shutter and the horizontal shift register 8.

FIG. 10 shows the normal drive vertical shift register 6 and the electronic shutter vertical shift register 7 shown in FIG.
3 is a schematic configuration diagram showing the input / output relationship of FIG. As shown in FIG. 10, the drive pulses V1, V2 and the start pulse VST1 are supplied to the normal drive vertical shift register 6, and the drive pulses V1, V2 and the start pulse VST2 are supplied to the electronic shutter vertical shift register 7. Supplied.

FIG. 11 is an internal circuit diagram of a normal drive vertical shift register 6 and an electronic shutter vertical shift register 7 which are dynamic logic type using n-type MOS transistors. In FIG. 11, when the start pulse VST1 is input to the drain of the transistor M1 of the normal drive vertical shift register 6 and at the same time the drive pulse V2 enters the gate electrode of the transistor M1, the normal drive vertical shift register 6 shifts. To start. The electronic shutter vertical shift register 7 has the same configuration as the normal drive vertical shift register 6, and when the start pulse VST2 is input to the drain of the transistor M2 and at the same time the drive pulse V2 enters the gate electrode, The electronic shutter vertical shift register 7 starts the shift operation.

FIG. 12 is a timing chart of the drive pulse V2, start pulses VST1 and VST2. As shown in FIG. 12, a normal drive vertical shift register 6 is provided.
In the time period T1, both the start pulse VST1 and the drive pulse V2 become “High” level, the voltage level of the start pulse VST1 is stored in the first stage capacitor C1 through the transistor M1, and the normal drive vertical shift register 6 is started. To do. After the time period T1, the drive pulse V2 is set to the "Low" level before the start pulse VST1 is set to the "Low" level, whereby the electric charge stored in the first-stage capacitor C1 is held.

Similarly, in the electronic shutter vertical shift register 7, both the start pulse VST2 and the drive pulse V2 become "High" level in the time period T2, and the voltage level of the start pulse VST2 becomes the transistor M2.
It is stored in the capacitor C2 of the first stage through the, and the vertical shift register 7 for the electronic shutter starts. After this time period T2, the start pulse VST2 is "Low".
By setting the drive pulse V2 to the “Low” level before reaching the level, the electric charge stored in the first-stage capacitor C2 is held.

[0007]

As described above, the conventional M
The OS-type image sensor requires two types, a normal drive vertical shift register (S / R1) 6 and an electronic shutter vertical shift register (S / R2) 7, for normal drive and electronic shutter drive, respectively. Although the drive pulses V1 and V2 are commonly supplied to the two shift registers, the start pulses VST1 and VST2 must be supplied separately for the start pulse because the start times of the shift registers are different.

However, in order to reduce the chip area, it is essential to reduce the number of circuits and the number of pulses. In particular, when the timing pulse generating circuit 9 is not provided in the MOS image sensor, the number of terminals for supplying pulses from the outside increases, so that the number of pulses can be reduced.
It is essential for reducing the chip area.

The present invention has been made in view of the above points, and an object thereof is to provide a solid-state imaging device in which the chip area is reduced by reducing the number of pulses supplied from the outside. .

[0010]

In order to achieve the above object, in the first signal transmission circuit according to the present invention, one start pulse is provided to at least two shift registers among a plurality of shift registers. A plurality of drive pulses that are commonly supplied and have different timings are supplied, and at least two shift registers are started at different timings according to the timings of the plurality of drive pulses with respect to the start pulse.

In order to achieve the above object, in the second signal transmission circuit according to the present invention, at least two input sections are provided for one shift register, and one start common to each input section is provided. Each of the plurality of drive pulses having different timings from the pulse is supplied, and one shift register is started at different timings at each timing of the plurality of drive pulses with respect to the start pulse.

In the first signal transmission circuit, each of the at least two shift registers includes a transistor to which a start pulse is supplied to the source or the drain and a corresponding drive pulse of the plurality of drive pulses is supplied to the gate. Is preferred.

In the second signal transmission circuit, each of the at least two input sections includes a transistor to which a start pulse is supplied to the source or the drain and a corresponding drive pulse of the plurality of drive pulses is supplied to the gate. Is preferred.

In the case of the above structure, the transistor is an n-type MO.
It is an S-transistor, and the falling timing of the start pulse is preferably later than the falling timing of the drive pulse, or the transistor is a p-type MOS.
It is a transistor, and the rising timing of the start pulse is preferably later than the rising timing of the drive pulse.

Further, in the first signal transmission circuit, each of the at least two shift registers is a transistor in which a start pulse is supplied to the gate and a corresponding drive pulse of the plurality of drive pulses is supplied to the source or the drain. It is preferable to provide.

In the second signal transmission circuit, each of the at least two input units is a transistor in which a start pulse is supplied to the gate and a corresponding drive pulse of the plurality of drive pulses is supplied to the source or the drain. It is preferable to provide.

In the case of the above structure, the transistor is an n-type MO.
It is an S transistor, and the falling timing of the start pulse is preferably earlier than the falling timing of the drive pulse, or the transistor is a p-type MOS.
It is a transistor, and the rising timing of the start pulse is preferably earlier than the rising timing of the drive pulse.

According to the configuration of the first signal transmission circuit, the pulse timing for individually starting a plurality of shift registers at different timings is provided in one start pulse. As a result, a large number of shift registers can be collectively managed, and the number of circuits that generate a plurality of start pulses can be reduced. In addition, the first signal transmission circuit is an MO that does not include a timing pulse generation circuit.
When applied to an S-type solid-state imaging device, a camera using the same, and a liquid crystal display device, the number of start pulses supplied from the outside can be reduced, and thus the number of terminals of an external package can be reduced.

According to the configuration of the second signal transmission circuit, the pulse timing for starting a plurality of drives at different timings is provided in one start pulse. As a result, it is possible to collectively manage a plurality of input sections and reduce the number of circuits that generate a plurality of start pulses. Further, when the second signal transmission circuit is applied to a MOS type solid-state image pickup device having no built-in timing pulse generation circuit, a camera using the same, and a liquid crystal display device, the number of start pulses supplied from the outside can be reduced. Therefore, the number of terminals of the external package can be reduced.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the case where the signal transmission circuit according to the present invention is applied to a MOS type solid-state imaging device will be described as an example.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is an overall configuration diagram of a normal drive vertical shift register (S / R1) 16 and an electronic shutter vertical shift register (S / R2) 17 in the MOS solid-state imaging device according to the embodiment. In FIG. 1, each shift register has two
It is driven by three pulses of one drive pulse V1, V2 and one start pulse VST1, and the start pulse VST1 is commonly used by two shift registers.

FIG. 2 is an internal circuit diagram of the normal drive vertical shift register 16 and the electronic shutter vertical shift register 17 which are dynamic logic type using n-type MOS transistors. In FIG. 2, the normal driving vertical shift register 16 has a start pulse VST1.
And the drive pulse V1 are both at the "High" level,
Through the transistor M1, the capacitor C1 is connected to “High
A voltage of "h" level is applied to start the shift operation. In the vertical shift register 17 for electronic shutter, both the start pulse VST1 and the drive pulse V2 are “High”.
During the "h" level period, a "High" level voltage is applied to the capacitor C2 through the transistor M2 to start the shift operation.

FIG. 3 is a timing chart of the drive pulses V1 and V2 and the start pulse VST1. Figure 3
As shown in, in the normal drive vertical shift register 6,
In the time period T1, the start pulse VST1 and the drive pulse V1 both become “High” level, the voltage level of the start pulse VST1 is stored in the first stage capacitor C1 through the transistor M1, and the shift operation is started. Immediately after this time period T1, the drive pulse V1 is set to the “Low” level before the start pulse VST1 is set to the “Low” level, so that the capacitor C
The "High" level charge stored in 1 is held, and the dynamic logic operates.

Similarly, in the vertical shift register 17 for electronic shutter, the start pulse VST1 is generated in the time period T2.
The drive pulse V2 and the drive pulse V2 both become "High" level, the voltage level of the start pulse VST1 is stored in the first stage capacitor C2 through the transistor M2, and the shift operation is started. Immediately after this time period T2, the drive pulse V2 is set to the “Low” level before the start pulse VST1 is set to the “Low” level, whereby the “High” level charge stored in the capacitor C2 is held, The dynamic logic will operate.

Thus, in each shift register,
The drive pulses V1 and V2 applied to the respective gates of the first stage transistors M1 and M2 to which the start pulse VST1 is applied to the drain are configured to be different, and one start pulse VST1 includes a plurality of drive pulses at different times. The start time of each shift register can be set differently by providing the pulse timing which can start the shift register individually.

Therefore, the normal drive vertical shift register 16 and the electronic shutter vertical shift register 17 are provided.
In driving, the drive pulses V1 and V2 are commonly used, and the start pulse VST1 can be commonly used. As a result, one start pulse VST1 collectively manages a large number of shift registers, and it is possible to reduce the number of circuits that generate a plurality of start pulses and reduce the chip area. Further, in the MOS type solid-state image pickup device in which the timing pulse generation circuit is not built in, the number of start pulses supplied from the outside can be reduced, so that the number of terminals of the external package can be reduced.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
N-type M in the MOS solid-state imaging device according to the embodiment
FIG. 3 is an internal circuit diagram of a normal drive vertical shift register 16 and an electronic shutter vertical shift register 17, which are dynamic logic type using OS transistors. The present embodiment differs from the first embodiment in that in each shift register, a start pulse is commonly supplied to the gates of the transistors M1 and M2 in the first stage, and the drains of the transistors M1 and M2 in the first stage are driven at different timings. The pulse is at the point where V1 and V2 are supplied.

The operation of each shift register thus configured will be described with reference to the timing chart of FIG.

In the normal drive vertical shift register 16, both the start pulse VST1 and the drive pulse V1 become "High" in the time period T1, and the drive pulse V1 becomes "H".
The "high" level voltage is stored in the first-stage capacitor C1 through the transistor M1 to start the shift operation. Immediately after this time period T1, the drive pulse V
Start pulse VS before 1 goes to "Low" level
By setting T1 to "Low" level, the capacitor C1
The "High" level electric charge stored in is held, and the dynamic logic operates.

Similarly, in the vertical shift register 17 for electronic shutter, both the start pulse VST1 and the drive pulse V2 become "High" level in the time period T2,
The "High" level voltage of the drive pulse V2 is stored in the first-stage capacitor C2 through the transistor M2, and the shift operation starts. Immediately after this time period T2, before the drive pulse V2 becomes the “Low” level,
By setting the start pulse VST1 to the “Low” level, the “High” level charge stored in the capacitor C2 is held, and the dynamic logic operates.

Thus, in each shift register,
The drive pulses V1 and V2 applied to the drains of the transistors M1 and M2 in the first stage, to which the start pulse VST1 is applied to the gates, are different from each other, and one start pulse VST1 includes a plurality of drive pulses at different times. The start time of each shift register can be set differently by providing the pulse timing which can start the shift register individually.

Therefore, the normal drive vertical shift register 16 and the electronic shutter vertical shift register 17 are provided.
In driving, the drive pulses V1 and V2 are commonly used, and the start pulse VST1 can be commonly used. As a result, one start pulse VST1 collectively manages a large number of shift registers, and the number of circuits that generate a plurality of start pulses can be reduced, so that the chip area can be reduced. Further, in the MOS type solid-state image pickup device in which the timing pulse generation circuit is not built in, the number of start pulses supplied from the outside can be reduced, so that the number of terminals of the external package can be reduced.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
Shift register 6 for both normal drive and electronic shutter drive in the MOS solid-state imaging device according to the embodiment
1 is an overall configuration diagram of 1. The shift register 61 has two drive pulses V1 and V2 and one start pulse VS.
Driven by 3 pulses of T1, start pulse VST
1 is commonly used by the two input units (IN-1, IN-2) 62, 63.

FIG. 7 shows a shift register 61 composed of a dynamic logic type using n-type MOS transistors.
3 is an internal circuit diagram of FIG. In FIG. 7, the input unit 62 has a start pulse VST for the shift register 61 for normal driving.
N has a role of generating N, and the input unit 63 uses the start pulse VS of the shift register 61 for driving the electronic shutter.
It has a role to generate TS.

In the input section 62, the start pulse VST1
And the drive pulse V1 are both at the "High" level,
Capacitor C1 is connected to "High" through transistor M1.
The "h" level voltage is applied, and the shift register 61 is started for normal driving. Further, in the input section 63, both the start pulse VST1 and the drive pulse V2 are “High”.
During the "h" level period, a "High" level voltage is applied to the capacitor C2 through the transistor M2, and the shift register 61 for driving the electronic shutter is started. The timing relationship between the drive pulses V1 and V2 and the start pulse VST1 is as shown in the timing chart of FIG.

As described above, in each input section, the transistor M to which the start pulse VST1 is applied to the drain is connected.
Drive pulse V applied to the respective gates of 1 and M2
1 and V2 are set differently, and the start time of each input section is set to be different by providing pulse timings for individually starting a plurality of shift registers at different times in one start pulse VST1. it can.

Therefore, the common shift register can be driven during the normal driving and the electronic shutter driving, and the start pulse VS can be used for driving the input sections 62 and 63.
T1 can also be commonly used. As a result, the number of shift registers and the common start pulse can reduce the number of circuits that generate multiple start pulses.
The chip area can be reduced. Further, in the MOS type solid-state image pickup device in which the timing pulse generation circuit is not built in, the number of start pulses supplied from the outside can be reduced, so that the number of terminals of the external package can be reduced.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
N-type M in the MOS solid-state imaging device according to the embodiment
FIG. 7 is an internal circuit diagram of a shift register 61 configured by a dynamic logic type using OS transistors for both normal drive and electronic shutter drive. This embodiment is different from the third embodiment in that the transistor M is provided in each input section.
The start pulse is commonly supplied to the gates of 1 and M2,
The driving pulses V1 and V2 having different timings are supplied to the drains of the transistors M1 and M2, respectively. Since the timing relationship between the drive pulses V1 and V2 and the start pulse VST1 is as shown in the timing chart of FIG. 5, the description of the operation is omitted.

As described above, in each of the input sections 62 and 63, the drive pulses V1 and V2 applied to the drains of the transistors M1 and M2 to which the start pulse VST1 is applied to the gate electrodes are made different. By providing pulse timings for individually starting a plurality of shift registers at different times in one start pulse VST1, the start time of each input section can be set differently.

Therefore, the common shift register can be driven during the standard driving and the electronic shutter driving, and the start pulse VS can be used for driving the input sections 62 and 63.
T1 can also be commonly used. As a result, the number of shift registers and the common start pulse can reduce the number of circuits that generate multiple start pulses.
The chip area can be reduced. Further, in the MOS type solid-state image pickup device in which the timing pulse generation circuit is not built in, the number of start pulses supplied from the outside can be reduced, so that the number of terminals of the external package can be reduced.

In the first to fourth embodiments of the present invention, the case where the two drive pulses V1 and V2 are used has been described as an example. However, even when the drive pulse is three or more, the shift register is used. If the number of drive pulses is large, the effect of reducing the number of circuit sections that generate a plurality of start pulses and reducing the number of terminals is further increased.

Further, in the first to fourth embodiments of the present invention, the vertical shift register 6 and the electronic shutter vertical shift register 7 are constructed by using n-type MOS transistors, but by using p-type MOS transistors. Even if it comprises, the same effect is produced.

Further, in the first to fourth embodiments of the present invention, the configuration example of the shift register for selecting the vertical row of the solid-state image pickup device is shown. However, in the shift register for selecting the horizontal address of the solid-state image pickup device. Can also be used.
Further, in a liquid crystal display device or the like, the same effect can be realized also as a shift register that determines addresses in the horizontal direction and the vertical direction.

[0044]

As described above, according to the present invention,
The number of circuits that generate a plurality of start pulses can be reduced, and the chip area can be reduced. Further, the signal transmission circuit of the present invention includes a MOS solid-state imaging device in which a timing pulse generation circuit is not built in, and a camera using the same.
When applied to a liquid crystal display device, the number of start pulses supplied from the outside can be reduced, so that the number of input terminals of an external package can be reduced. By this, MO
The S-type solid-state imaging device can be downsized, which is extremely useful in industry.

[Brief description of drawings]

FIG. 1 is a vertical shift register for normal driving (S / S) in a MOS type solid-state imaging device according to a first embodiment of the present invention.
R1) 16 and vertical shift register for electronic shutter (S / R2) 17

FIG. 2 is a vertical drive shift register (S / S) for normal driving in the MOS type solid-state imaging device according to the first embodiment of the present invention.
R1) 16 and electronic shutter vertical shift register (S / R2) 17 internal circuit diagram

FIG. 3 is a timing chart of pulses supplied to each shift register in FIG.

FIG. 4 is a vertical drive shift register (S / S) for normal driving in a MOS type solid-state imaging device according to a second embodiment of the present invention.
R1) 16 and electronic shutter vertical shift register (S / R2) 17 internal circuit diagram

5 is a timing chart of pulses supplied to each shift register in FIG.

FIG. 6 is an overall configuration diagram of a shift register 61 for both normal drive and electronic shutter drive in a MOS solid-state imaging device according to a third embodiment of the present invention.

FIG. 7 is an internal circuit diagram of a shift register 61 for both normal drive and electronic shutter drive in a MOS type solid-state imaging device according to a third embodiment of the present invention.

FIG. 8 is an internal circuit diagram of a shift register 61 for both normal drive and electronic shutter drive in a MOS type solid-state imaging device according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a configuration example of a conventional MOS image sensor.

FIG. 10 is an overall configuration diagram of a conventional normal drive vertical shift register 6 and an electronic shutter vertical shift register 7.

FIG. 11 is an internal circuit diagram of a conventional normal drive vertical shift register 6 and a conventional electronic shutter vertical shift register 7.

FIG. 12 is a timing chart of pulses supplied to each shift register in FIG.

[Explanation of symbols]

1 Photodiode 2 Transfer Transistor 3 Reset Transistor 4 Amplifying Transistor 5 Photosensitive Area 6, 16 Normal Drive Vertical Shift Register 7, 17 Electronic Shutter Vertical Shift Register 8 Horizontal Shift Register 9 Timing Pulse Generation Circuit 61 Both Normal Drive and Electronic Shutter Drive Shift register 62, 63 input section

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623H 3/36 3/36 H01L 27/146 H01L 27/14 A F term (Reference) 2H093 NA16 NA44 NB23 NC22 NC33 ND42 4M118 AA10 AB01 BA14 CA02 FA06 FA21 FA50 GA10 5C006 BC03 BC12 BF03 BF34 EB05 FA16 FA41 5C024 CX54 CY16 GX04 GY31 HX02 HX40 5C080 AA10 BB05 DD22 DD25 JJ04 JJ04

Claims (13)

[Claims] 1. A start pulse is commonly supplied to at least two shift registers of a plurality of shift registers, and a plurality of drive pulses having different timings are supplied to each of the shift registers. A signal transmission circuit, wherein the at least two shift registers are started at different timings at respective timings of a plurality of drive pulses. 2. A shift register is provided with at least two input parts, and one start pulse common to each input part and a plurality of drive pulses with different timings are supplied to each shift register. The signal transmission circuit is characterized in that the one shift register is started at different timings according to respective timings of the plurality of drive pulses with respect to. 3. Each of the at least two shift registers comprises a transistor to which the start pulse is supplied to a source or a drain and a corresponding drive pulse of the plurality of drive pulses is supplied to a gate. The signal transmission circuit according to claim 1. 4. Each of the at least two inputs is
3. The signal transmission circuit according to claim 2, further comprising a transistor in which the start pulse is supplied to a source or a drain and a corresponding drive pulse among the plurality of drive pulses is supplied to a gate. 5. The signal transmission circuit according to claim 3, wherein the transistor is an n-type MOS transistor, and the fall timing of the start pulse is later than the fall timing of the drive pulse. 6. The signal transmission circuit according to claim 3, wherein the transistor is a p-type MOS transistor, and the rising timing of the start pulse is later than the rising timing of the drive pulse. 7. The start pulse is supplied to a gate of each of the at least two shift registers,
The signal transmission circuit according to claim 1, further comprising a transistor whose corresponding drive pulse is supplied to a source or a drain of the plurality of drive pulses. 8. Each of said at least two inputs is
3. The signal transmission circuit according to claim 2, further comprising a transistor in which the start pulse is supplied to a gate and a corresponding drive pulse among the plurality of drive pulses is supplied to a source or a drain. 9. The signal transmission circuit according to claim 7, wherein the transistor is an n-type MOS transistor, and the fall timing of the start pulse is earlier than the fall timing of the drive pulse. 10. The signal transmission circuit according to claim 7, wherein the transistor is a p-type MOS transistor, and the rising timing of the start pulse is earlier than the rising timing of the drive pulse. 11. A solid-state imaging device using the signal transmission circuit according to claim 1. Description: 12. A camera using the solid-state imaging device according to claim 11. 13. A liquid crystal display device using the signal transmission circuit according to claim 1. Description: