JP2002335455A - Solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a MOS type sensor including a floating diffusion (FD) amplifier in each pixel. SOLUTION: Drain regions (regions for supplying a pulse voltage to FD portions through reset transistors 3) of unit pixels are connected to different drain lines row by row, so as to selectively supply a power pulse to each row. The power pulse is set to a high level potential at least during a period when signal charge stored in the FD portion is reset and a period when the signal charge stored in the FD portion is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type solid-state imaging device used for a digital camera or the like.

[0002]

2. Description of the Related Art FIG. 17 shows an example of a conventional solid-state imaging device composed of MOS transistors. This solid-state imaging device includes a plurality of semiconductor devices each including a photodiode (PD) 1, a readout transistor 2, a floating diffusion (FD) unit, a reset transistor 3, a detection transistor 4, and an address transistor 5 on a semiconductor substrate. A solid-state imaging device provided with a photosensitive region 14 in which amplifying unit pixels are two-dimensionally arranged, further comprising a signal line 6, a drain line 7, a readout gate line 8, a reset gate line 9, an address gate line 10, a pixel It comprises a vertical shift register 12 for selecting a row, a horizontal shift register 13 for selecting a pixel column, and a timing generation circuit 11 for supplying necessary pulses to the shift registers 12 and 13.

The signal charge photoelectrically converted by the PD 1 is read out by the readout transistor 2 to an FD section which is an accumulation area for storing the signal charge. The potential of the FD section is determined by the amount of charge read to the FD section, the gate voltage of the detection transistor 4 changes, and a signal voltage is extracted to the signal line 6 on condition that the address transistor 5 is selected. It is.

[0004]

According to the prior art shown in FIG. 17, all of the plurality of amplifying unit pixels arranged two-dimensionally, despite the fact that a signal voltage is taken out to the signal line 6 for each row. At the same time, a power pulse is supplied via the vertical drain line 7. Therefore, there is a problem that power consumption is large.

An object of the present invention is to reduce power consumption in a solid-state imaging device.

[0006]

In order to achieve the above object, a solid-state imaging device according to the present invention comprises a drain region of a plurality of amplifying unit pixels (for supplying a pulse voltage to an FD section via a reset transistor). Region) is connected to a different drain line for each row. With this configuration, a power pulse can be selectively supplied for each row, so that power consumption is reduced. In addition, at least during the period of resetting the signal charge in the storage region and the period of detecting the signal charge in the storage region, the potential of the drain line is set to a high level.
The drain line is pulse-driven so as to be set to the H level potential. That is, since the drain line is driven only during a necessary period, power consumption is further reduced.

Further, if the potential of the drain line is set to the HIGH level potential while the read transistor is on, the reverse flow of charges to the photoelectric conversion region (PD) due to the LOW level potential of the drain line No worries.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described.

FIG. 1 shows an example of the configuration of an amplification type unit pixel in a solid-state imaging device according to the present invention. In FIG. 1, 1 is a photodiode (PD), 2 is a read transistor, FD is a floating diffusion portion,
3 is a reset transistor, 4 is a detection transistor, 6
Is a signal line, 7 is a drain line (VDD), 15 is an amplifying unit pixel, 16 is a gate line that performs both reading and resetting,
17 is an F connecting the FD section and the gate of the detection transistor 4
D wiring. Gate line 1 for both reading and reset
6 is connected to the gate of the readout transistor 2 of the pixel in the Nth row and the gate of the reset transistor 3 of the pixel in the (N + 1) th row, where N is an integer. The detection transistor 4 is connected to a different signal line 6 for each column. Further, different VDD power supply pulses are applied to the horizontal drain lines 7 for each row.

According to FIG. 1, the configuration of each unit pixel 15 is as follows.
One vertical line (signal line 6), two horizontal lines (drain line 7, and gate line 1 serving as both reading and resetting)
6) and three transistors (read transistor 2, reset transistor 3, and detection transistor 4).

FIG. 2 shows a configuration example of the vertical shift register 12. Vin, T1 and T2 are timing pulses provided from the timing generation circuit 11. A capacitor 18 is provided at each stage of the shift register, and Sig1, Sig2, and Sig3 are outputs of each stage of the shift register.

FIG. 3 shows an example of the configuration of a drive circuit for driving the amplifying unit pixel 15 of FIG. 3, reference numeral 20 denotes the N-th stage of the vertical shift register 12, 21 denotes the (N + 1) -th stage of the vertical shift register 12, 22 denotes a charge readout pulse generation circuit, 23 denotes a reset pulse generation circuit, 24 denotes an OR circuit, and 25 denotes This is a VDD horizontal wiring power supply circuit. The charge read pulse generation circuit 22 is a circuit for generating an AND signal between the N-th output SigN of the vertical shift register 12 and a conventional read pulse. The reset pulse generation circuit 23 is a circuit for generating an AND signal between the (N + 1) th stage output Sig (N + 1) of the vertical shift register 12 and a conventional reset pulse. O
The R circuit 24 is a circuit for supplying an OR signal of the output of the charge readout pulse generation circuit 22 and the output of the reset pulse generation circuit 23 to the gate line 16. The VDD horizontal wiring power supply circuit 25 is a circuit for supplying an AND signal between the N-th output SigN of the vertical shift register 12 and a conventional power supply pulse to the drain line 7.

FIG. 4 is a timing chart for explaining the operation of the drive circuit of FIG. “FD2” in FIG.
“Potential” indicates the potential of the FD section in the amplification type unit pixel (first pixel) 15 in FIG. FIG. 5A is a diagram showing a relative position of each potential in the first pixel, and FIGS. 5B to 5G are potential diagrams of the same pixel accompanying the operation of the driving circuit in FIG. It is. 5 (b) to 5
Timings t1 to t6 in (g) respectively correspond to timings t1 to t6 in FIG. Here, when the second pixel adjacent to the first pixel is reset, the LOW level potential of the drain line 7 of the first pixel is equal to the PD level of the first pixel.
The potential is set higher than the potential depth of 1. Also, the first
When a LOW level voltage is applied to the gate of the reset transistor 3 of the pixel, the potential below the gate is set to a potential higher than the LOW level potential of the drain line 7. Therefore, even when a pulse is applied to the readout transistor 2 of the first pixel when the second pixel is reset, unnecessary charges of the PD1 in the first pixel are efficiently discarded as shown in FIG. FD
Backflow of charges from the section to PD1 is prevented. In addition, the detection transistor 4 of the first pixel in a situation other than that shown in FIG.
LOW level voltage applied to the gate of the readout transistor 2 of the same pixel so that the off state of
The voltage is set to be lower than the LOW level voltage applied to the gate of the reset transistor 3 of the same pixel.

In this case, the potential of the drain line 7 is set to HIGH during the period in which the signal charges read from the PD 1 are stored in the FD portion and at least one of the periods in which the signal charges in the FD portion are reset. Must be set to level potential. When the unnecessary charges obtained by the PD1 are discarded for realizing the electronic shutter function, the period during which the unnecessary charges read from the PD1 are stored in the FD section and the FD
The potential of the drain line 7 may be set to the HIGH level potential during the period in which unnecessary charges of the unit are reset. However,
In the case where the unnecessary charges read from the PD 1 to the FD section are immediately reset, the drain line 7 is turned on while the read transistor 2 and the reset transistor 3 are simultaneously turned on.
May be set to a HIGH level potential. In order to realize the interlaced display, in order to detect signal charges of two or more pixels adjacent to each other in the column direction, the potentials of the drain lines 7 of two or more rows are set to HIG within one horizontal blanking period.
It is configured so that it can be set to the H level potential.

Note that, when the second pixel is reset, the LOW level potential of the drain line 7 of the first pixel is set to a potential lower than the potential depth of PD1 of the first pixel, and
When a LOW level voltage is applied to the gate of the reset transistor 3 of the pixel, the potential under the gate may be set to a potential higher than the LOW level potential of the drain line 7. Accordingly, when a pulse is given to the readout transistor 2 of the first pixel at the time of resetting the second pixel, the LO of VDD is reduced to prevent a residual image.
A so-called "priming effect", in which the W level potential is used as the reference potential of the PD, can be exhibited.

FIG. 6 shows a modification of the operation shown in FIG.
5A to FIG. 5G correspond to FIG.
(G) shows a modified example. 6 and 7
As shown in (a) to (g) of FIG. 7, even if the difference between the LOW level potential of VDD and the potential of PD1 is increased, P
The backflow of the electric charge to D1 can be prevented. In this case, the read transistor 2 and the reset transistor 3
And the LOW level voltage applied to each gate can be made the same, and the manufacturing process can be simplified.

FIG. 8 shows another example of the configuration of a drive circuit for driving the amplifying unit pixel of FIG. In FIG. 8, reference numeral 30 denotes a first power supply pulse generation circuit, 31 denotes a second power supply pulse generation circuit, and 32 denotes a VDD horizontal wiring power supply OR circuit. The first power supply pulse generation circuit 30 is a circuit for generating an AND signal between the N-th output SigN of the vertical shift register 12 and the first power supply pulse in the first period. The second power supply pulse generating circuit 31 generates an AND signal between the (N + 1) -th stage output Sig (N + 1) of the vertical shift register 12 and the second power supply pulse in a second period following the first period. Circuit. VDD
The horizontal wiring power supply OR circuit 32 is a circuit for supplying an OR signal of the output of the first power supply pulse generation circuit 30 and the output of the second power supply pulse generation circuit 31 to the drain line 7.
The circuit configuration for driving the gate line 16 is the same as that in FIG.

FIG. 9 is a timing chart for explaining the operation of the drive circuit of FIG. "FD2" in FIG.
“Potential” indicates the potential of the FD section in the amplification type unit pixel (first pixel) 15 in FIG. Here, L of the drain line 7
In order to prevent the OW level potential from flowing back to the PD1, at timings t4 to t6 in FIG. 9, "OR circuit output" which is an OR signal of the output of the charge readout pulse generation circuit 22 and the output of the reset pulse generation circuit 23 After “2” becomes LOW after the timing t4, the VDD power supply pulse (VDD2) is set to the LOW level (t5). FIG. 10A is a diagram showing a relative position of each potential in the first pixel.
(B) to (g) of FIG. 10 are potential diagrams of the same pixel accompanying the operation of the drive circuit of FIG. 10 (b) to 10
Timings t1 to t6 in (g) respectively correspond to timings t1 to t6 in FIG. Here, the potential of the drain line 7 of the first pixel at the time of reset of the second pixel adjacent to the first pixel is set to the HIGH level potential, and the signal charge obtained by photoelectric conversion in the second pixel is read transistor. 2, the drain line 7 of the first pixel at the time when the detection transistor 4 operates by being read to the FD section (t5).
Are set to LOW level potentials (here, zero). Further, when a LOW level voltage is applied to the gate of the reset transistor 3 of the first pixel, the potential under the gate is set to a potential higher than the potential depth of PD1 of the first pixel. Therefore, even when a pulse is applied to the readout transistor 2 of the first pixel when the second pixel is reset, for example, as shown in FIG. 10E, the charge from the FD portion to the PD1 in the first pixel is changed. Backflow is prevented. Moreover, as shown in FIG. 10F, the drain line 7 of the first pixel at the time of reading out the second pixel is used.
Is a LOW level potential, the off state of the detection transistor 4 in the first pixel can be ensured, and mixing of output signals on the signal line 6 can be prevented. Note that the reset transistor 3 may be of a depletion type.
Further, even when the LOW level potential of the drain line 7 is set to zero, the off state of the detection transistor 4 can be ensured.

FIG. 11 shows a specific configuration example of the drive circuits of FIGS. In FIG. 11, C1 and C1
2 is a capacitor, SW1 and SW2 are switches, Tr1
And Tr2 are backflow prevention transistors. The configuration of FIG. 11 is based on a first AND comprising C1, SW1, and Tr1.
Circuit and a second AND comprising C2, SW2 and Tr2
This is a dynamic circuit composed of a circuit and a wired OR connection of outputs of both AND circuits. For example, the first AND circuit supplies the charge readout pulse generation circuit 22 with:
The second AND circuit corresponds to the reset pulse generating circuit 23, and the wired OR connection corresponds to the OR circuit 24 (see FIG. 3). In this case, the two inputs φ of the first AND circuit
A and φT correspond to the N-th output SigN of the vertical shift register 12 and the conventional read pulse, respectively,
Are input to the (N + 1) th stage output Sig (N + 1) of the vertical shift register 12 respectively.
And a conventional reset pulse. In the first AND circuit, the switch SW1 is connected to one end (+
Side) is applied with the first pulse signal φA. A second pulse signal φT is applied to the other end (−side) of the capacitor C1. The gate of the transistor Tr1 is a capacitor C
1, the drain is coupled to the other end (− side) of the capacitor C1, and the source is coupled to a wired OR connection point. The second AND circuit has a similar configuration. φB and φY are signals for controlling the opening and closing of switches SW1 and SW2, respectively.

FIG. 12 shows the first AND in the circuit of FIG.
FIG. 3 is a timing chart for explaining the operation of the circuit. According to FIG. 12, the switch SW is controlled by the control signal φB.
1 is closed, the rising edge of the first pulse signal φA arrives. As a result, the capacitor C1 is charged, and the capacitor C1 holds the charging voltage (the HIGH level voltage having the polarity shown in FIG. 11) even after the switch SW1 is opened. When the second pulse signal φT arrives in this state, the HIGH level voltage of this signal is superimposed on the charging voltage of the capacitor C1, and as a result, the transistor Tr
1 turns on, and the pulse signal φT passes through the wired OR connection point. Thereafter, the switch SW1 is closed again after the fall of the first pulse signal φA. As a result, the capacitor C1 is discharged and returns to the original state.

According to each AND circuit in FIG. 11, the backflow of charges from the output side to the input side is prevented. Therefore,
The capacitor 1 in the vertical shift register 12 shown in FIG.
8 is charged, the vertical shift register 12
There is no problem in the operation of. However, the dynamic circuit having the backflow prevention function of FIG. 11 has a wide application range, not limited to the solid-state imaging device according to the present embodiment.

FIG. 13 shows an example of a wiring layout in the amplifying unit pixel 15 of FIG. The signal line 6 and the drain line 7 are wired so as to intersect at different layers in order to prevent light leakage. Specifically, the drain line 7 and the FD wiring 17 are made of a first-layer metal above the gate line 16 (not shown), and the signal line 6 is made of a second-layer metal above this. Here, the FD wiring 17 is a first-layer light-shielding metal, and the signal line 6 is a second-layer light-shielding metal. A light-shielding film may be further provided on the signal line 6. If the drain line 7 and the gate line 16 are formed of the same wiring layer, for example, polysilicon, polycide, silicide, etc., the layer stacked on the semiconductor substrate can be made thinner, so that the light collection efficiency at the opening of the PD 1 can be reduced. Is improved.

FIG. 14 shows another wiring layout example in the amplification type unit pixel 15 of FIG. In this example,
In order to prevent light leakage, the signal line 6 and the drain line 7 are wired so as to cross each other in different layers. Specifically, the signal line 6 and the FD wiring 17 are connected to the gate line 16
The drain line 7 is made of a first metal layer (not shown), and the drain line 7 is made of a second metal layer. here,
The FD wiring 17 is a first-layer light-shielding metal, and the drain line 7 is a second-layer light-shielding metal. A light-shielding film may be further provided on the drain line 7.

FIG. 15 shows a configuration example of another solid-state imaging device according to the present invention. In the example of FIG. 15, a VDD common wiring (single drain layer) 41 is formed on the polysilicon / aluminum wiring 40. That is, the horizontal drain lines 7 in FIG. 1 are further reduced, and the drain region of each unit pixel is connected to a single drain layer 41 also serving as a light shielding film. More specifically, the signal line and the FD wiring are formed of polysilicon / aluminum wiring 4 above the gate line (not shown).
0, and the drain layer 41 is made of a second-layer metal layer above the drain layer 41. Here, the FD wiring is a first layer light shielding metal, and the drain layer 41 is a second layer light shielding metal. It is preferable that the drain layer 41 also serves as a cell light shielding film in the optical black portion. However,
The configuration in FIG. 15 can be applied to a solid-state imaging device having no gate line for both reading and resetting.

FIG. 16 shows a modification of the configuration of FIG. According to FIG. 2, it is understood that the input timing pulse T1 or T2 for driving the vertical shift register 12 becomes the output Sig (N) of each stage of the shift register (N
= 1, 2, 3, ...). According to FIG. 16, the Nth stage output SigN of the vertical shift register 12 directly drives the drain line 7 without passing through the VDD horizontal wiring power supply circuit 25 (see FIG. 3). That is, according to the example of FIG. 16, the driver constituting the VDD horizontal wiring power supply circuit 25 can be omitted, and the reduction in the size of the semiconductor substrate and the reduction in power consumption can be realized. The gate line 16 which performs both reading and resetting is connected to the vertical shift register 1
It may be driven by the output of each of the two stages.

Although the above embodiment has shown the case where the transistor is an N-type MOS, the same effect can be realized when the transistor is a P-type MOS or a CMOS by operating according to the same principle. Further, the present invention is not limited to the above embodiments, and various combinations such as a unit pixel, a vertical shift register and its driving circuit, a structure of wiring and a light shielding film, and the like can be adopted. In the above embodiment, the case of the N-type photodiode has been described. However, in the case of the P-type photodiode, it goes without saying that the relationship between each voltage and the potential is reversed.

[0027]

As described above, according to the present invention, a solid-state imaging device can selectively supply a power pulse for each row, thereby reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of an amplification type unit pixel in a solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a vertical shift register.

FIG. 3 is a block diagram illustrating a configuration example of a drive circuit for driving the amplification unit pixel of FIG. 1;

FIG. 4 is a timing chart for explaining the operation of the drive circuit of FIG. 3;

5A is a diagram showing a relative position of each potential in the amplification unit pixel of FIG. 1, and FIGS. 5B to 5G are potential diagrams of the same pixel accompanying the operation of the drive circuit of FIG. is there.

FIG. 6 is a timing chart showing a modification of the operation in FIG. 4;

7 (a) to 7 (g) correspond to FIG. 6 and FIG. 5 (a)
It is a figure which shows the modification of FIG.5 (g).

FIG. 8 is a block diagram showing another configuration example of a drive circuit for driving the amplification unit pixel of FIG. 1;

FIG. 9 is a timing chart for explaining the operation of the drive circuit of FIG. 8;

10A is a diagram showing a relative position of each potential in the amplifying unit pixel of FIG. 1, and FIGS.
FIG. 9 is a potential diagram of the pixel accompanying the operation of the drive circuit of FIG.

FIG. 11 is a circuit diagram showing a specific configuration example of the drive circuits of FIGS. 3 and 8;

FIG. 12 is a timing chart for explaining the operation of the circuit of FIG. 11;

FIG. 13 is a plan view illustrating an example of a wiring layout in the amplification unit pixel of FIG. 1;

FIG. 14 is a plan view showing another example of a wiring layout in the amplification unit pixel of FIG. 1;

FIG. 15 is a cross-sectional view illustrating a configuration example of another solid-state imaging device according to the present invention.

FIG. 16 is a block diagram showing a modification of the configuration of FIG. 3;

FIG. 17 is a block diagram illustrating an example of a conventional solid-state imaging device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 photodiode (PD) [photoelectric conversion region] 2 readout transistor 3 reset transistor 4 detection transistor 6 signal line 7 drain line (VDD) 11 timing generation circuit 12 vertical shift register 13 horizontal shift register 14 photosensitive region 15 amplifying unit pixel 16 Gate line serving both reading and reset 17 Wiring connecting floating diffusion (FD) and detection transistor 18 Capacitor 20 Nth stage of shift register 21 Nth stage of shift register (N + 1) stage 22 Charge read pulse generation circuit 23 Reset pulse generation circuit 24 OR Circuit 25 VDD horizontal wiring power supply circuit 30 First power pulse generation circuit 31 Second power pulse generation circuit 32 VDD horizontal wiring power supply OR circuit 40 Polysilicon / aluminum wiring 41 VDD common wiring [ Single drain layer] C1, C2 Capacitor FD Floating diffusion [storage area] SW1, SW2 Switch Tr1, Tr2 Backflow prevention transistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M118 AA04 AB01 BA14 CA02 DB03 DB09 DB11 DD04 DD12 FA06 FA33 GB15 GB17 5C024 CY42 GX03 GX16 GY38 GY39 GZ22 HX40 HX51

Claims (12)

[Claims] 1. A photoelectric conversion region for photoelectrically converting incident light, a readout transistor for reading out signal charges obtained by the photoelectric conversion, and storing the readout signal charges on a semiconductor substrate. A detection transistor for detecting the read signal charge by applying a potential of the storage region to a gate; a reset transistor for resetting the signal charge of the storage region; In a solid-state imaging device in which a plurality of amplifying unit pixels having a drain region for supplying a pulse voltage to the accumulation region via a transistor are two-dimensionally arranged, the drain region of the plurality of amplifying unit pixels is: A period connected to a different drain line for each row, and at least a period for resetting signal charges in the accumulation region; The period for detecting the signal charge to set the potential of the drain line to HIGH level potential, the solid-state imaging device, characterized in that said drain line is pulsed. 2. The solid-state imaging device according to claim 1, wherein the potential of the drain line is set to a HIGH level potential while the readout transistor is on. apparatus. 3. The solid-state imaging device according to claim 1, wherein a vertical shift register for selecting a certain row among the plurality of amplifying unit pixels, and an output of a certain stage of the vertical shift register are provided. A solid-state imaging device further comprising: a circuit for supplying a power pulse generated by using the power pulse to a drain line of a corresponding row. 4. The solid-state imaging device according to claim 1, further comprising a shift register for selecting a certain row or column among the plurality of amplifying unit pixels, wherein the plurality of amplifying unit pixels are further provided. Are driven by a pulse for driving the shift register. 5. The solid-state imaging device according to claim 1, wherein two or more signal charges adjacent to each other in a column direction among the plurality of amplification unit pixels are detected. A solid-state imaging device configured to be able to set the potentials of two or more drain lines to a HIGH level potential during a blanking period. 6. The solid-state imaging device according to claim 1, wherein a period during which the signal charge read from the photoelectric conversion region is stored in the storage region, and a period during which the signal charge is stored in the storage region. The solid-state imaging device is configured to set the potential of the drain line to a HIGH level potential at least once in the period for resetting the signal charge. 7. The solid-state imaging device according to claim 1, wherein the unnecessary charge read from the photoelectric conversion region is used to discard the unnecessary charge obtained in the photoelectric conversion region. The period in which the charge is stored in the storage region and the period in which the unnecessary charge in the storage region is reset are determined by setting the potential of the drain line to a high level.
A solid-state imaging device configured to be set to an H level potential. 8. The solid-state imaging device according to claim 1, wherein the readout transistor and the reset transistor are simultaneously turned on to discard unnecessary charges obtained in the photoelectric conversion region. The potential of the drain line is set to HI
A solid-state imaging device configured to be set to a GH level potential. 9. The solid-state imaging device according to claim 1, wherein said drain line is formed of the same wiring layer as a gate of each of said transistors. apparatus. 10. The solid-state imaging device according to claim 1, wherein a wiring connecting the storage region and a gate of the detection transistor is made of a first-layer light-shielding metal. Characteristic solid-state imaging device. 11. The solid-state imaging device according to claim 1, wherein the detection transistors of the plurality of amplification-type unit pixels are connected to different signal lines for each column, and A wiring connecting the gate of the detection transistor and the drain line are made of a first layer metal,
In addition, the signal line is made of a second layer metal that is higher than the first layer metal. 12. The solid-state imaging device according to claim 1, wherein the detection transistors of the plurality of amplifying unit pixels are connected to different signal lines for each column, and are connected to the storage region. The wiring connecting the gate of the detection transistor and the signal line are made of a first-layer metal, and the drain line is made of a second-layer metal higher than the first-layer metal. Characteristic solid-state imaging device.