JP3786886B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS type solid-state imaging device used for a digital camera or the like.
[0002]
[Prior art]
FIG. 17 shows an example of a conventional solid-state imaging device composed of MOS transistors. The solid-state imaging device includes a plurality of photodiodes (PD) 1, a readout transistor 2, a floating diffusion (FD) portion, a reset transistor 3, a detection transistor 4, and an address transistor 5 on a semiconductor substrate. A solid-state imaging device having a photosensitive region 14 in which amplification unit pixels are two-dimensionally arranged, and further includes a signal line 6, a drain line 7, a readout gate line 8, a reset gate line 9, an address gate line 10, and a pixel. A vertical shift register 12 that selects a row, a horizontal shift register 13 that selects a pixel column, a timing generation circuit 11 that supplies necessary pulses to both shift registers 12 and 13, and the like.
[0003]
The signal charge photoelectrically converted by the PD 1 is read by the read transistor 2 to the FD portion which is an accumulation region for storing the signal charge. The signal voltage is taken out to the signal line 6 on the condition that the potential of the FD portion is determined by the amount of charge read to the FD portion, the gate voltage of the detection transistor 4 is changed, and the address transistor 5 is selected. It is.
[0004]
[Problems to be solved by the invention]
According to the prior art of FIG. 17, although the signal voltage is taken out to the signal line 6 for each row, the vertical drain line 7 is simultaneously applied to all of the plurality of amplifying unit pixels arranged in two dimensions. A power pulse is supplied through the terminal. Therefore, there is a problem that power consumption is large.
[0005]
An object of the present invention is to reduce power consumption in a solid-state imaging device.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a solid-state imaging device according to the present invention includes a photoelectric conversion region for photoelectrically converting incident light on a semiconductor substrate, a read transistor for reading signal charges obtained by photoelectric conversion, and A storage region for storing the read signal charge, a detection transistor for detecting the read signal charge by applying the potential of the storage region to the gate, and resetting the signal charge in the storage region In a solid-state imaging device in which a plurality of amplifying unit pixels having a reset transistor and a drain region for supplying a pulse voltage composed of a LOW level potential and a HIGH level potential to a storage region via the reset transistor are two-dimensionally arranged The drain regions of the plurality of amplification unit pixels are connected to different drain lines for each row, and the plurality of amplification unit pixels The read pulse to the read transistor of the first pixel and the reset pulse to the reset transistor of the second pixel adjacent to the first pixel in the column direction are supplied by a common gate line. When the second pixel is reset before the signal transistor obtained in the photoelectric conversion region in the second pixel is read out to the accumulation region by the readout transistor and the detection transistor operates. The potential of the drain line of the first pixel when a pulse is applied to the common gate line of the readout transistors is set to a HIGH level potential . With this configuration, power supply pulses can be selectively supplied for each row, so that power consumption is reduced. In addition, there is no fear of backflow of charges to the photoelectric conversion region (PD) due to the LOW level potential of the drain line.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described.
[0009]
FIG. 1 shows a configuration example of an amplification unit pixel in a solid-state imaging device according to the present invention. In FIG. 1, 1 is a photodiode (PD), 2 is a readout transistor, FD is a floating diffusion section, 3 is a reset transistor, 4 is a detection transistor, 6 is a signal line, 7 is a drain line (VDD), and 15 is an amplification type. A unit pixel, 16 is a gate line for both reading and resetting, and 17 is an FD wiring connecting the FD section and the gate of the detection transistor 4. The gate line 16 that performs both reading and resetting is connected to the gate of the reading transistor 2 of the pixel in the Nth row and the gate of the reset transistor 3 of the pixel in the (N + 1) th row, where N is an integer. . The detection transistors 4 are connected to different signal lines 6 for each column. The horizontal drain line 7 is supplied with a different VDD power supply pulse for each row.
[0010]
According to FIG. 1, the configuration of each unit pixel 15 is composed of one vertical wiring (signal line 6), two horizontal wirings (drain line 7 and gate line 16 for both reading and resetting), 3 The number of transistors (read transistor 2, reset transistor 3, and detection transistor 4) is reduced.
[0011]
FIG. 2 shows a configuration example of the vertical shift register 12. Vin, T1, and T2 are timing pulses given from the timing generation circuit 11. Capacitors 18 are provided at each stage of the shift register, and Sig1, Sig2, and Sig3 are outputs of the respective stages of the shift register.
[0012]
FIG. 3 shows a configuration example of a drive circuit for driving the amplification type unit pixel 15 of FIG. In FIG. 3, 20 is the Nth stage of the vertical shift register 12, 21 is the (N + 1) th stage of the vertical shift register 12, 22 is the charge read pulse generating circuit, 23 is the reset pulse generating circuit, 24 is the OR circuit, 25 is This is a VDD horizontal wiring power supply circuit. The charge read pulse generation circuit 22 is a circuit for generating an AND signal of the N-stage output SigN of the vertical shift register 12 and the conventional read pulse. The reset pulse generation circuit 23 is a circuit for generating an AND signal of the (N + 1) -th stage output Sig (N + 1) of the vertical shift register 12 and a conventional reset pulse. The OR circuit 24 is a circuit for supplying an OR signal of the output of the charge readout pulse generation circuit 22 and the output of the reset pulse generation circuit 23 to the gate line 16. The VDD horizontal wiring power supply circuit 25 is a circuit for supplying an AND signal of the N-stage output SigN of the vertical shift register 12 and the conventional power supply pulse to the drain line 7.
[0013]
FIG. 4 is a timing chart for explaining the operation of the drive circuit of FIG. “The potential of FD2” in FIG. 4 indicates the potential of the FD portion in the amplification type unit pixel (first pixel) 15 in FIG. FIG. 5A is a diagram showing the relative position of each potential in the first pixel, and FIGS. 5B to 5G are potential diagrams of the pixel accompanying the operation of the drive circuit in FIG. It is. Timings t1 to t6 in FIGS. 5B to 5G respectively correspond to timings t1 to t6 in FIG. Here, the LOW level potential of the drain line 7 of the first pixel when the second pixel adjacent to the first pixel is reset is set to a potential higher than the potential depth of PD1 of the first pixel. Further, when a LOW level voltage is applied to the gate of the reset transistor 3 of the first pixel, the potential under the gate is set to a potential higher than the LOW level potential of the drain line 7. Therefore, even if a pulse is given to the read transistor 2 of the first pixel when the second pixel is reset, unnecessary charges of the PD 1 in the first pixel are efficiently discarded as shown in FIG. 5 (e), for example. As a result, the backflow of charges from the FD portion to PD1 is prevented. In addition, the LOW level voltage applied to the gate of the readout transistor 2 of the same pixel is the reset transistor 3 of the same pixel so that the off state of the detection transistor 4 of the first pixel can be ensured in a situation other than FIG. The voltage is set to be lower than the LOW level voltage applied to the gate.
[0014]
In this case, the potential of the drain line 7 is set to the HIGH level potential during the period in which the signal charges read from the PD 1 are stored in the FD section and at least one of the periods in which the signal charges in the FD section are reset. Must be set. When discarding unnecessary charges obtained by the PD 1 for realizing the electronic shutter function, a period in which the unnecessary charges read from the PD 1 are stored in the FD section, and a period in which the unnecessary charges in the FD section are reset. In addition, the potential of the drain line 7 may be set to a HIGH level potential. However, when the unnecessary charge read from the PD 1 to the FD portion is immediately reset, the potential of the drain line 7 may be set to the HIGH level potential while the read transistor 2 and the reset transistor 3 are simultaneously turned on. In order to realize interlaced display, the potentials of the drain lines 7 in two or more rows can be set to a HIGH level potential within one horizontal blanking period in order to detect signal charges of two or more pixels adjacent to each other in the column direction. Configure.
[0015]
Note that the LOW level potential of the drain line 7 of the first pixel at the time of resetting the second pixel is set to a potential lower than the potential depth of the PD1 of the first pixel, and the reset transistor of the first pixel. When the LOW level voltage is applied to the gate 3, the potential under the gate may be set to a potential higher than the LOW level potential of the drain line 7. Thus, when a pulse is given to the read transistor 2 of the first pixel at the time of resetting the second pixel, the so-called “priming effect” in which the LOW level potential of VDD is set as the reference potential of the PD as a countermeasure against afterimage. Can be demonstrated.
[0016]
6 shows a modified example of the operation of FIG. 4, and FIGS. 7A to 7G show modified examples of FIGS. 5A to 5G corresponding to FIG. As shown in FIGS. 6 and 7 (a) to 7 (g), the backflow of charge to PD1 can be prevented only by increasing the difference between the LOW level potential of VDD and the potential of PD1. In this case, the LOW level voltage applied to the gates of the read transistor 2 and the reset transistor 3 can be made the same, and the manufacturing process can be simplified.
[0017]
FIG. 8 shows another configuration example of the drive circuit for driving the amplification type unit pixel of FIG. In FIG. 8, 30 is a first power supply pulse generation circuit, 31 is a second power supply pulse generation circuit, and 32 is a VDD horizontal wiring power supply OR circuit. The first power pulse generation circuit 30 is a circuit for generating an AND signal of the N-th stage output SigN of the vertical shift register 12 and the first power pulse in the first period. The second power supply pulse generation circuit 31 generates an AND signal of the (N + 1) -th stage output Sig (N + 1) of the vertical shift register 12 and the second power supply pulse in the second period following the first period. Circuit. The VDD horizontal wiring power supply OR circuit 32 is a circuit for supplying an OR signal of the output of the first power supply pulse generation circuit 30 and the output of the second power supply pulse generation circuit 31 to the drain line 7. The circuit configuration for driving the gate line 16 is the same as in the case of FIG.
[0018]
FIG. 9 is a timing chart for explaining the operation of the drive circuit of FIG. “The potential of FD2” in FIG. 9 indicates the potential of the FD portion in the amplification type unit pixel (first pixel) 15 in FIG. Here, in order to prevent the LOW level potential of the drain line 7 from flowing backward to PD1, the OR of the output of the charge read pulse generation circuit 22 and the output of the reset pulse generation circuit 23 is performed at timings t4 to t6 in FIG. After the signal “OR circuit output 2” becomes LOW after timing t4, the VDD power supply pulse (VDD2) is set to the LOW level (t5). Further, FIG. 10 (a) is a diagram showing the relative positions of the respective potentials of the first pixel, the potential diagram of the pixel associated with the operation of the drive circuit of FIG. 10 (b) ~ FIG 10 (g) is 8 It is. Timings t1 to t6 in FIGS. 10B to 10G correspond to timings t1 to t6 in FIG. 9, respectively. Here, when the second pixel adjacent to the first pixel is reset, the potential of the drain line 7 of the first pixel is set to the HIGH level potential, and the signal charge obtained by photoelectric conversion in the second pixel is read transistor. 2, the potential of the drain line 7 of the first pixel is set to the LOW level potential (here, zero) when the detection transistor 4 is read by the FD unit to operate (t5). Further, when a LOW level voltage is applied to the gate of the reset transistor 3 of the first pixel, the potential under the gate is set to a potential higher than the potential depth of PD1 of the first pixel. Therefore, even when a pulse is given to the readout transistor 2 of the first pixel at the time of resetting the second pixel, for example, as shown in FIG. 10E, the charge from the FD portion to the PD1 in the first pixel is reduced. Backflow is prevented. In addition, as shown in FIG. 10F, since the potential of the drain line 7 of the first pixel at the time of reading the second pixel is the LOW level potential, the off state of the detection transistor 4 in the first pixel is ensured. It is possible to prevent mixing of output signals on the signal line 6. The reset transistor 3 may be a depletion type. Further, even when the LOW level potential of the drain line 7 is set to zero, the detection transistor 4 can be kept off.
[0019]
FIG. 11 shows a specific configuration example of the drive circuit of FIGS. 3 and 8. In FIG. 11, C1 and C2 are capacitors, SW1 and SW2 are switches, and Tr1 and Tr2 are backflow prevention transistors. The configuration shown in FIG. 11 is a dynamic AND circuit composed of a first AND circuit composed of C1, SW1, and Tr1, a second AND circuit composed of C2, SW2, and Tr2, and a wired OR connection of outputs of both AND circuits. Circuit. For example, the first AND circuit corresponds to the charge readout pulse generation circuit 22, the second AND circuit corresponds to the reset pulse generation circuit 23, and the wired OR connection corresponds to the OR circuit 24 (see FIG. 3). In this case, the two inputs φA and φT of the first AND circuit correspond to the N-stage output SigN of the vertical shift register 12 and the conventional read pulse, respectively, and the two inputs φX and φR of the second AND circuit are vertical, respectively. This corresponds to the (N + 1) -th stage output Sig (N + 1) of the shift register 12 and the conventional reset pulse. In the first AND circuit, the switch SW1 applies the first pulse signal φA to one end (+ side) of the capacitor C1. The second pulse signal φT is applied to the other end (− side) of the capacitor C1. The transistor Tr1 has a gate coupled to one end (+ side) of the capacitor C1, a drain coupled to the other end (− side) of the capacitor C1, and a source coupled to a wired OR connection point. The second AND circuit has a similar configuration. φB and φY are signals for controlling opening and closing of the switches SW1 and SW2, respectively.
[0020]
FIG. 12 is a timing chart for explaining the operation of the first AND circuit in the circuit of FIG. According to FIG. 12, the rising edge of the first pulse signal φA arrives with the switch SW1 closed by the control signal φB. Thereby, even after the capacitor C1 is charged and the switch SW1 is opened, the capacitor C1 maintains the charging voltage (HIGH level voltage having the polarity shown in FIG. 11). When the second pulse signal φT arrives in this state, the HIGH level voltage of this signal is superimposed on the charging voltage of the capacitor C1, so that the transistor Tr1 is turned on, and the pulse signal φT passes to the wired OR connection point. . Thereafter, the switch SW1 is closed again after the fall of the first pulse signal φA. As a result, the capacitor C1 is discharged and returns to the original state.
[0021]
According to each AND circuit in FIG. 11, the backflow of charges from the output side to the input side is prevented. Therefore, even when the capacitor 18 in the vertical shift register 12 shown in FIG. 2 is charged, the operation of the vertical shift register 12 is not hindered. However, the dynamic circuit having the backflow prevention function in FIG. 11 is not limited to the solid-state imaging device according to the present embodiment, and has a wide application range.
[0022]
FIG. 13 shows a wiring layout example in the amplification type unit pixel 15 of FIG. The signal line 6 and the drain line 7 are wired so as to intersect with each other in different layers in order to prevent light leakage. Specifically, the drain line 7 and the FD wiring 17 are made of a first layer metal above the gate line 16 (not shown), and the signal line 6 is made of a second layer metal above this. Here, the FD wiring 17 is a light shielding metal in the first layer, and the signal line 6 is a light shielding metal in the second layer. A light shielding film may be further provided on the signal line 6. If the drain line 7 and the gate line 16 are made of the same wiring layer, for example, polysilicon, polycide, silicide, etc., the layer stacked on the semiconductor substrate can be made thin, so that the light collection rate at the opening of the PD 1 can be reduced. Is improved.
[0023]
FIG. 14 shows another wiring layout example in the amplification unit pixel 15 of FIG. Also in this example, in order to prevent light leakage, the signal line 6 and the drain line 7 are wired so as to cross each other in different layers. Specifically, the signal line 6 and the FD wiring 17 are made of a first layer metal above the gate line 16 (not shown), and the drain line 7 is made of a second layer metal above this. Here, the FD wiring 17 is a light shielding metal in the first layer, and the drain line 7 is a light shielding metal in the second layer. A light shielding film may be further provided on the drain line 7.
[0024]
FIG. 15 shows a configuration example of another solid-state imaging apparatus according to the present invention. In the example of FIG. 15, the VDD common wiring (single drain layer) 41 is formed on the polysilicon / aluminum wiring 40. That is, the horizontal drain line 7 in FIG. 1 is further reduced, and the drain region of each unit pixel is connected to a single drain layer 41 that also serves as a light shielding film. More specifically, the signal line and the FD wiring are made of polysilicon / aluminum wiring 40 above the gate line (not shown), and the drain layer 41 is made of a second layer metal above this. Here, the FD wiring is a first layer light shielding metal, and the drain layer 41 is a second layer light shielding metal. The drain layer 41 may also serve as a cell light-shielding film for the optical black portion. However, the configuration of FIG. 15 can also be applied to a solid-state imaging device that does not have a gate line for both reading and resetting.
[0025]
FIG. 16 shows a modification of the configuration of FIG. As can be seen from FIG. 2, the input timing pulse T1 or T2 for driving the vertical shift register 12 becomes the output Sig (N) of each stage of the shift register (N = 1, 2, 3,...). According to FIG. 16, the N-th stage output SigN of the vertical shift register 12 directly drives the drain line 7 without going through the VDD lateral wiring power supply circuit 25 (see FIG. 3). That is, according to the example of FIG. 16, the driver constituting the VDD horizontal wiring power supply circuit 25 can be omitted, and the semiconductor substrate can be reduced in size and reduced in power consumption. The gate line 16 serving both for reading and resetting may be driven by the output of each stage of the vertical shift register 12.
[0026]
Although the above embodiment shows the case where the transistor is an N-type MOS, the same effect can be realized by operating according to the same principle when the transistor is a P-type MOS or CMOS. Further, the present invention is not limited to the above-described embodiment, and various combinations such as a unit pixel, a vertical shift register and its driving circuit, a structure of a wiring and a light shielding film, and the like can be adopted as the embodiment. In the above-described embodiment, the case of the N-type photodiode has been described. However, it goes without saying that the relationship between each voltage and potential is reversed in the case of the P-type photodiode.
[0027]
【The invention's effect】
As described above, according to the present invention, since the power pulse can be selectively supplied for each row in the solid-state imaging device, the power consumption is reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of an amplification unit pixel in a solid-state imaging device according to the present invention.
FIG. 2 is a circuit diagram illustrating a configuration example of a vertical shift register.
3 is a block diagram illustrating a configuration example of a driving circuit for driving the amplification type unit pixel of FIG. 1;
4 is a timing chart for explaining the operation of the drive circuit of FIG. 3; FIG.
5A is a diagram showing a relative position of each potential in the amplification type unit pixel of FIG. 1, and FIGS. 5B to 5G are potential diagrams of the pixel accompanying the operation of the drive circuit of FIG. is there.
6 is a timing chart showing a modification of the operation of FIG.
FIGS. 7A to 7G are diagrams showing modifications of FIGS. 5A to 5G corresponding to FIG.
FIG. 8 is a block diagram showing another configuration example of a drive circuit for driving the amplification type unit pixel of FIG. 1;
9 is a timing chart for explaining the operation of the drive circuit of FIG. 8; FIG.
10A is a diagram showing the relative position of each potential in the amplification type unit pixel of FIG. 1, and FIGS. 10B to 10G are potential diagrams of the pixel accompanying the operation of the drive circuit of FIG. is there.
11 is a circuit diagram showing a specific configuration example of the drive circuit of FIGS. 3 and 8. FIG.
12 is a timing chart for explaining the operation of the circuit of FIG.
13 is a plan view showing a wiring layout example in the amplification type unit pixel of FIG. 1; FIG.
14 is a plan view showing another wiring layout example in the amplification type unit pixel of FIG. 1; FIG.
FIG. 15 is a cross-sectional view illustrating a configuration example of another solid-state imaging device according to the present invention.
16 is a block diagram showing a modification of the configuration of FIG.
FIG. 17 is a block diagram illustrating an example of a conventional solid-state imaging device.
[Explanation of symbols]
1 Photodiode (PD) [Photoelectric conversion area]
2 Reading transistor 3 Reset transistor 4 Detection transistor 6 Signal line 7 Drain line (VDD)
DESCRIPTION OF SYMBOLS 11 Timing generation circuit 12 Vertical shift register 13 Horizontal shift register 14 Photosensitive area | region 15 Amplification type | mold unit pixel 16 Gate line 17 which served as both reading and reset Wiring 18 which connects a floating diffusion (FD) and a detection transistor 18 Capacitor 20 Shift register Nth stage 21 shift register (N + 1) stage 22 charge readout pulse generation circuit 23 reset pulse generation circuit 24 OR circuit 25 VDD horizontal wiring power supply circuit 30 first power pulse generation circuit 31 second power pulse generation circuit 32 VDD horizontal wiring power supply OR Circuit 40 Polysilicon / aluminum wiring 41 VDD common wiring [single drain layer]
C1, C2 Capacitor FD Floating diffusion [Storage region]
SW1, SW2 Switch Tr1, Tr2 Backflow prevention transistor

Claims (7)

A photoelectric conversion region for photoelectrically converting incident light on a semiconductor substrate, a read transistor for reading signal charges obtained by the photoelectric conversion, and an accumulation region for storing the read signal charges A detection transistor for detecting the read signal charge by applying a potential of the storage region to a gate, a reset transistor for resetting the signal charge of the storage region, and the reset transistor through the reset transistor. In a solid-state imaging device in which a plurality of amplification type unit pixels having a drain region for supplying a pulse voltage composed of a LOW level potential and a HIGH level potential to a storage region are two-dimensionally arranged,
The drain regions of the plurality of amplification type unit pixels are connected to different drain lines for each row,
A readout pulse to the readout transistor of the first pixel of the plurality of amplification type unit pixels and a reset pulse to the reset transistor of the second pixel adjacent to the first pixel in the column direction are shared. Configured to supply with a gate line of
In resetting the second pixel, the signal charge obtained in the photoelectric conversion region in the second pixel is read out to the accumulation region by the read transistor and the detection transistor operates. A solid-state imaging device , wherein a potential of a drain line of the first pixel when a pulse is applied to the common gate line of the readout transistor is set to a HIGH level potential . The solid-state imaging device according to claim 1,
After the signal charge obtained in the photoelectric conversion region in the second pixel is read out to the storage region by the read transistor and the detection transistor is operated, a pulse is applied to the common gate line of the read transistor in the first pixel. And a potential of the drain line of the first pixel is set to a HIGH level potential during a period in which the readout transistor of the first pixel is on . The solid-state imaging device according to claim 1 or 2 ,
Within one horizontal blanking period, the potential of the drain lines of two or more rows can be set to a HIGH level potential in order to detect signal charges of two or more pixels adjacent to each other in the column direction among the plurality of amplification type unit pixels. A solid-state imaging device configured as described above. The solid-state imaging device according to any one of claims 1 to 3 ,
The solid-state imaging device, wherein the drain line is formed of the same wiring layer as the gate of each transistor. The solid-state imaging device according to any one of claims 1 to 3 ,
The solid-state imaging device, wherein a wiring connecting the accumulation region and the gate of the detection transistor is made of a light-shielding metal of a first layer. The solid-state imaging device according to any one of claims 1 to 3 ,
The detection transistors of the plurality of amplification unit pixels are connected to different signal lines for each column,
The wiring connecting the accumulation region and the gate of the detection transistor and the drain line are made of a first layer metal, and
The solid-state imaging device, wherein the signal line is made of a second layer metal that is higher than the first layer metal. The solid-state imaging device according to any one of claims 1 to 3 ,
The detection transistors of the plurality of amplification unit pixels are connected to different signal lines for each column,
The wiring connecting the accumulation region and the gate of the detection transistor and the signal line are made of a first layer metal, and
The solid-state imaging device, wherein the drain line is made of a second layer metal that is higher than the first layer metal.

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