JP2003046221A - Method of manufacturing electronic component wiring board - Google Patents

Method of manufacturing electronic component wiring board

Info

Publication number
JP2003046221A
JP2003046221A JP2001229777A JP2001229777A JP2003046221A JP 2003046221 A JP2003046221 A JP 2003046221A JP 2001229777 A JP2001229777 A JP 2001229777A JP 2001229777 A JP2001229777 A JP 2001229777A JP 2003046221 A JP2003046221 A JP 2003046221A
Authority
JP
Japan
Prior art keywords
wiring
pattern
wiring board
etching
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001229777A
Other languages
Japanese (ja)
Other versions
JP4137412B2 (en
Inventor
Tomio Hioki
富男 日沖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP2001229777A priority Critical patent/JP4137412B2/en
Publication of JP2003046221A publication Critical patent/JP2003046221A/en
Application granted granted Critical
Publication of JP4137412B2 publication Critical patent/JP4137412B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Screen Printers (AREA)
  • ing And Chemical Polishing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component wiring board which is capable of preventing a short circuit from occurring between wiring patterns formed by etching or screen printing. SOLUTION: A circuit pattern is composed of wiring patterns 19 provided in array, a common wire 26 is provided to either of the wiring patterns 19, and the wiring patterns 19 are set independent of each other at a joint between the wiring pattern and the common wire 26. The circuit pattern is formed by etching in a method of manufacturing an electronic component wiring board 10, where a part 19a corresponding to the wiring pattern 19 is provided to a pattern mask 17 used for forming an etching resist film 18 utilized in an etching process, and a corresponding enlarged space 27 which furthermore enlarges a space 25 formed between the wiring patterns 19 is provided to the corner of the pattern mask 17 where a part 26a corresponding to the common wire 26 and a part 19a corresponding to the wiring pattern 19 are connected together.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子等の電
子部品を実装する電子部品用配線基板の製造方法に係
り、より詳細には、スペース部を介して近接する配線パ
ターンに短絡の発生のない回路パターンを備える電子部
品用配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component wiring board for mounting an electronic component such as a semiconductor element, and more specifically, to a short circuit in a wiring pattern which is adjacent to a wiring pattern via a space portion. The present invention relates to a method for manufacturing a wiring board for electronic components having a non-existing circuit pattern.

【0002】[0002]

【従来の技術】近年の半導体素子等の電子部品の高性能
化、小型化にともない、電子部品を搭載するための電子
部品用配線基板には、外部接続端子の多端子化、半導体
素子等の実装性、低コスト化、放熱特性、低インピーダ
ンス化、高絶縁特性等の観点からプラスチックからなる
配線基板やセラミックからなるパッケージや多層配線基
板が多く用いられている。
2. Description of the Related Art As electronic components such as semiconductor elements have become higher in performance and smaller in size in recent years, wiring boards for electronic components for mounting electronic components have a large number of external connection terminals, semiconductor elements, etc. From the viewpoint of mountability, cost reduction, heat dissipation characteristics, low impedance, high insulation characteristics, etc., wiring boards made of plastic, packages made of ceramics, and multilayer wiring boards are often used.

【0003】図6(A)〜(E)に示すように、例えば
プラスチック配線基板50は、樹脂からなる樹脂基材5
1の両面に銅箔52を接合して形成した導体層を備えた
1層又は多層の高耐熱性の銅張り樹脂基材53の所定の
位置にスルーホール54を穿設し、銅張り樹脂基材53
の表層及びスルーホール54に銅めっき55を施す。更
にその表層にドライフィルムを貼着し、配線パターン5
8通りになるようにフォトリソグラフィ法でエッチング
レジスト膜56を形成し、銅箔52及び銅めっき55か
らなる銅層にエッチング液57を噴射させてエッチング
を行った後、エッチングレジスト膜56を剥離して配線
パターン58を形成する。そして、感光性のソルダーレ
ジストをスクリーン印刷し、フォトリソグラフィ法によ
ってワイヤボンドパッド59や外部接続端子用パッド6
0等の部分を除いてソルダーレジスト膜61で被覆し、
ソルダーレジスト膜61の開口部から露出した部分にニ
ッケルめっき及び金めっきを施して形成している。
As shown in FIGS. 6A to 6E, for example, a plastic wiring board 50 includes a resin base material 5 made of resin.
Through holes 54 are formed at predetermined positions in a one-layer or multi-layered copper-clad resin base material 53 having high heat resistance, which is provided with a conductor layer formed by joining copper foils 52 on both sides of the copper-clad resin base. Material 53
Copper plating 55 is applied to the surface layer and the through holes 54. Further, a dry film is attached to the surface layer, and the wiring pattern 5
The etching resist film 56 is formed by a photolithography method so as to have eight patterns, the etching solution 57 is sprayed on the copper layer formed of the copper foil 52 and the copper plating 55 to perform etching, and then the etching resist film 56 is peeled off. To form the wiring pattern 58. Then, a photosensitive solder resist is screen-printed, and the wire bond pad 59 and the external connection terminal pad 6 are formed by photolithography.
It is covered with a solder resist film 61 except for parts such as 0,
The portion exposed from the opening of the solder resist film 61 is formed by nickel plating and gold plating.

【0004】また、図7(A)、(B)に示すように、
例えばセラミックパッケージ70は、アルミナ等からな
るセラミックグリーンシートに、半導体素子等の電子部
品搭載部やスルーホールを穿設し、このセラミックグリ
ーンシートに配線パターン72通りとなるようなスクリ
ーン印刷用スクリーンを当接させ、タングステンやモリ
ブデンからなる高融点金属のペーストを用いて、スルー
ホール導体71や配線パターン72をスクリーン印刷で
形成し、これらの複数枚のセラミックグリーンシートを
重ね合わせて、加熱しながら加圧して積層体を形成し、
還元性雰囲気中の約1550℃程度の高温でセラミック
グリーンシートと高融点金属を同時焼成して形成してい
る。
Further, as shown in FIGS. 7 (A) and 7 (B),
For example, in the ceramic package 70, a ceramic green sheet made of alumina or the like is provided with electronic component mounting portions such as semiconductor elements and through holes, and a screen printing screen having 72 wiring patterns is applied to the ceramic green sheet. The through-hole conductor 71 and the wiring pattern 72 are formed by screen printing using a high melting point metal paste made of tungsten or molybdenum, and a plurality of these ceramic green sheets are stacked and pressed while heating. To form a laminate,
The ceramic green sheet and the refractory metal are formed by simultaneous firing at a high temperature of about 1550 ° C. in a reducing atmosphere.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前述し
たような従来のプラスチック配線基板やセラミックパッ
ケージ等の電子部品用配線基板の製造方法においては、
次のような問題がある。 (1)図8(A)に示すように、例えば各配線パターン
58と、配線パターン58を一旦短絡させてめっきを施
すためのめっき引き回しパターンとなる共通線62とを
有する回路パターンをエッチング処理によって形成する
プラスチック配線基板50の場合には、各配線パターン
58と共通線62とが接続される隅部付近のエッチング
において、エッチング液の流れが悪くなり、スペース部
64にエッチング残り部65が発生し、めっきを施した
後に共通線62と各配線パターン58との接続部分を切
断部63で切断して切り離したとしても、隣り合う配線
パターン58間に短絡部66が発生する。 (2)図8(B)に示すように、セラミック基材上に、
屈曲部74を有し、隣り合う配線パターン72が狭幅の
スペース部73を介して近接する回路パターンをスクリ
ーン印刷を用いて形成するセラミックパッケージ70の
場合には、屈曲部74の角部付近のスクリーン印刷にお
いて、印刷ペーストの滲み部75が発生し、隣り合う配
線パターン72間に短絡が発生する。本発明は、このよ
うな事情に鑑みてなされたものであって、エッチングや
スクリーン印刷で形成する配線パターンの間に短絡が発
生するのを防止する電子部品用配線基板の製造方法を提
供することを目的とする。
However, in the conventional method of manufacturing a wiring board for electronic parts such as a plastic wiring board and a ceramic package as described above,
There are the following problems. (1) As shown in FIG. 8 (A), a circuit pattern having, for example, each wiring pattern 58 and a common line 62 which serves as a plating routing pattern for short-circuiting the wiring pattern 58 to perform plating is etched. In the case of the plastic wiring board 50 to be formed, the flow of the etching solution becomes poor in the etching in the vicinity of the corners where the wiring patterns 58 and the common line 62 are connected, and the etching residual portion 65 is generated in the space portion 64. Even if the connecting portion between the common line 62 and each wiring pattern 58 is cut and cut by the cutting portion 63 after plating, a short-circuit portion 66 occurs between the adjacent wiring patterns 58. (2) As shown in FIG. 8 (B), on a ceramic substrate,
In the case of a ceramic package 70 that has a bent portion 74 and adjacent wiring patterns 72 are adjacent to each other through a narrow space portion 73 to form a circuit pattern by using screen printing, a portion near the corner of the bent portion 74 is formed. In screen printing, a bleed portion 75 of the printing paste is generated, and a short circuit occurs between the adjacent wiring patterns 72. The present invention has been made in view of the above circumstances, and provides a method for manufacturing a wiring board for an electronic component, which prevents a short circuit from occurring between wiring patterns formed by etching or screen printing. With the goal.

【0006】[0006]

【課題を解決するための手段】前記目的に沿う第1の発
明に係る電子部品用配線基板の製造方法は、並設された
配線パターンの一方に共通線を有し、最終的には、配線
パターンと共通線との接合部分で各配線パターンを分離
独立させる回路パターンをエッチング処理によって形成
する電子部品用配線基板の製造方法において、エッチン
グ処理に用いるエッチングレジスト膜を形成するための
パターンマスクに、配線パターンに相当する部分と、共
通線に相当する部分が接続される隅部に、各配線パター
ンの間に形成されるスペース部が更に広がる対応拡大ス
ペース部を設けている。これにより、エッチング液が各
配線パターン間に形成されるスペース部の隅部まで流れ
やすくなり、エッチング液の滞りの発生を防止してエッ
チング処理が行える。従って、例えばめっき引き回しパ
ターンである共通線と各配線パターンとをエッチング後
に切断しても、エッチング未処理部の発生が抑えられる
ので、製品部の隣り合う配線パターンの間の短絡を防止
することができる。
According to a first aspect of the present invention, there is provided a method of manufacturing a wiring board for electronic parts, which has a common line on one of wiring patterns arranged in parallel, and finally a wiring pattern. In a method of manufacturing a wiring board for electronic components for forming a circuit pattern for separating and independently separating each wiring pattern at a joint portion between a pattern and a common line, in a pattern mask for forming an etching resist film used for etching processing, Corresponding enlarged space portions are provided at the corners where the portions corresponding to the wiring patterns and the portions corresponding to the common lines are connected, and the space portions formed between the wiring patterns further expand. As a result, the etching solution easily flows to the corners of the space formed between the wiring patterns, and the etching process can be performed while preventing the etching solution from being stagnant. Therefore, for example, even if the common line, which is a plating routing pattern, and each wiring pattern are cut after etching, the generation of unetched portions can be suppressed, so that a short circuit between adjacent wiring patterns of the product portion can be prevented. it can.

【0007】前記目的に沿う第2の発明に係る電子部品
用配線基板の製造方法は、セラミック基材上に、屈曲部
を有し、隣り合う配線パターンが狭幅のスペース部を介
して近接する回路パターンをスクリーン印刷を用いて形
成する電子部品用配線基板の製造方法において、スクリ
ーン印刷で用いられるスクリーン印刷用スクリーンの印
刷用レジスト膜には、屈曲部に対応する部分の少なくと
も一方の角部付近に、スペース部に対応する部分を実質
的に広げる対応拡大スペース部を設けている。これによ
り、印刷ペーストの滲みを対応拡大スペース部によって
形成される拡大スペース部で吸収でき、屈曲部の少なく
とも一方の角部付近までで抑えられるので、隣接する配
線パターン間の短絡を防止することができる。
According to a second aspect of the present invention, there is provided a method for manufacturing a wiring board for electronic parts, which has a bent portion on a ceramic substrate and adjacent wiring patterns are close to each other via a narrow space portion. In a method of manufacturing a wiring board for an electronic component in which a circuit pattern is formed by screen printing, a printing resist film of a screen printing screen used in screen printing has a corner near at least one corner of a portion corresponding to a bent portion. In addition, a corresponding enlarged space portion is provided which substantially expands a portion corresponding to the space portion. As a result, the bleeding of the printing paste can be absorbed in the enlarged space portion formed by the corresponding enlarged space portion and can be suppressed to the vicinity of at least one corner of the bent portion, so that a short circuit between adjacent wiring patterns can be prevented. it can.

【0008】[0008]

【発明の実施の形態】続いて、添付した図面を参照しつ
つ、本発明を具体化した実施の形態につき説明し、本発
明の理解に供する。ここに、図1(A)〜(E)はそれ
ぞれ本発明の第1の実施の形態に係る電子部品用配線基
板の製造方法の説明図、図2(A)〜(D)はそれぞれ
同電子部品用配線基板の回路パターンの形成方法を説明
する部分拡大平面図、図3(A)〜(C)はそれぞれ本
発明の第2の実施の形態に係る電子部品用配線基板の製
造方法で使用するスクリーン印刷用スクリーンの作製方
法の説明図、図4(A)〜(C)はそれぞれ同電子部品
用配線基板の製造方法で使用するスクリーン印刷用スク
リーンの部分拡大平面図、図5(A)〜(C)はそれぞ
れ同電子部品用配線基板の製造方法の説明図である。
BEST MODE FOR CARRYING OUT THE INVENTION Next, referring to the attached drawings, an embodiment in which the present invention is embodied will be described to provide an understanding of the present invention. Here, FIGS. 1 (A) to 1 (E) are explanatory views of a method for manufacturing a wiring board for electronic parts according to the first embodiment of the present invention, and FIGS. 2 (A) to 2 (D) are the same electronic drawings, respectively. 3A to 3C are partially enlarged plan views illustrating a method of forming a circuit pattern of a component wiring board, and FIGS. 3A to 3C are used in a method for manufacturing an electronic component wiring board according to a second embodiment of the present invention. 4A to 4C are partially enlarged plan views of the screen printing screen used in the method for manufacturing the electronic component wiring board, respectively, and FIG. (C) is an explanatory view of the manufacturing method of the wiring board for electronic components, respectively.

【0009】図1(A)〜(E)を参照しながら本発明
の第1の実施の形態に係る電子部品用配線基板の一例で
あるプラスチック配線基板10の製造方法を説明する。
図1(A)に示すように、BT樹脂(ビスマイレイミド
トリアジンを主成分にした樹脂)やポリイミド樹脂等の
高耐熱性、誘電特性、絶縁特性、加工性に優れた樹脂基
材11の両面に、銅の厚みが10〜70μmで、銅の純
度が99.8%以上の銅箔12を張って形成した導体層
を備えた1層又は多層の高耐熱性の銅張り樹脂基板13
を用いて、この銅張り樹脂基板13の所定の位置にスル
ーホール14をドリルやレーザー等を用いて穿孔する。
A method of manufacturing a plastic wiring board 10, which is an example of a wiring board for electronic parts according to the first embodiment of the present invention, will be described with reference to FIGS.
As shown in FIG. 1 (A), both surfaces of a resin base material 11 such as BT resin (a resin containing bismaleimide triazine as a main component) or polyimide resin having excellent heat resistance, dielectric properties, insulation properties, and processability. In addition, a single-layer or multi-layer high heat-resistant copper-clad resin substrate 13 having a conductor layer formed by stretching a copper foil 12 having a copper thickness of 10 to 70 μm and a copper purity of 99.8% or more.
Through holes 14 are drilled at predetermined positions of the copper-clad resin substrate 13 by using a drill or a laser.

【0010】次いで、銅張り樹脂基板13の銅箔12の
表面やスルーホール14の壁面等にパラジウム等の触媒
を付与後、ホルマリンを還元剤とする強アルカリ浴中で
無電解銅めっきを施すことで、スルーホール14の壁面
に形成された銅の導体膜を介して銅張り樹脂基板13の
両面表層を電気的に導通状態とする。そして、無電解銅
めっきの導体膜を介して、めっき浴中、例えば、硫酸
銅、ピロリン酸等のめっき浴中で陽極側に取付けられた
銅板が、陰極側に取付けられた被めっき物である銅張り
樹脂基板13に対向して配設し、銅板と銅張り樹脂基板
13の間に直流電源装置の電圧を印加することで、被め
っき物である銅張り樹脂基板13の無電解銅めっきが施
されている表層及びスルーホール14に金属銅を析出さ
せて電解銅めっきを施し、無電解銅めっき及び電解銅め
っきからなる銅めっき膜15を形成する。なお、この銅
めっき膜15は銅箔12の表面にも併せて形成される。
そして、銅めっき膜15の上に感光性のドライフィルム
16を貼着する。
Then, after applying a catalyst such as palladium to the surface of the copper foil 12 of the copper-clad resin substrate 13 and the wall surface of the through hole 14, electroless copper plating is performed in a strong alkaline bath using formalin as a reducing agent. Then, the both surface layers of the copper-clad resin substrate 13 are brought into an electrically conducting state via the copper conductor film formed on the wall surface of the through hole 14. Then, in the plating bath through the electroless copper-plated conductor film, for example, a copper plate attached to the anode side in a plating bath of copper sulfate, pyrophosphoric acid or the like is the object to be attached attached to the cathode side. The electroless copper plating of the copper-clad resin substrate 13 as the object to be plated is performed by arranging the copper-clad resin substrate 13 so as to face the copper-clad resin substrate 13 and applying the voltage of the DC power supply device between the copper plate and the copper-clad resin substrate 13. Metal copper is deposited on the surface layer and the through holes 14 that have been applied and electrolytic copper plating is applied to form a copper plated film 15 composed of electroless copper plating and electrolytic copper plating. The copper plating film 15 is also formed on the surface of the copper foil 12.
Then, a photosensitive dry film 16 is attached on the copper plating film 15.

【0011】次に、図1(B)、(C)に示すように、
エッチング用パターンマスク17をドライフィルム16
の上に当接させ、通常のフォトリソグラフィ法で紫外線
を照射して露光、現像を行ってドライフィルム16から
配線パターン19を有する所望の回路パターンを被覆す
る部分以外を除去して開口部20を有するエッチングレ
ジスト膜18を形成する。そして、塩化第2鉄溶液、塩
化第2銅溶液、アルカリエッチャント、過酸化水素−硫
酸系エッチャント等のエッチング液を噴射してエッチン
グ処理を行い、エッチングレジスト膜18の開口部20
から露出する銅箔12及び銅めっき膜15を除去する。
Next, as shown in FIGS. 1 (B) and 1 (C),
Etching pattern mask 17 is dry film 16
The exposed portion is exposed to ultraviolet rays by a normal photolithography method, exposed and developed to remove the portion other than the portion covering the desired circuit pattern having the wiring pattern 19 from the dry film 16 to form the opening 20. The etching resist film 18 having is formed. Then, an etching solution such as a ferric chloride solution, a cupric chloride solution, an alkaline etchant, a hydrogen peroxide-sulfuric acid-based etchant is sprayed to perform an etching process, and the opening 20 of the etching resist film 18 is formed.
The copper foil 12 and the copper plating film 15 exposed from the are removed.

【0012】次いで、図1(D)に示すように、エッチ
ングレジスト膜18の表面に剥離液を噴射して膨潤さ
せ、エッチングレジスト膜18を剥離して配線パターン
19を有する回路パターンを形成する。更に、図1
(E)に示すように、感光性のソルダーレジストをロー
ルコーターやスクリーン印刷等で塗布し、ソルダーレジ
スト用のパターンマスクを当接し、フォトリソグラフィ
法で紫外線露光、現像を行って、開口部22を有するソ
ルダーレジスト膜21を形成する。このソルダーレジス
ト膜21の開口部22から露出する部分には、Niめっ
き及びAuめっきが施され、ボンディングワイヤで半導
体素子と接続するためのワイヤボンドパッド23や、外
部接続端子用パッド24等を有するプラスチック配線基
板10を形成する。
Next, as shown in FIG. 1D, a stripping solution is sprayed on the surface of the etching resist film 18 to swell it, and the etching resist film 18 is stripped to form a circuit pattern having a wiring pattern 19. Furthermore, FIG.
As shown in (E), a photosensitive solder resist is applied by a roll coater, screen printing, or the like, a pattern mask for the solder resist is brought into contact, and ultraviolet exposure and development are performed by a photolithography method to open the opening 22. The solder resist film 21 having is formed. A portion of the solder resist film 21 exposed from the opening 22 is plated with Ni and Au, and has a wire bond pad 23 for connecting to a semiconductor element with a bonding wire, a pad 24 for an external connection terminal, and the like. The plastic wiring board 10 is formed.

【0013】前記プラスチック配線基板10の回路パタ
ーンは、並設された配線パターン19の一方に、例え
ば、隣り合う配線パターン19を一旦短絡させて、めっ
きを施すときに用いるめっき引き回しパターンである共
通線26を有し、最終的には、配線パターン19と共通
線26との接合部分で切断(図2(D)の符号28は切
断線を示す)して配線パターン19を分離独立させるよ
うになっている。この回路パターンをエッチング処理
(図1(C)参照)して形成するには、先ず、図2
(A)に示すように、エッチングで用いられるエッチン
グレジスト膜18を形成するためのエッチング用パター
ンマスク17をドライフィルム16上に配置する。この
エッチング用パターンマスク17には、配線パターン1
9に相当する部分19aと、共通線26に相当する部分
26aが接続される隅部に各配線パターン19の間に形
成されるスペース部25が更に広がる対応拡大スペース
部27が設けられている。
The circuit pattern of the plastic wiring board 10 is, for example, a common line which is a plating routing pattern used when plating is performed by short-circuiting adjacent wiring patterns 19 to one of the wiring patterns 19 arranged in parallel. 26, and finally the wiring pattern 19 and the common line 26 are cut at the junction (reference numeral 28 in FIG. 2D indicates a cutting line) to separate the wiring pattern 19 independently. ing. In order to form this circuit pattern by etching (see FIG. 1C), first, as shown in FIG.
As shown in (A), an etching pattern mask 17 for forming an etching resist film 18 used for etching is arranged on the dry film 16. This etching pattern mask 17 has a wiring pattern 1
A corresponding enlarged space portion 27 is provided at the corner where the portion 19a corresponding to 9 and the portion 26a corresponding to the common line 26 are connected and the space portion 25 formed between the wiring patterns 19 further expands.

【0014】そして、図2(B)に示すように、通常の
フォトリソグラフィ法で紫外線を照射して露光、現像を
行ってエッチング用パターンマスク17の被覆部分以外
(図中格子線で示す部分)を除去してドライフィルム1
6の開口部20から銅めっき膜15を露出させたエッチ
ングレジスト膜18を形成する。このエッチングレジス
ト膜18には、エッチング用パターンマスク17のパタ
ーンと同様に、配線パターン19に相当する部分と共通
線26に相当する部分が接続される隅部に、スペース部
25が更に拡がる対応拡大スペース部27aが設けられ
ている。
Then, as shown in FIG. 2B, a portion other than the covering portion of the pattern mask 17 for etching is exposed (exposure and developed by irradiation with ultraviolet rays by a normal photolithography method) (a portion indicated by a grid line in the drawing). To remove dry film 1
An etching resist film 18 exposing the copper plating film 15 from the opening 20 of 6 is formed. Similar to the pattern of the etching pattern mask 17, in the etching resist film 18, a space portion 25 further expands at the corner where the portion corresponding to the wiring pattern 19 and the portion corresponding to the common line 26 are connected. A space portion 27a is provided.

【0015】次いで、図2(C)に示すように、エッチ
ングレジスト膜18の開口部20から露出した銅めっき
膜15上にエッチング液を噴射させて銅めっき膜15及
び銅箔12を除去して樹脂基材11を露出させてスペー
ス部25を形成する。そして、エッチングレジスト膜1
8を剥離除去して配線パターン19の一方に共通線26
を有する回路パターンを形成する。このエッチング処理
では、エッチングレジスト膜18の対応拡大スペース部
27aによって、エッチング液がスペース部25の隅部
までよく流れるので、スペース部25と共通線26が接
続される隅部にエッチング未処理部が発生するのを防止
することができる。従って、図2(D)に示すように、
ソルダーレジスト膜21で被覆後、配線パターン19と
共通線26との接合部分を切断しても隣り合う配線パタ
ーン19の間の短絡の発生を防止することができる。な
お、上記の対応拡大スペース部27、27aの形状は、
円形、楕円形、三角形、角形、多角形、あるいはこれら
を組み合わせた形状等のいずれでもよく、特に限定する
ものではない。
Next, as shown in FIG. 2C, an etching solution is jetted onto the copper plating film 15 exposed from the opening 20 of the etching resist film 18 to remove the copper plating film 15 and the copper foil 12. The resin base material 11 is exposed to form the space portion 25. Then, the etching resist film 1
8 is peeled off to remove the common line 26 on one side of the wiring pattern 19.
Forming a circuit pattern having In this etching process, since the corresponding enlarged space portion 27a of the etching resist film 18 causes the etching solution to flow well to the corner of the space portion 25, an unetched portion is formed at the corner where the space portion 25 and the common line 26 are connected. It can be prevented from occurring. Therefore, as shown in FIG.
Even after cutting the joint between the wiring pattern 19 and the common line 26 after coating with the solder resist film 21, a short circuit between the adjacent wiring patterns 19 can be prevented. The shapes of the corresponding expansion space portions 27 and 27a are as follows.
The shape may be any of a circle, an ellipse, a triangle, a square, a polygon, or a combination thereof, and is not particularly limited.

【0016】次に、図3〜図5を参照して、本発明の第
2の実施の形態に係る電子部品用配線基板の一例である
セラミックパッケージ10aの製造方法を説明する。先
ず、セラミック粉末、例えばアルミナ(Al23 )粉
末にマグネシア、シリカ、カルシア等の焼結助剤を適当
量加えた粉末に、ジオキシルフタレート等の可塑剤と、
アクリル樹脂等のバインダー、及びトルエン、キシレ
ン、アルコール類等の溶剤を加え、十分に混練し、脱泡
して粘度2000〜40000cpsのスラリーを作製
し、ドクターブレード法等によって、例えば厚み0.3
mmのロール状のシートを形成し、適当なサイズにカッ
トして複数枚の矩形状のセラミックグリーンシート29
(図5参照)を作製する。そして、各セラミックグリー
ンシート29には、打ち抜き型やNCパンチングマシー
ン等を用いて、複数のスルーホールやスクリーン印刷の
位置合わせ用孔等や、半導体素子等の電子部品を搭載す
る部分となるキャビティ部を形成するための孔を穿設す
る。
Next, a method of manufacturing the ceramic package 10a, which is an example of the electronic component wiring board according to the second embodiment of the present invention, will be described with reference to FIGS. First, a ceramic powder, for example, alumina (Al 2 O 3 ) powder, to which a suitable amount of a sintering aid such as magnesia, silica, or calcia is added, and a plasticizer such as dioxyl phthalate,
A binder such as an acrylic resin and a solvent such as toluene, xylene, alcohols, etc. are added, sufficiently kneaded, and defoamed to prepare a slurry having a viscosity of 2000 to 40,000 cps.
mm-shaped roll-shaped sheet, cut into an appropriate size, and formed into a plurality of rectangular ceramic green sheets 29.
(See FIG. 5). Then, a punching die, an NC punching machine or the like is used for each ceramic green sheet 29 to form a plurality of through holes, positioning holes for screen printing, etc., and a cavity portion for mounting electronic components such as semiconductor elements. A hole for forming the is formed.

【0017】一方、図3(A)〜(C)に示すように、
セラミック基材となるセラミックグリーンシート29上
にスクリーン印刷するのに用いられるスクリーン印刷用
スクリーン30は、例えば、ポリエステル、ナイロン、
テトロン等の合成繊維やステンレスの細線からなる縦線
と横線を交互に織って網目状にしたスクリーンメッシュ
31をスクリーン版枠に貼り付けて固定し、両面に感光
性乳剤32を塗布し、乾燥して付着させる。次に、感光
性乳剤32が付着したスクリーンメッシュ31の被スク
リーン印刷材に接する面側に感光用パターンマスク33
を当接し、露光と現像を行って所望とする配線パターン
40(図5(B)参照)となる部分の感光性乳剤32を
除去してスクリーンパターンを形成する。そして、残っ
た感光性乳剤を硬化させて印刷用レジスト膜34を形成
して作製している。
On the other hand, as shown in FIGS. 3 (A) to 3 (C),
The screen-printing screen 30 used for screen-printing on the ceramic green sheet 29 serving as a ceramic substrate is, for example, polyester, nylon,
A screen mesh 31 formed by alternately weaving vertical and horizontal lines made of synthetic fibers such as tetoron or fine wires of stainless steel is attached and fixed to a screen plate frame, and a photosensitive emulsion 32 is applied on both sides and dried. To attach. Next, a photosensitive pattern mask 33 is formed on the surface side of the screen mesh 31 to which the photosensitive emulsion 32 is attached, in contact with the screen printing material.
Are exposed to light and developed to remove a portion of the photosensitive emulsion 32 which becomes a desired wiring pattern 40 (see FIG. 5B) to form a screen pattern. Then, the remaining photosensitive emulsion is cured to form a printing resist film 34, which is manufactured.

【0018】この印刷用レジスト膜34を用いてスクリ
ーン印刷によりセラミック基材上に、実質的に直角に曲
がる屈曲部を有し、隣り合う配線パターン40が狭幅の
スペース部を介して近接する回路パターンを形成する場
合に、図4(A)に示すように、屈曲部に対応する部分
35の少なくとも一方の角部付近に、スペース部に対応
する部分36を実質的に広げる対応拡大スペース部37
を設けている。また、図4(B)に示すように、屈曲部
に対応する部分35で他方の角部付近にスペース部に対
応する部分36を実質的に広げる対応拡大スペース部3
7aを設けることもできる。更に、図4(C)に示すよ
うに、屈曲部に対応する部分35での両方の角部付近に
平面視して対応拡大スペース部37b、37cを設ける
こともできる。なお、これらの対応拡大スペース部の形
状は、特に限定されるものではない。
A circuit having a bent portion which is bent at a substantially right angle on a ceramic substrate by screen printing using this resist film 34 for printing, and adjacent wiring patterns 40 are adjacent to each other via a narrow space portion. When forming a pattern, as shown in FIG. 4A, a corresponding enlarged space portion 37 that substantially expands a portion 36 corresponding to the space portion near at least one corner of the portion 35 corresponding to the bent portion.
Is provided. In addition, as shown in FIG. 4B, the corresponding enlarged space portion 3 that substantially expands the portion 36 corresponding to the space portion in the portion 35 corresponding to the bent portion in the vicinity of the other corner portion.
7a can also be provided. Further, as shown in FIG. 4C, corresponding enlarged space portions 37b and 37c can be provided near both corners of the portion 35 corresponding to the bent portion in plan view. The shape of the corresponding expansion space portion is not particularly limited.

【0019】次いで、図5(A)、(B)に示すよう
に、セラミックグリーンシート29の表面に、スクリー
ン印刷用スクリーン30を当接する。そして、印刷ペー
スト38をスキージ39で印刷用レジスト膜34の開口
部から押し出して印刷することで配線パターン40を有
する回路パターンを形成する。対応拡大スペース部を設
けることで印刷ペースト38の滲みをこの部分で吸収で
き、隣接する配線パターン間の短絡を防止することがで
きる。その後、図5(C)に示すように、配線パターン
40の形成された複数枚のセラミックグリーンシート2
9を積み重ね、加熱圧着して積層体を形成し、約155
0℃の還元性雰囲気中で焼成してセラミックパッケージ
10aを製造する。
Next, as shown in FIGS. 5A and 5B, a screen printing screen 30 is brought into contact with the surface of the ceramic green sheet 29. Then, the printing paste 38 is extruded from the opening of the printing resist film 34 with a squeegee 39 to print, thereby forming a circuit pattern having a wiring pattern 40. By providing the corresponding enlarged space portion, the bleeding of the printing paste 38 can be absorbed in this portion, and a short circuit between adjacent wiring patterns can be prevented. Then, as shown in FIG. 5C, the plurality of ceramic green sheets 2 on which the wiring patterns 40 are formed are formed.
9 are stacked and thermocompression bonded to form a laminated body.
The ceramic package 10a is manufactured by firing in a reducing atmosphere at 0 ° C.

【0020】[0020]

【発明の効果】請求項1記載の電子部品用配線基板の製
造方法は、エッチング処理に用いるエッチングレジスト
膜を形成するためのパターンマスクに、配線パターンに
相当する部分と、共通線に相当する部分が接続される隅
部に、各配線パターンの間に形成されるスペース部が更
に広がる対応拡大スペース部を設けたので、エッチング
液が対応拡大スペース部の隅部付近まで流れやすくな
り、エッチング未処理部分の発生を防止してエッチング
処理が行える。従って、例えばめっき引き回しパターン
である配線パターンの共通線をエッチング処理後に切断
した後、エッチング未処理部分が残らず、製品部の隣り
合う配線パターンの間の短絡の発生を防止することがで
きる。
According to the first aspect of the present invention, there is provided a method of manufacturing a wiring board for an electronic component, wherein a pattern mask for forming an etching resist film used in an etching process has a portion corresponding to a wiring pattern and a portion corresponding to a common line. Since the corresponding enlarged space portion that further expands the space portion formed between each wiring pattern is provided at the corner where the wiring pattern is connected, the etching liquid easily flows to the vicinity of the corner of the corresponding enlarged space portion, and the etching is not processed. The etching process can be performed by preventing the generation of a portion. Therefore, for example, after the common line of the wiring pattern, which is the plating lead-out pattern, is cut after the etching process, no unetched portion remains, and it is possible to prevent the occurrence of a short circuit between the adjacent wiring patterns of the product portion.

【0021】請求項2記載の電子部品用配線基板の製造
方法は、スクリーン印刷で用いられるスクリーン印刷用
スクリーンの印刷用レジスト膜には、屈曲部に対応する
部分の少なくとも一方の角部付近に、スペース部に対応
する部分を実質的に広げる対応拡大スペース部を設けた
ので、印刷ペーストの滲みを対応拡大スペース部で吸収
でき、屈曲部の少なくとも一方の角部付近までで抑えら
れるので、隣接する配線パターン間の短絡の発生を防止
することができる。
According to a second aspect of the present invention, there is provided a method of manufacturing a wiring board for an electronic component, wherein a printing resist film of a screen printing screen used in screen printing has at least one corner of a portion corresponding to a bent portion near a corner. Since the corresponding enlarged space portion that substantially expands the portion corresponding to the space portion is provided, the bleeding of the printing paste can be absorbed in the corresponding enlarged space portion, and it can be suppressed near at least one corner of the bent portion, so it is adjacent It is possible to prevent a short circuit between the wiring patterns.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)〜(E)はそれぞれ本発明の第1の実施
の形態に係る電子部品用配線基板の製造方法の説明図で
ある。
1A to 1E are explanatory views of a method for manufacturing an electronic component wiring board according to a first embodiment of the present invention.

【図2】(A)〜(D)はそれぞれ同電子部品用配線基
板の回路パターンの形成方法を説明する部分拡大平面図
である。
2A to 2D are partially enlarged plan views illustrating a method of forming a circuit pattern on the electronic component wiring board.

【図3】(A)〜(C)はそれぞれ本発明の第2の実施
の形態に係る電子部品用配線基板の製造方法で使用する
スクリーン印刷用スクリーンの作製方法の説明図であ
る。
3A to 3C are explanatory views of a method for producing a screen printing screen used in a method for producing an electronic component wiring board according to a second embodiment of the present invention.

【図4】(A)〜(C)はそれぞれ同電子部品用配線基
板の製造方法で使用するスクリーン印刷用スクリーンの
部分拡大平面図である。
FIG. 4A to FIG. 4C are partially enlarged plan views of screen printing screens used in the method for manufacturing the same electronic component wiring board.

【図5】(A)〜(C)はそれぞれ同電子部品用配線基
板の製造方法の説明図である。
5A to 5C are explanatory views of a method for manufacturing the same electronic component wiring board.

【図6】(A)〜(E)は従来の電子部品用配線基板の
製造方法の説明図である。
6A to 6E are explanatory views of a conventional method for manufacturing a wiring board for electronic parts.

【図7】(A)、(B)は従来の電子部品用配線基板の
製造方法の説明図である。
7A and 7B are explanatory views of a conventional method for manufacturing a wiring board for electronic parts.

【図8】(A)、(B)は従来の電子部品用配線基板の
製造方法の説明図である。
8A and 8B are explanatory views of a conventional method for manufacturing a wiring board for electronic components.

【符号の説明】[Explanation of symbols]

10:プラスチック配線基板、10a:セラミックパッ
ケージ、11:樹脂基材、12:銅箔、13:銅張り樹
脂基板、14:スルーホール、15:銅めっき膜、1
6:ドライフィルム、17:エッチング用パターンマス
ク、18:エッチングレジスト膜、19:配線パター
ン、19a:配線パターンに相当する部分、20:開口
部、21:ソルダーレジスト膜、22:開口部、23:
ワイヤボンドパッド、24:外部接続端子用パッド、2
5:スペース部、26:共通線、26a:共通線に相当
する部分、27、27a:対応拡大スペース部、28:
切断線、29:セラミックグリーンシート、30:スク
リーン印刷用スクリーン、31:スクリーンメッシュ、
32:感光性乳剤、33:感光用パターンマスク、3
4:印刷用レジスト膜、35:屈曲部に対応する部分、
36:スペース部に対応する部分、37、37a、37
b、37c:対応拡大スペース部、38:印刷ペース
ト、39:スキージ、40:配線パターン
10: Plastic wiring board, 10a: Ceramic package, 11: Resin base material, 12: Copper foil, 13: Copper-clad resin board, 14: Through hole, 15: Copper plating film, 1
6: Dry film, 17: Pattern mask for etching, 18: Etching resist film, 19: Wiring pattern, 19a: Portion corresponding to wiring pattern, 20: Opening portion, 21: Solder resist film, 22: Opening portion, 23:
Wire bond pad, 24: Pad for external connection terminal, 2
5: space part, 26: common line, 26a: part corresponding to common line, 27, 27a: corresponding expanded space part, 28:
Cutting line, 29: Ceramic green sheet, 30: Screen for screen printing, 31: Screen mesh,
32: Photosensitive emulsion, 33: Photosensitive pattern mask, 3
4: resist film for printing, 35: a portion corresponding to the bent portion,
36: parts corresponding to the space part, 37, 37a, 37
b, 37c: corresponding expansion space portion, 38: print paste, 39: squeegee, 40: wiring pattern

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/12 H05K 3/12 610P H05K 3/12 610 H01L 23/12 D Fターム(参考) 2C035 AA06 FF24 FF26 4K057 WA11 WB04 WB17 WC10 WE08 WN01 5E339 AB02 AD03 BC02 BD07 BE11 BE13 CD01 CE12 CE16 CF15 EE02 GG02 5E343 AA02 AA12 AA15 AA17 BB72 CC62 DD03 ER12 ER16 FF12 GG06 GG08 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 23/12 H05K 3/12 610P H05K 3/12 610 H01L 23/12 DF term (reference) 2C035 AA06 FF24 FF26 4K057 WA11 WB04 WB17 WC10 WE08 WN01 5E339 AB02 AD03 BC02 BD07 BE11 BE13 CD01 CE12 CE16 CF15 EE02 GG02 5E343 AA02 AA12 AA15 AA17 BB72 CC62 DD03 ER12 ER16 FF12 GG06 GG08

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 並設された配線パターンの一方に共通線
を有し、最終的には、前記配線パターンと前記共通線と
の接合部分で前記各配線パターンを分離独立させる回路
パターンをエッチング処理によって形成する電子部品用
配線基板の製造方法において、前記エッチング処理に用
いるエッチングレジスト膜を形成するためのパターンマ
スクに、前記配線パターンに相当する部分と、前記共通
線に相当する部分が接続される隅部に、前記各配線パタ
ーンの間に形成されるスペース部が更に広がる対応拡大
スペース部を設けたことを特徴とする電子部品用配線基
板の製造方法。
1. An etching process of a circuit pattern having a common line on one of the wiring patterns arranged in parallel and finally separating and separating the respective wiring patterns at a joint portion between the wiring pattern and the common line. In a method of manufacturing a wiring board for electronic parts formed by, a portion corresponding to the wiring pattern and a portion corresponding to the common line are connected to a pattern mask for forming an etching resist film used in the etching process. A method of manufacturing a wiring board for an electronic component, characterized in that a corresponding enlarged space portion is provided in a corner portion to further expand a space portion formed between the wiring patterns.
【請求項2】 セラミック基材上に、屈曲部を有し、隣
り合う配線パターンが狭幅のスペース部を介して近接す
る回路パターンをスクリーン印刷を用いて形成する電子
部品用配線基板の製造方法において、前記スクリーン印
刷で用いられるスクリーン印刷用スクリーンの印刷用レ
ジスト膜には、前記屈曲部に対応する部分の少なくとも
一方の角部付近に、前記スペース部に対応する部分を実
質的に広げる対応拡大スペース部を設けたことを特徴と
する電子部品用配線基板の製造方法。
2. A method of manufacturing a wiring board for an electronic component, which has a bent portion on a ceramic substrate, and a circuit pattern in which adjacent wiring patterns are adjacent to each other through a narrow space portion is formed by screen printing. In the printing resist film of the screen printing screen used in the screen printing, in the vicinity of at least one corner of the portion corresponding to the bent portion, substantially expand the portion corresponding to the space portion. A method of manufacturing a wiring board for an electronic component, characterized in that a space portion is provided.
JP2001229777A 2001-07-30 2001-07-30 Manufacturing method of wiring board for electronic parts Expired - Fee Related JP4137412B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001229777A JP4137412B2 (en) 2001-07-30 2001-07-30 Manufacturing method of wiring board for electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001229777A JP4137412B2 (en) 2001-07-30 2001-07-30 Manufacturing method of wiring board for electronic parts

Publications (2)

Publication Number Publication Date
JP2003046221A true JP2003046221A (en) 2003-02-14
JP4137412B2 JP4137412B2 (en) 2008-08-20

Family

ID=19062077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001229777A Expired - Fee Related JP4137412B2 (en) 2001-07-30 2001-07-30 Manufacturing method of wiring board for electronic parts

Country Status (1)

Country Link
JP (1) JP4137412B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2016021543A (en) * 2014-07-15 2016-02-04 ▲き▼邦科技股▲分▼有限公司 Circuit board

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JP2015198108A (en) * 2014-03-31 2015-11-09 凸版印刷株式会社 Printed wiring board and method of manufacturing the same and photogravure cylinder
JP2016021543A (en) * 2014-07-15 2016-02-04 ▲き▼邦科技股▲分▼有限公司 Circuit board

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