JP2003037502A - Device and method for processing digital signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for processing digital signal, which does not allow a D/A converter to generate noises even during IEEE1394 transmission and a mode transition, by transmitting continued 1-bit mute patterns from the output of the D/A converter. SOLUTION: When an IEEE1394 bus is connected to an IEEE1394 interface 10 and a microcomputer 16 detects the connection, the microcomputer 16 sends a control signal S1 according to the connection to a controller 11. This switches audio signal reproduction by a D/A converter 9 to IEEE1394 data transmission. a switch 8 switches the 1-bit mute pattern signal a, generated by a mute pattern generator 4, to a 1-bit mute pattern signal b, generated by a mute pattern generator 5 and delayed by a delay line 7, at a specified timing depending on a control signal S2 from the controller 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing method and apparatus, and more particularly to a digital signal processing apparatus and method for performing digital signal processing on a delta-sigma modulated high speed 1-bit signal.

[0002]

2. Description of the Related Art A ΔΣ-modulated high-speed 1-bit audio signal is a data format used in conventional digital audio (for example, a sampling frequency of 44.
Compared with 1kHz, data word length 16 bits), it has a very high sampling frequency and a short data word length (for example, the sampling frequency is 64 times 44.1kHz and the data word length is 1 bit). It features a possible frequency band. Further, even if it is a 1-bit signal by ΔΣ modulation, since it has an oversampling frequency of 64 times, it is possible to secure a high dynamic range in the low audio band. Utilizing this feature, it can be applied to high-quality sound recorders and data transmission.

The ΔΣ modulation circuit itself is not a new technology, its circuit configuration is suitable for integration, and the accuracy of analog-digital (AD) conversion can be obtained relatively easily. It is a circuit that is often used in.

The ΔΣ-modulated signal can be returned to an analog audio signal by passing through a simple analog low-pass filter.

[0005]

By the way, in an apparatus for reproducing and transmitting a 1-bit audio signal, in addition to data transmission to a digital-analog (D / A) converter, it is considered to transmit data from an IEEE1394 interface. To be When a 1-bit audio signal is output and transmitted from the IEEE1394 interface, depending on the mode, the transmitted data is transferred based on the clock on the IEEE1394 receiver side, so that non-linear transmission in which the transfer rate varies with time is performed.

On the other hand, the D / A converter always converts 1-bit digital data into an analog signal with a linear clock and reproduces it as an audio signal.
The 1-bit data output of the / A converter system always requires linear data transmission. Here, during the IEEE1394 transmission output, if this non-linear data is simultaneously transmitted as it is from the D / A converter system output, the reproduced audio signal becomes a signal covered with noise. Therefore, it is necessary to mute the D / A system output by the mute pattern data during the IEEE1394 transmission output.
Even if you play a non-linear mute pattern as it is,
After all, there was a problem that it became an audio signal mixed with noise.

The present invention has been made in view of the above situation, and by transmitting a continuous 1-bit mute pattern from the output of the D / A converter, noise is also generated from the D / A converter during IEEE1394 transmission and mode transition. It is an object of the present invention to provide a digital signal processing device and a digital signal processing method that can prevent the generation.

[0008]

In order to solve the above-mentioned problems, a digital signal processing apparatus according to the present invention generates a 1-bit digital signal of a mute signal pattern.
Mute signal generating means, crossfade processing means for performing crossfade processing on the input 1-bit digital signal and the 1-bit digital signal of the mute signal pattern output from the first mute signal generating means, and outputting the result. Second mute signal generating means for generating a 1-bit digital signal of the signal pattern, 1-bit digital signal output from the crossfade processing means, and 1 of the mute signal pattern generated by the second mute signal generating means. Switching means for switching the bit digital signal, D / A conversion means for D / A converting the 1-bit digital signal output from the switching means, and variable transfer of the 1-bit digital signal output from the crossfade processing means. Communication processing means for converting the rate and transferring the data; Mute output from the first mute signal generation means for muting the output from the D / A conversion means while the 1-bit digital signal from the fade processing means is output from the communication processing means at a variable transfer rate. And a control means for controlling the switching means so as to switch the signal pattern to the mute signal pattern output from the second mute signal generating means at a predetermined timing.

In order to solve the above-mentioned problems, the digital signal processing method according to the present invention includes a first mute signal generating step of generating a 1-bit digital signal having a mute signal pattern, and an input 1-bit digital signal. And a crossfade processing step of crossfading the 1-bit digital signal of the mute signal pattern output from the first mute signal generation step, and outputting the crossfade processing, and a second mute for generating the 1-bit digital signal of the mute signal pattern. A signal generating step, a switching step of switching between the 1-bit digital signal output from the crossfade processing step and the 1-bit digital signal of the mute signal pattern generated in the second mute signal generating step, and the switching step D / A conversion of output 1-bit digital signal And a communication processing step of converting the 1-bit digital signal output from the crossfade processing step into a variable transfer rate and transferring the variable signal, and the switching step is performed by the switching step from the crossfade processing step. While outputting a 1-bit digital signal from the communication processing step at a variable transfer rate, the mute signal pattern output from the first mute signal generating step is muted to mute the output from the D / A converting step. The mute signal pattern output from the second mute signal generation step is controlled to be switched at a predetermined timing.

As described above, the digital signal processing apparatus and method according to the present invention has a linear mute pattern generating means independent of the non-linear mute pattern generating means, and the communication processing means outputs, for example, IEEE1394 transmission output. At the time of execution, the D / A system output data is switched to the mute pattern data from the linear mute pattern generating means to output the linear mute pattern. When the IEEE1394 transmission is terminated and the data is switched to the reproduction system data again, after crossfading the reproduction system data with the mute pattern, the phase of the mute pattern of the mute pattern generator and the mute pattern of the reproduction system is set to the rate of the reproduction system device. By controlling, by synchronizing, the D / A system output is switched to the reproduction system mute pattern signal, so that the mode can be transited without generating noise from the D / A system output.

As a result, the D / A system output can always output a continuous 1-bit signal, which solves the above problem.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A digital signal reproducing / transmitting apparatus as an embodiment of a digital signal processing apparatus and a digital signal processing method according to the present invention will be described below.
The digital signal reproduction / transmission device 1 shown in FIG. 1 transmits a ΔΣ-modulated 1-bit signal obtained from the 1-bit signal reproduction device 3 to a D / A converter 9 described later to reproduce an audio signal. Output (linear transmission) system,
IEEE 1394 transmission output (non-linear transmission) for transmitting the 1-bit signal from the IEEE 1394 interface 10 described later
It has two output systems.

D / A transmission output (linear transmission) system D / A
The analog audio signal output S4 converted by the converter 9 is sent to a volume controller (not shown) via the output terminal 12 to be volume-controlled, amplified by an amplifier, and then supplied to a speaker or headphones.

IEEE 1394 transmission output (non-linear transmission) system
The 1-bit data S5 transmitted from the IEEE1394 interface 10 is sent from the IEEE1394 output terminal 13 to the IEEE1394 receiver via the IEEE1394 bus. IEEE1394
The receiving device may be an amplifying device, a personal computer, or the like. Here, 1-bit data is supplied to the IEEE1394 transmission output (non-linear transmission) system when the IEEE1394 bus is connected to the IEEE1394 output terminal 13, that is, IE.
EE1394 cable is the digital signal reproduction and transmission equipment and IE
This is when the EE1394 receiver is connected. At this time, D /
In the A transmission output (linear transmission) system, the ΔΣ-modulated 1-bit signal obtained from the 1-bit signal reproducing device 3 is muted. The D / A transmission output (linear transmission) system transmits a mute pattern signal described later. Detailed operation of this will be described later.

First, the configuration of the digital signal reproducing and transmitting apparatus 1 will be described. This digital signal reproduction / transmission apparatus 1 has a linear 1 in a D / A transmission output (linear transmission) system.
Non-linear operable block 2 that transmits a 1-bit digital signal non-linearly to the IEEE1394 transmission output (non-linear transmission) system while transmitting a bit digital signal
Is equipped with. The non-linearly operable block 2 includes a 1-bit signal reproducing device 3 for reproducing a 1-bit digital signal from, for example, an optical disk described later, a mute pattern generator 4 for generating a 1-bit digital signal M1 of a mute signal pattern, and a 1-bit signal reproduction. The cross-fade device 5 cross-fade and outputs the 1-bit digital signal reproduced by the device 3 and the 1-bit digital signal M1 of the mute signal pattern generated by the mute pattern generator 4.

Further, the digital signal reproducing / transmitting apparatus 1 is
A mute pattern generator 6 (second mute signal generating means) for generating a 1-bit digital signal M0 of the mute signal pattern, and a delay line 7 for delaying the 1-bit digital signal M0 of the mute signal pattern from the mute pattern generator 6. A switching device 8 for switching between the 1-bit digital signal M0 of the mute signal pattern delayed by the delay line 7 and the crossfade reproduction signal from the crossfade device 5, and a switching device 8
The D / A converter 9 for converting the 1-bit digital signal S3 output from the analog signal into an analog signal, and the 1-bit digital signal output from the crossfade device 5 at a fixed transfer rate are converted into a variable transfer rate for IEEE1394 and transferred. And an IEEE 1394 interface 10 that operates.

Further, the digital signal reproducing and transmitting apparatus 1 is
While the 1-bit digital signal from the crossfade device is being output from the IEEE 1394 interface 10 at a variable transfer rate, one of the mute signal patterns output from the mute pattern generator 4 for muting the output from the D / A converter 9 is output. And a controller 11 for supplying a switching control signal S2 to the switching device 8 so as to switch the bit digital signal M1 to the mute signal pattern M0 output from the mute pattern generator 6 at a predetermined timing. There is. The control device 11 is supplied with a microcomputer control signal S1 from an external microcomputer 16.

The microcomputer 16 detects whether or not the IEEE1394 bus is connected to the IEEE1394 interface 10, and the microcomputer control signal S is detected based on the detection result.
1 is generated and supplied to the control device 11.

As shown in FIG. 2, the 1-bit signal reproducing device 3 reproduces the 1-bit digital signal from the optical disc 20 on which the 1-bit digital signal is recorded, through the optical pickup 21, the RF amplifier 23 and the demodulation decoder 28. Then, the reproduced 1-bit digital signal is supplied to the crossfade device 5.

The detailed structure of the 1-bit signal reproducing apparatus 3 will be described below. A CLV processor 30 generates a CLV control signal in response to a timing signal generated by a timing generation circuit 29 from an RF signal generated by an RF amplifier 23, which will be described later, and the spindle motor 22 rotates the optical disc 20 by CLV in response to the CLV control signal. To do.

The optical disc 20 rotated by the spindle motor 22 is irradiated with reproduction laser light from the optical pickup 21 to read a signal, and the read signal is supplied to the RF amplifier 23.

The RF amplifier 23 generates a reproduction signal from the read signal to generate a PLL circuit 27 and a demodulation decoder 28.
And to the timing generation circuit 29. The RF amplifier 23 also generates a tracking error signal and a focus error signal from the read signal and supplies them to the servo signal processing circuit 24.

The servo signal processing circuit 24 includes the RF amplifier 2
The reproduction laser light from the optical pickup 21 is caused to follow the optical disc 20 based on the tracking error signal and the focus error signal supplied from the optical disc 20.

The PLL circuit 27 generates a clock signal from the reproduction signal from the RF amplifier 23, and the demodulation decoder 28
Supply to.

The demodulation decoder 28 demodulates the reproduced signal based on the clock signal from the PLL circuit 27 and supplies the demodulated data to the crossfade device 5.

In FIG. 2, the microcomputer 16 also controls the servo processing of the servo signal processing device 24. Further, in FIG.
Includes a memory unit 17 for storing auxiliary information and the operation unit 1.
8 and the display unit 19 are connected.

Next, the mute pattern generator 4 generates a 1-bit mute signal pattern consisting of, for example, repeating "1,0,0,1,0,1,1,0". In particular, the mute pattern generator 4 is
When it is detected that the IEEE1394 bus is connected to the IEEE1394 interface 10, the 1-bit mute signal pattern can be generated non-linearly.

The crossfade device 5 is a 1-bit digital signal reproduced by the 1-bit signal reproducing device 3 under the control of the control device 11 and a 1-bit digital signal of the mute signal pattern generated by the mute pattern generator 4. The signal M1 is cross-faded and output.

The mute pattern generator 6 linearly generates a 1-bit mute signal pattern consisting of repeating "1,0,0,1,0,1,1,0", for example.

The delay line 7 delays the 1-bit digital signal M0 of the mute signal pattern from the mute pattern generator 6 by the delay time by the crossfade process when the crossfade device 5 is performing the crossfade process. To do.

The switching device 8 switches between the 1-bit digital signal M0 of the mute signal pattern delayed by the delay line 7 and the crossfade reproduction signal from the crossfade device 5 under the control of the control device 11 to switch the D / D signal. Supply to the A converter 9.

The D / A converter 9 is used when the IEEE1394 bus is not connected to the IEEE1394 output terminal 13, that is, IE.
EE1394 cable is the digital signal reproduction and transmission equipment and IE
When not connected to the EE1394 receiver, the 1-bit signal reproducing device 3 converts the 1-bit digital signal reproduced from the optical disc 1 into an analog audio signal and outputs it. However, the IEEE1394 output terminal 13 is connected to the IEEE1394 bus. During this time, the mute pattern signal switched by the switching device 8 is converted into an analog signal and output.

The IEEE1394 interface 10 converts the 1-bit digital signal output from the crossfade device 5 into a variable transfer rate for IEEE1394 according to the request command Cr supplied from the IEEE1394 receiver to the command input terminal 14, and the IEEE1394 variable transfer rate. Transfer to the IEEE1394 receiver side via the bus.

Next, the operation of the digital signal reproducing / transmitting apparatus 1 will be described with reference to the timing chart of FIG. First, when the user uses the operation unit 18 connected to the microcomputer 16 to reproduce an analog audio signal from the D / A converter 9 of the D / A transmission output (linear transmission) system, the following operation is performed. It becomes as follows.

D / A transmission output (linear transmission) system D / A
When the analog audio signal is reproduced by the converter 9, the 1-bit signal reproducing device 3 linearly reproduces the 1-bit digital signal S3, and the crossfade device 5
Also, linear transmission is performed to the D / A converter 9 through the switching device 8. As a result, the D / A converter 9
From, a continuous analog audio signal S4 can be obtained.

Next, the IEEE 1394 interface 10 has an IE
The EE1394 bus is connected and it is connected to the microcomputer 1
When detected by 6, the microcomputer 16 sends a microcomputer control signal S1 corresponding to the connection to the control device 11.
As a result, the audio signal reproduction by the D / A converter 9 is switched to the data transmission by IEEE1394.

The control device 11 receives the microcomputer control signal S1 corresponding to the result of detecting the connection of the IEEE1394 bus to the IEEE1394 interface 10 and controls the crossfade device 5 of the non-linearly operable block 2. Specifically, when the audio signal reproduction by the D / A converter 9 is switched to the data transmission by IEEE1394, the control device 11 which receives the microcomputer control signal S1 shows the crossfade device reproduction signal level L in FIG. To 1
A 1-bit digital signal obtained from the bit signal reproducing device 3 and a 1-bit mute pattern signal generated by the mute pattern generator 4 (shown by a broken line in FIG. 3)
And cross-fade with the cross-fade device 5.

The crossfade by the crossfade device 5 is performed according to the digital signal processing method disclosed by the applicant of the present application in Japanese Patent Application Laid-Open No. 9-307452. Briefly, the 1-bit digital signal obtained from the 1-bit signal reproducing device 3 and the mute pattern generator 4
This is a technique in which after matching the level with the 1-bit mute pattern signal generated by, the pattern matching over a plurality of samples is detected and switching is performed according to the detection result.

Here, the phases of the 1-bit mute pattern signals generated by the mute pattern generator 4 and the mute pattern generator 6 are previously synchronized so as to be the same. In addition, the delay line 7 provides a delay equivalent to the delay of the crossfade device 5, so that the phases of both 1-bit mute patterns reaching the switching device 8 are aligned.

Then, the control signal S2 from the controller 11
The switching device 8 generates a 1-bit mute pattern signal a (denoted as mute pattern A in FIG. 3) generated by the mute pattern generator 4 by the mute pattern generator 5 at a predetermined timing based on The signal is switched to the 1-bit mute pattern signal b delayed on line 7 (denoted as mute pattern B in FIG. 3). At this time, since the phases of the mutual mute pattern signals are synchronized, a continuous analog mute signal can be obtained from the D / A converter 10.

The crossfade device 5 again performs a crossfade process from the 1-bit mute pattern signal generated by the mute pattern generator 4 to the 1-bit signal obtained by the 1-bit signal reproducing device 3, and after the crossfade process. The 1-bit signal is transmitted to the IEEE1394 interface 10.

Here, the non-linearly operable block 2 including the 1-bit signal reproducing device 3, the crossfade device 5, and the mute pattern generator 4 and the IEEE1394 interface 10 have a non-linearly operable structure. Therefore, after the switching device 8 switches the signal to the D / A converter 9 to the 1-bit mute pattern signal generated by the mute pattern generator 6, the 1-bit digital signal of the 1-bit signal reproducing device 3 is transferred to the IEEE1394 interface 10. To perform non-linear transmission (described as a non-linear transmission period in FIG. 3).

At this time, since the 1-bit mute pattern signal b (mute pattern B) generated by the mute pattern generator 6 is linearly transmitted to the D / A converter 9, a continuous analog mute signal is always obtained. You can

Next, the IEEE1394 interface 10 and IE
The operation of the digital signal reproduction / transmission device 1 when the EE1394 bus is disconnected will be described. When the microcomputer 16 detects disconnection of the IEEE1394 bus for the IEEE1394 interface 10, the microcomputer 16 sends a microcomputer control signal S1 corresponding to the disconnection to the control device 11. As a result, the data transmission by IEEE1394 is switched to the audio signal reproduction by the D / A converter 9.
Details are shown below.

The control device 11 receives the microcomputer control signal S1 corresponding to the disconnection, controls the crossfade device 5, and generates the 1-bit signal obtained from the 1-bit signal reproducing device 3 and the mute pattern generator 4. Cross fades with the 1-bit mute pattern signal.

Here, the phases of the 1-bit mute pattern signal generated by the mute pattern generator 4 and the 1-bit mute pattern signal generated by the mute pattern generator 6 are the phases after the non-linearly operable block 2 is non-linearly operated. Do not match because.

Therefore, by controlling the rate of the non-linearly operable block 2 by the controller 11 so that the phases of both 1-bit mute patterns coincide with each other, the phase synchronization processing of the mute patterns is performed, and when they are synchronized, the linear operation is performed thereafter. I do. A period during which the phase synchronization processing of the mute pattern is performed is shown in FIG. 3 as a mute pattern synchronization processing period.

In this state, the switching device 8 has the mute pattern generator 6 delayed by the delay line 10.
The 1-bit mute pattern signal from 1 is switched to the 1-bit mute pattern signal generated by the mute pattern generator 4. At this time, since the phases of the mute pattern signals are synchronized with each other, the output of the D / A converter 9 becomes a continuous analog mute signal.

The crossfade device 5 again performs a crossfade process from the 1-bit mute pattern signal generated by the mute pattern generator 4 to the 1-bit signal obtained by the 1-bit signal reproducing device 3. As a result, a continuous analog audio signal output reproduced by the 1-bit signal reproducing device 3 can be obtained from the D / A converter 9. This period is shown as a linear transmission period in FIG.

FIG. 4 shows a digital signal reproducing / transmitting apparatus 1
A specific example of the mute pattern synchronization processing performed by the above-mentioned during the mute pattern synchronization processing period will be described. From the mute pattern generator 6, {1, 0, 0, 1, 0, 1, 1, 0}
The 1-bit mute pattern signal is generated linearly. On the other hand, the 1-bit mute pattern signal generated by the mute pattern generator 4 repeats the same {1, 0, 0, 1, 0, 1, 0} and is non-linear during data transmission by IEEE1394. Because of transmission, the phases of the output signals of the mute pattern generator 4 and the mute pattern generator 6 do not match, as shown in the nonlinear transmission engine of FIG. In order to switch from data transmission by IEEE1394 to audio signal reproduction from the D / A converter 9, a 1-bit mute pattern generated by the mute pattern generator 4 during the mute pattern synchronization processing period shown in FIG. By controlling the rate of the signals and shifting the phases, the phases of both 1-bit mute pattern signals are matched. If the phases match, then
By linearly operating the mute pattern generator 4, the phases of both 1-bit mute pattern signals can be synchronized as shown in the linear transmission period of FIG.

As described above, during the non-linear transfer to IEEE1394, in order to prevent noise from being generated from the D / A converter 9, a mute pattern is always generated separately from the mute pattern generator 4 used for mute processing of the reproduction signal. I have another system of mute pattern generator 6 to continue, IE
By switching to this side during non-linear transfer to EE1394, it is possible to prevent noise from being generated from the D / A converter output during non-linear transfer to IEEE1394.

If the present invention is not applied, if the mute pattern generator output generated linearly and the mute pattern generator output signal operated non-linearly are switched,
Discontinuity of the mute pattern occurs there, and click noise occurs from the D / A converter output at the switching point. However, by applying the present invention, muting that occurs non-linearly before switching. By controlling the rate and aligning the phases of the output mute pattern of the pattern generator, it is possible to implement switching without switching noise.

In this embodiment, as a linear system, D / A
Although IEEE 1394 is shown as a non-linear system for the converter, other transmission systems may be applied.

As an example of a non-linear clock,
Although a clock having a half cycle is shown, a completely discontinuous asynchronous clock may be used.

[0055]

According to the digital signal transmission device and method of the present invention, a mute pattern generator for linearly generating a mute pattern is provided, and at the time of non-linear transmission output, a mute pattern signal generated linearly from the linear transmission output. By switching to and outputting to, it is possible to output a linear mute pattern from the linear transmission output even during non-linear transfer, and it is possible to realize analog audio signal reproduction without noise.

Further, according to the present invention, when the switching is performed, the phases of the mute patterns on the linear and non-linear sides are controlled to synchronize with each other.
Since the continuity of the signal is maintained even at the time of switching, continuous linear reproduction without instantaneous noise is realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital signal reproducing / transmitting device.

2 is included in the digital signal reproducing and transmitting apparatus 1
It is a figure which shows the detailed structure of a bit signal reproducing device.

FIG. 3 is a timing chart for explaining the operation of the digital signal reproducing / transmitting device.

FIG. 4 is a diagram for explaining a mute pattern synchronization process of the digital signal reproducing / transmitting device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 digital signal reproduction / transmission device, 2 non-linear operable blocks, 3 1-bit signal reproduction device, 4 mute pattern generator (first mute pattern generating means), 5 crossfade device, 6 mute pattern generator (second mute) Pattern generating means), 7 delay line, 8 switching device, 9 D / A converter, 10 IEEE1394 interface, 11 control device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Nobukazu Suzuki             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F-term (reference) 5B077 AA14 BB04 MM02 NN02                 5D044 AB06 BC03 CC06 FG14 FG16                       GK12 GK15 GM23 HL12 HL15                 5J022 AB01 BA02 CA02 CE01 CG01

Claims (7)

[Claims] 1. A first mute signal generating means for generating a 1-bit digital signal of a mute signal pattern, an input 1-bit digital signal and a mute signal pattern of 1 output from the first mute signal generating means. Crossfade processing means for crossfading the bit digital signal and outputting it, second mute signal generating means for generating a 1-bit digital signal of a mute signal pattern, and 1-bit digital signal output from the crossfade processing means And a switching means for switching the 1-bit digital signal of the mute signal pattern generated by the second mute signal generating means, and a D / A conversion for D / A converting the 1-bit digital signal output from the switching means. Means and 1 output from the crossfade processing means Communication processing means for converting a digital signal into a variable transfer rate and transferring the same, and a 1-bit digital signal from the crossfade processing means while outputting from the communication processing means at a variable transfer rate. The switching means is controlled so as to switch the mute signal pattern output from the first mute signal generation means to the mute signal pattern output from the second mute signal generation means at a predetermined timing in order to mute the output. A digital signal processing device comprising a control means. 2. The control means fades out the input 1-bit digital signal by the crossfade processing means and fades in the 1-bit digital signal of the mute signal pattern output from the first mute signal generation means. 2. The digital signal processing device according to claim 1, wherein after the cross-fade processing is performed as described above, the switching means switches to the mute signal pattern output from the second mute signal generating means. 3. The control means is switched from a mode in which the 1-bit digital signal is output from the communication processing means at a variable transfer rate to a mode in which the 1-bit digital signal is output from the D / A conversion means. Is detected, the 1-bit digital signal of the mute signal pattern output from the first mute signal generating means and the mute signal pattern output from the second mute signal generating means are matched in phase to each other. 2. The digital signal processing apparatus according to claim 1, wherein the rate of a reproducing system including a 1-bit digital signal of the mute signal pattern output from the 1 mute signal generating means is controlled. 4. The control means sets the phase of the 1-bit digital signal of the mute signal pattern output from the first mute signal generation means to the phase of the mute signal pattern output from the second mute signal generation means. After the phase is adjusted, the switching means is used to supply the D / A conversion means, and then the crossfade processing means outputs the 1-bit digital signal of the mute signal pattern output from the first mute signal generation means. The D / A while performing cross-fade processing so that the input 1-bit digital signal is faded in.
4. The digital signal processing apparatus according to claim 3, wherein the 1-bit digital signal is supplied to the converting means. 5. The digital signal according to claim 1, wherein the first and second mute signal generating means generate a mute signal which is formed by repeating a pattern using the same number of 1-bit signals 0 and 1. Signal processing device. 6. The first and second mute signal generation means use the same number of 0 and 1 of 1-bit signals, “1,
6. The digital signal processing device according to claim 5, wherein the mute signal is generated by repeating a pattern of "0, 0, 1, 0, 1, 1, 0". 7. A first mute signal generation step of generating a 1-bit digital signal of a mute signal pattern, an input 1-bit digital signal, and a mute signal pattern of 1 output from the first mute signal generation step. A cross-fade processing step of cross-fading the bit digital signal and outputting it, a second mute signal generating step of generating a 1-bit digital signal of a mute signal pattern, and a 1-bit digital signal output from the cross-fade processing step. And a switching step of switching between the 1-bit digital signal of the mute signal pattern generated in the second mute signal generation step, and a D / A conversion step of D / A converting the 1-bit digital signal output from the switching step. And the 1-bit output from the crossfade processing step. A communication processing step of converting the digital signal to a variable transfer rate and transferring the variable transfer rate, wherein the switching step outputs the 1-bit digital signal from the crossfade processing step from the communication processing step at a variable transfer rate. In order to mute the output from the D / A conversion process, the mute signal pattern output from the first mute signal generation process is switched to the mute signal pattern output from the second mute signal generation process at a predetermined timing. A digital signal processing method characterized by being controlled as follows.