JP2000196454A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a signal processor that can vary a digital signal characteristic without the need for an externally mounted mute circuit. SOLUTION: The signal processor is provided with a digital signal processor 120 whose digital signal processor characteristic can be changed in response to a parameter and that is provided with a mute function, which sets/releases muting while smoothly changing an output level, a D/A converter means 160 that applies D/A conversion to digital data that are digitally processed by the digital signal processor 120, and control means (101, 140, 150) that stop a clock to the D/A converter means 160 in a state that the output is nullified through the setting of muting, changes the parameter of the digital signal processor and restart supply of the clock signal to the D/A converter means 160 after the revision of the parameter so as to release the muting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device, and more particularly, to a signal processing device capable of changing digital signal processing characteristics.

[0002]

2. Description of the Related Art Digital signal processors (DS)
In a signal processing device such as P), digital signal processing characteristics are determined according to parameters. Therefore, it is possible to change to a desired signal processing characteristic by changing the parameter.

[0003] In such a digital signal processor, noise is output at the moment when the digital signal processing characteristics are changed by changing the parameters. Therefore, a mute circuit for performing muting is connected to a stage subsequent to the digital signal processor.

[0004]

SUMMARY OF THE INVENTION For the above reasons,
An external mute circuit is required in addition to the digital signal processor. For this reason, an increase in the number of components causes a problem that the device becomes expensive and the area of the circuit increases.

[0005] Even if a function equivalent to an external mute circuit is simply built in the digital signal processor, the parameters for determining the digital signal processing characteristics are switched (the old parameters are cleared and the new parameters are loaded. At the time of switching), noise may be generated, and this noise is output to the outside, so that the problem is not fundamentally solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to realize a signal processing device capable of changing digital signal processing characteristics without requiring an external mute circuit. is there.

[0007]

Accordingly, the invention as a means for solving the problems will be described below. (1) A digital signal having a mute function in which digital signal processing characteristics can be changed according to a parameter and muting can be set and released while smoothly changing an output level. And a D / A converter for D / A converting digital data digitally processed by the digital signal processor.
The output is set to 0 by the / A conversion means and muting setting.
Control means for stopping the clock to the D / A conversion means, changing the parameters of the digital signal processor, restarting the supply of the clock to the D / A conversion means after the parameter change, and canceling the muting. And a signal processing device.

Here, the setting of muting means that the output is reduced from the rated value to 0, and the cancellation of muting means that the output is returned from 0 to the rated value.

In this signal processing device, the output level is smoothly set to 0 by setting muting so that no noise is output, and further, the clock to the D / A converter is stopped to stop the output. Then, the parameters of the digital signal processor are changed in this state. Then, after the parameter is changed, the supply of the clock to the D / A conversion means is resumed, muting is smoothly released, and a signal processed by the digital signal processing characteristics based on the new parameter is output.

Thus, it is possible to realize a signal processing device capable of changing digital signal processing characteristics without requiring an external mute circuit.

(2) The clock for the D / A conversion means is composed of a word clock corresponding to a word of digital data and a bit clock for bits of digital data, and the stop of the clock is the stop of the bit clock. There is a feature.

In this signal processing device, since the operation of the D / A conversion means is stopped by stopping the bit clock, no noise is output to the outside even when the parameters of the digital signal processor are changed.

(3) In stopping or restarting the supply of the clock, a word clock and a bit clock are synchronized. In this signal processing device, the clock supply is stopped or restarted by synchronizing the word clock and the bit clock, so that no noise is generated even when the signal output is restarted after changing the parameters of the digital signal processor. .

(4) The signal processing apparatus according to any one of claims 1 to 3, wherein the digital signal processing characteristic is a characteristic of a noise shaper. In this signal processing device, when changing the parameters of the digital signal processor for changing the characteristics of the noise shaper, the above (1) to (3)
With this configuration, noise is prevented from being output to the outside, and a signal processing device capable of changing digital signal processing characteristics without requiring an external mute circuit can be realized.

Further, as a change of the characteristics of the noise shaper, by turning off the noise shaper in a minute signal area, it is possible to reproduce a music signal in a state that is preferable in terms of audibility.

[0016]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a signal processing device 100 according to the first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a main microcomputer for controlling the entire signal processing device 100; 110, an operation unit for receiving an operation input from a user of the signal processing device 100; The operation input in the operation unit 110 includes a change of a parameter for switching a digital signal processing characteristic, and the result of the operation input is transmitted to the main microcomputer 101.

Numeral 120 denotes a digital signal processor (DSP) having a mute function capable of changing digital signal processing characteristics by changing parameters and setting and canceling muting while smoothly changing an output level. .

130 is a digital signal processor 1
20 is a ROM as data holding means for storing parameter data for determining the digital signal processing characteristics of the digital signal processing device 20, and is configured so that a desired parameter can be read (loaded) by designating an address. I have.

A controller 140 generates a clock enable signal for controlling the supply of a clock.
0 is the clock supply / supply by the clock enable signal.
This is a logic circuit that does not supply. Note that the main microcomputer 101, the controller 140, and the logic circuit 15 described above are used.
0 constitutes the control means of the claims.

Reference numeral 160 denotes a D / A converter for converting digital data into an analog signal, to which a bit clock CLDA and a word clock WSDA are supplied as clocks. The word clock WSDA corresponds to a word of digital data, and the bit clock CLD
A is for bits of digital data. The word clock WSDA is created by a clock generation unit (not shown) or the like, and the bit clock CLDA is determined based on the word clock WSDA.
01.

Hereinafter, the operation of the signal processing apparatus 100 according to the present embodiment will be described with reference to the flowchart of FIG. 2 and the time chart of FIG.

First, it is assumed that an instruction to change the digital signal processing characteristics is made on the operation unit 110, and the instruction is transmitted to the main microcomputer 101. Therefore, a predetermined signal is given to the MUTE terminal of the digital signal processor 120 according to an instruction from the main microcomputer 101, and the output level is smoothly muted by the mute function built in the digital signal processor 120 (FIGS. 2S1 and 3). (A)).

Here, "smoothly changing the level" means, for example, changing the level according to a sine curve or a cosine curve. Note that FIG. 3A shows the characteristics of the mute function, and the normal rated level (=
It is smoothly changed from 1) to 0 level. In this case, the instruction from the CPU 101 is a pulse-like signal (mute on) and the digital signal processor 120
A smooth characteristic may be realized by a mute characteristic curve included in
The instruction may be directly given from the PU 101.

When the output level of the digital signal processor 120 becomes 0 by the above mute function, the CPU 101 sets the control signal CTL to L level (FIG. 3B). In the controller 140 which has received the control signal CTL, the control signal CT
First word clock WSD after L goes to L level
At the change timing of A (FIG. 3C), the clock enable CLEN is set to L level (FIG. 3D).

As a result, the bit clock CLDA from the digital signal processor 120 is
Due to 0, the state is not supplied to the D / A converter 160 (FIG. 3E). As a result, the D / A converter 160 stops operating (S2 in FIG. 2).

The main microcomputer 101 changes the digital signal processing characteristics of the digital signal processor 120 (FIG. 3 (f)).
To the digital signal processor 120 (FIG. 3).
(G)). In the digital signal processor 120,
At the falling edge of the reset pulse RST, the parameters for the digital signal processing characteristics up to that point are cleared (FIG. 3 (g)).

Then, at the rise of the reset pulse RST, the parameters necessary for the designated digital signal processing characteristics are loaded from the ROM 130 (FIG. 2 S3, FIG. 3).
(G)). Thereby, the digital signal processing characteristics of the digital signal processor 120 are changed.

At this point, the D / A converter 160
Since the supply of the bit clock to the digital signal processor is stopped, even if noise is generated from the output at the moment when the characteristic of the digital signal processor 120 is switched, noise does not appear in the analog signal.

Then, the digital signal processor 1
At the point in time when a new parameter has been loaded into the CPU 20 and the normal operation has elapsed, the CPU 101 sets the control signal CTL to the H level (FIG. 3B). In the controller 140 that has received the control signal CTL, the change timing of the first word clock WSDA after the control signal CTL goes high (FIG. 3C).
Then, the clock enable CLEN is returned to the H level (FIG. 3D).

Thus, the bit clock CLDA from the digital signal processor 120 is supplied to the D / A converter 160 in synchronization with the word clock WSDA (FIG. 3 (e)). Since the bit clock and the word clock are synchronized in this manner, the D / A converter 160 can operate normally, and no noise or the like occurs.

As a result, the D / A converter 160 resumes its operation (S4 in FIG. 2). When the operation of the D / A converter 160 is resumed, the digital signal processor 120
Is a normal operation of the digital signal processing characteristics based on the new parameter, but the mute function is set and the output level is set to 0 (FIG. 3 (h)).

Thereafter, according to an instruction from the main microcomputer 101, the MUTE of the digital signal processor 120
A predetermined signal is supplied to the terminal, and muting is smoothly canceled by a mute function built in the digital signal processor 120 (FIG. 2S5, FIG. 3A).
Here, to smoothly change the level means to change the level according to a cosine curve or a sine curve, as described above. Here, the level is smoothly changed from the 0 level to the normal rated level (= 1). In this case, the instruction from the CPU 101 is a pulse signal (mute off), and the digital signal processor 120
A smooth characteristic may be realized by a mute characteristic curve included in
The instruction may be directly given from the PU 101.

By the above series of operations, noise when switching the digital signal processing characteristics of the digital signal processor 120 is not output to the outside, and the analog signal switched to the new digital signal processing characteristics by smooth muting is output. It will be output to the outside. In such an operation, there is no need to use an external mute circuit.

The digital signal processor as described above can perform various digital data signal processing. For example, the digital signal processor is used to change the characteristics of a noise shaper when reproducing digital data from a CD player or DAT. Is possible.

Note that it has conventionally been considered that a noise shaper preferably has linear input and output at all levels.

This situation is shown in N. Shape on in FIG. Here, an example of 44.1 kHz 16-bit quantized digital data is shown. In such a case, the parameter of the digital signal processing characteristic 120 is changed to -82.
By changing the characteristic to slightly increase the output by about 3 dB at the maximum for input less than about dB (N. Shaper off in FIG. 4), it is possible to obtain a result that the perceived depth and sound image localization are improved. Was found in

Accordingly, the signal processing device of the present embodiment is mounted on a digital signal processing portion such as a CD player, and the characteristics of the noise shaper can be changed by changing parameters according to the user's preference. By that
You will be able to play better music.

The parameters are not limited to those previously stored in the ROM, but may be read by a user with a memory card or downloaded via a communication line.

[0040]

As described in detail above, the invention of the signal processing device described in this specification has the following effects.

(1) According to the first aspect of the present invention, the output level is smoothly set to 0 by setting muting so that noise is not output, and further, the clock to the D / A conversion means is stopped to output. Stop. Then, the parameters of the processor are changed in this state. Then, after the parameter is changed, the supply of the clock to the D / A conversion means is resumed, muting is smoothly released, and a signal processed by the digital signal processing characteristics based on the new parameter is output. This allows
A signal processing device capable of changing digital signal processing characteristics without requiring an external mute circuit can be realized.

(2) In the second aspect of the present invention, since the operation of the D / A conversion means is stopped by stopping the bit clock, noise is output to the outside even when the parameters of the processor are changed. There is no.

(3) In the third aspect of the present invention, the clock supply is restarted by synchronizing the word clock and the bit clock. Therefore, noise is generated even when the signal output is restarted after changing the parameters of the processor. I will not do it.

(4) According to the fourth aspect of the present invention, since the above-described configurations (1) to (3) are used in changing the parameters of the processor for changing the characteristics of the noise shaper in the signal processing device, noise is reduced. It is possible to realize a signal processing device that is configured not to output to the outside and that can change digital signal processing characteristics without requiring an external mute circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a main part of a signal processing device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the signal processing device according to the embodiment of the present invention.

FIG. 3 is a time chart illustrating an operation of the signal processing device according to the embodiment of the present invention;

FIG. 4 is a characteristic diagram illustrating an example of digital signal processing characteristics in the signal processing device according to the embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 signal processing device 101 main microcomputer 110 operation unit 120 digital signal processor 130 ROM 140 controller 150 logic circuit 160 D / A converter

Claims (4)

[Claims] A digital signal processor having a mute function capable of changing a digital signal processing characteristic in accordance with a parameter and capable of setting and canceling muting while smoothly changing an output level; D / A conversion means for D / A conversion of digital data digitally processed by the processor, and D / A conversion with the output set to 0 by muting setting.
And control means for stopping the clock to the / A conversion means, changing the parameters of the digital signal processor, and restarting the supply of the clock to the D / A conversion means after the parameter change to cancel muting. Characteristic signal processing device. 2. A clock for the D / A conversion means is composed of a word clock corresponding to a word of digital data and a bit clock for bits of digital data, and the stop of the clock is a stop of the bit clock. The signal processing device according to claim 1, wherein: 3. The signal processing apparatus according to claim 2, wherein the word clock and the bit clock are synchronized when the supply of the clock is stopped or restarted. 4. The signal processing device according to claim 1, wherein the digital signal processing characteristic is a characteristic of a noise shaper.